Last update:
Tue Dec 31 13:29:48 MST 2024
Robert N. Noyce and
Marcian E. Hoff, Jr. A History of Microprocessor Development
at Intel . . . . . . . . . . . . . . . . 8--11, 13--21
H. Troy Nagle, Jr. and
Victor P. Nelson Digital filter implementation on 16-bit
microcomputers . . . . . . . . . . . . . 23--41
V. P. Nelson and
H. T. Nagle, Jr. Digital filtering performance comparison
of 16-bit microcomputers . . . . . . . . 32--41
Paul D. Stigall and
Rodger E. Ziemer and
Van T. Pham A performance study of a
microcomputer-implemented FSK receiver 43--51
Edwin E. Klingman Hierarchical coding of microcomputers
for high-level architecture . . . . . . 53--56
Edwin E. Klingman A Design Philosophy for Microcomputers 58--64
Andrew A. Allison Status-Report on the P896 Backplane Bus 67--69, 71--82
Paul L. Borrill Microprocessor Bus Structures and
Standards . . . . . . . . . . . . . . . 84--95
W. Myers Control Robotic Systems with Distributed
Microprocessors . . . . . . . . . . . . 112--112
Ritchie L. Tabachnick and
Paul J. A. Zsombor-Murray and
Louis J. Vroomen and
Tho Le-Ngoc Sequence controllers with standard
hardware and custom firmware . . . . . . 9--25
Hoo-min D. Toong and
Amar Gupta An architectural comparison of
contemporary 16-bit microprocessors . . 26--37
Takehiko Tomikawa and
Kinji Matsumoto Ink Jet Printing of Japanese Kanji
Characters . . . . . . . . . . . . . . . 39--42, 44--46
Fraser George Duncan Level-Independent Notation for
Microcomputer Programs . . . . . . . . . 47--52
Alfred C. Hartmann and
Scott Fehr A VLSI architecture for software
structure: the Intel 8086 . . . . . . . 57--69
Anonymous A proposed standard for extending
high-level languages for microprocessors 70--75
Victor P. Nelson and
Hugh L. Fellows, Jr. A microcomputer-based controller for an
amusement park ride . . . . . . . . . . 13--22
Steven C. Bass and
Thomas W. Goeddel The efficient digital implementation of
subtractive music synthesis . . . . . . 24--37
Richard V. Orlando and
Thomas L. Anderson An overview of the 9900 microprocessor
family . . . . . . . . . . . . . . . . . 38--44
J. Robert Heath and
Shailesh M. Patel How to write a universal cross-assembler 45--66
T. S. Berman Forget Algebraic Notation . . . . . . . 3--3
Tracy S. Kinsel and
John H. Wuorinen, Jr. A Digital Signal Generator . . . . . . . 6--15
Donald F. Hanson An improved model for a microcomputer
component --- the 6520 PIA . . . . . . . 17--25
Robert Ryan and
George D. Marshall and
Robert Beach and
Steven R. Kerman Intel Local Network Architecture . . . . 26--41
Yaohan Chu and
Paul L. Schapiro Micro-Cobol --- a Data-Processing
Language for Microprocessor Systems . . 43--55
Mike Newman and
David Wayne Smith The MC6809 in DMA Mode on the IEEE-488
Bus . . . . . . . . . . . . . . . . . . 56--66, 68--75
F. G. Duncan Debate Continues on Algebraic Notation 5--5
Richard H. Stern and
Jeffrey L. Squires Can we stop software theft? . . . . . . 13--25
Ware Myers Personal Computers Aid the Handicapped 26--40
Richard Gilbert The General-Purpose Interface Bus . . . 41--51
Wayne M. Loucks and
Martin Snelgrove and
Safwat G. Zaky A Vector Processor Based on One-Bit
Microprocessors . . . . . . . . . . . . 53--62
M. J. McGovern Is ROMed Code Copyrightable After All? 3--6
P. Palamara And Is ROMed Code Really Different from
Source Code . . . . . . . . . . . . . . 6--6
D. A. Fairclough A Unique Microprocessor Instruction Set 8--18
R. C. Jaeger Tutorial: analog data acquisition
technology. I. Digital-to-analog
conversion . . . . . . . . . . . . . . . 20--37
P. Civera and
G. Conte and
D. Del Corso and
F. Gregoretti and
E. Pasero The mu * project: an experience with a
multimicroprocessor system . . . . . . . 38--50
G. Silverman and
A. Stundel and
J. Lehman The modular multiprocessor --- a model
for laboratory instrument design . . . . 51--62
G. D. Taylor and
S. J. McCormick Best Starting Approximations . . . . . . 64--65
W. Myers Compcon Spring 82 . . . . . . . . . . . 81--83
T. Smith The Near-Optimal Instruction Set . . . . 5--7
D. A. Fairclough The Near-Optimal Instruction Set ---
Reply . . . . . . . . . . . . . . . . . 6--7
D. W. Best and
C. E. Kress and
N. M. Mykris and
J. D. Russell and
W. J. Smith An advanced-architecture CMOS/SOS
microprocessor . . . . . . . . . . . . . 10--26
W. Myers Toward a Local-Network Standard . . . . 28--45
R. C. Jaeger Tutorial: analog data acquisition
technology. II. Analog-to-digital
conversion . . . . . . . . . . . . . . . 46--57
T. Le-Ngoc and
L. C. Vroomen Programming strategies in the game of
Push-over . . . . . . . . . . . . . . . 58--68
M. Andrews Mathematical Microprocessor Software: a
sqrt($x$) comparison . . . . . . . . . . 63--79
B. Unger and
D. Bidulock and
G. Lomow and
P. Belanger and
C. Hankins and
N. Jain An OASIS simulation of the ZNET
microcomputer network . . . . . . . . . 70--84
R. Hariharan and
V. D. Kulkarni A Microprocessor-Based Pulse-Height
Analyzer . . . . . . . . . . . . . . . . 86--91
R. D. Teachey Square-Root-X Comparison --- New Results
Discovered . . . . . . . . . . . . . . . 5--6
M. Andrews Square-Root-X Comparison --- New Results
Discovered --- Reply . . . . . . . . . . 5--6
J. W. Crenshaw More on Instruction Sets . . . . . . . . 6--6
M. D. Shapiro Errors Detected in Caps Programmers Card 6--6
D. A. Patterson and
R. S. Piepho Assessing RISCs in High Level Language
Support . . . . . . . . . . . . . . . . 9--19
R. C. Jaeger Tutorial: analog data acquisition
technology. III. Sample-and-holds,
instrumentation amplifiers, and analog
multiplexers . . . . . . . . . . . . . . 20--35
N. M. Abo El Naga and
J. A. Field A Hardware Algol Machine . . . . . . . . 37--47
Y. Okada and
H. Tajima and
R. Mori A reconfigurable parallel processor with
microprogram control . . . . . . . . . . 48--60
P. D. Stigall and
R. E. Ziemer and
L. Hudec A Performance Study of 16-Bit
Microcomputer-Implemented FFT Algorithms 61--66
K. Eckert A Multiprocessor Interface . . . . . . . 67--70
W. Myers Local-Network Standard on Track . . . . 74--76
Amar Gupta and
Hoo-min D. Toong An Architectural Comparison of 32-Bit
Microprocessors . . . . . . . . . . . . 9--22
Richard H. Stern Micro Law: Can software be tied to
hardware? Part I . . . . . . . . . . . . 23--33
Magdy S. Abadir and
Hassan K. Reghbati LSI Testing Techniques . . . . . . . . . 34--51
R. C. Jaeger Tutorial: analog data acquisition
technology. IV. System design, analysis,
and performance . . . . . . . . . . . . 52--61
P. J. McKerrow Microcomputers, Slotcars, and Education 62--65
E. Skordalakis Meta-assemblers . . . . . . . . . . . . 6--16
Richard H. Stern Micro Law: Can Software Be Tied to
Hardware? Part II . . . . . . . . . . . 17--25
Martin De Prycker A performance comparison of three
contemporary 16-bit microprocessors . . 26--37
Andre M. van Tilborg and
Larry D. Wittie Operating systems for the Micronet
network computer . . . . . . . . . . . . 38--47
Philip C. Dennis A Heuristic Routing Algorithm . . . . . 48--54
J. H. Aylor and
E. L. Johnson Guest Editors' Introduction ---
Microcomputing to Aid the Handicapped. 1 6--7
Clifford P. Grossner and
Thiruvengadam Radhakrishnan and
Andy Pospiech An integrated workstation for the
visually handicapped . . . . . . . . . . 8--16
Craig W. Heckathorne and
Dudley S. Childress Applying anticipatory text selection in
a writing aid for people with severe
motor impairment . . . . . . . . . . . . 17--23
Douglas MacGregor and
David S. Mothersole Virtual Memory and the MC68010 . . . . . 24--39
Aram Perez Byte-Wise CRC Calculations . . . . . . . 40--50
David B. Gustavson and
John Theus Wire-OR Logic on Transmission-Lines . . 51--55
H. Hecht Publication Creates de-Facto Standards
Without Proper Review . . . . . . . . . 57--58
D. B. Gustavson and
T. Pittman and
M. Smolin and
R. G. Stewart Publication Is Timely and Democratic . . 58--60
R. H. Stern Micro Law: a Proposal for a System of
Computer Software Protection . . . . . . 61--65
C. M. Mathias Computer Software Protection Law ---
Technical Expertise Needed . . . . . . . 5--6
Peter J. Nelson and
Larry Korba and
Gordon Park and
David Crabtree The MOD keyboard (modified keyboard) . . 7--17
David Lunney and
Robert C. Morrison and
Margaret M. Cetera and
Richard V. Hartness and
Raymond T. Mills and
Alger D. Salt and
David C. Sowell A Microcomputer-Based Laboratory Aid for
Visually Impaired Students . . . . . . . 19--31
Hubert Kirrmann Data Format and Bus Compatibility in
Multiprocessors . . . . . . . . . . . . 32--47
Anonymous The microprocessor universal format for
object modules --- proposed standard . . 48--66
Paul J. A. Zsombor-Murray and
Louis J. Vroomen and
Robert D. Hudson and
Tho Le-Ngoc and
Peter H. Holck Binary-Decision-Based Programmable
Controllers. Part I . . . . . . . . . . 67--78, 81--83
W. Myers Deaf to Get Microprocessor-Based
Autocuer . . . . . . . . . . . . . . . . 84--85
Richard H. Stern Micro Law . . . . . . . . . . . . . . . 88--92
C. Müller-Schloer A Microprocessor-Based Cryptoprocessor 5--15
Paul J. A. Zsombor-Murray and
Louis J. Vroomen and
Robert D. Hudson and
Peter H. Holck and
Tho Le-Ngoc Binary-decision-based programmable
controllers. II . . . . . . . . . . . . 16--26
W. Thomas Adams and
John Brady Magnitude approximations for
microprocessor implementation . . . . . 27--31
Eli T. Fathi and
Moshe Krieger An Executive for Task-Driven
Multimicrocomputer Systems . . . . . . . 32--41
David K. Kahaner and
Webb L. Wyman Mathematical Software in Basic:
Evaluation of Definite Integrals . . . . 42--46
J. Isaak What Defines a 32-Bit Microprocessor? 3--6
P. Grogono Copyrighting of IEEE Standards
Challenged . . . . . . . . . . . . . . . 4--4
H. Kirrmann What Defines a 32-Bit Microprocessor?
--- Reply . . . . . . . . . . . . . . . 4--4
H. Hecht Copyrighting of IEEE Standards
Challenged . . . . . . . . . . . . . . . 4
D. Edwards Fighting the Chip Pirates . . . . . . . 5--6
Hideo Maejima and
Koyo Katsura and
Hideo Nakamura and
Toshimasa Kihara The VLSI control structure of a CMOS
microcomputer . . . . . . . . . . . . . 9--16
Trevor G. Marshall and
John A. Attikiouzel Floppy Disk Data Transfer Techniques . . 17--23
Paul J. A. Zsombor-Murray and
Louis J. Vroomen and
Robert D. Hudson and
Peter H. Holck and
Tho Le-Ngoc Binary-decision-based programmable
controllers. III . . . . . . . . . . . . 24--39
David M. Abrahamson A fast entry path into user microcode on
the VAX-11/780 . . . . . . . . . . . . . 40--43
Clayton Huntsman and
Duane Cawthron The MC68881 Floating-Point Coprocessor 44--54
W. Myers Language Translator Runs on As Little As
64K . . . . . . . . . . . . . . . . . . 64--68
W. Myers Single-Chip 32-Bit Microprocessors
Arriving . . . . . . . . . . . . . . . . 65
T. Paterson Data Format and the S-100 Bus . . . . . 11--14
H. Kirrmann Data Format and the S-100 Bus --- Reply 11--14
E. Zschau A National Policy to Maintain United
States Technological Leadership . . . . 12--14
L. R. Morris Price, Derek, Desolla and the
Antikythera Mechanism --- An
Appreciation 1922--1983 --- Obituary . . 15--21
Derek de Solla Price A History of Calculating Machines . . . 22--52
James M. Sibigtroth Motorola's MC68HC11: Definition and
design of a VLSI microprocessor . . . . 54--65
Ernst J. Schmitter and
Peter Baues The Basic Fault-Tolerant System . . . . 66--74
W. Myers Additional 32-Bit Microprocessors
Reported . . . . . . . . . . . . . . . . 75--81
W. Myers Active Interconnections Enable Parallel
Microprocessors to Manage Vast
Relational Database . . . . . . . . . . 76--79
T. G. Marshall Correction . . . . . . . . . . . . . . . 78--78
J. Nelson Correction . . . . . . . . . . . . . . . 78--78
W. Myers Concurrent Microprocessors Are
Cost-Effective for Scientific Problems 79
R. H. Stern Micro Law: What Is the Function of an
Operating System? . . . . . . . . . . . 80--81
R. G. Stewart P854 Working Group Completes
Radix-Independent Floating-Point Draft 82--83
G. Baldwin Status-Report P694 Microprocessor
Assembly Language . . . . . . . . . . . 83--83
D. L. Hannum HP Opts for Compatibility . . . . . . . 84--85
M. F. Smith and
B. E. Luff Automatic assembler source translation
from the Z80 to the MC6809 . . . . . . . 3--9
Paul D. Stigall and
Brian E. Lenharth A Microprocessor-Controlled Message
Display System . . . . . . . . . . . . . 10--25
Colin B. Hunter and
Erin Farquhar Introduction to the NS16000 Architecture 26--47
Daniel Tabak Dynamic Architecture and LSI Modular
Computer Systems --- a Review of
``Designing and Programming Modern
Computers and Systems, Volume I --- LSI
Modular Computer Systems'' . . . . . . . 48--66
R. H. Stern Micro Law: More on the Copyright
Controversy --- Who Owns Software . . . 69--70
W. Myers Standards Are Our Friends, Gordon Bell
Says . . . . . . . . . . . . . . . . . . 71--71
J. R. Goodman Microprocessors Defy Classification . . 3--6
H. Kirrmann Microprocessors Defy Classification ---
Reply . . . . . . . . . . . . . . . . . 3--6
N. Mineta Factors of Production . . . . . . . . . 4--6
Borivoje Furht and
Peter Lee An efficient software driver for Am9511
arithmetic processor implementation . . 7--19
Walter S. Heath A system executive for real-time
microcomputer programs . . . . . . . . . 20--32
Anonymous P959 I/O Expansion Bus --- Proposed
Standard . . . . . . . . . . . . . . . . 33--54
Peter U. Schulthess A Reduced High-Level-Language
Instruction Set . . . . . . . . . . . . 55--67
P. Borrill and
R. G. Stewart Standards --- Guest Editors'
Introduction . . . . . . . . . . . . . . 3--6
David B. Gustavson Computer Buses --- a Tutorial . . . . . 7--22
R. V. Balakrishnan The proposed IEEE 896 Futurebus --- a
solution to the bus driving problem . . 23--27
D. M. Taub Arbitration and control acquisition in
the proposed IEEE 896 Futurebus . . . . 28--41
Paul Borrill and
John Theus An advanced communication protocol for
the proposed IEEE 896 Futurebus . . . . 42--56
Fletcher J. Buckley The IEEE Software Engineering Standards
Process . . . . . . . . . . . . . . . . 57--62
Don L. Jackson and
Jack Cowan The proposed IEEE 855 microprocessor
operating systems interface standard . . 63--71
Tim Elsmore and
William R. Shields The proposed IEEE 1000 microcomputer
system bus standard . . . . . . . . . . 72--80
Geoff Baldwin Towards an Assembly Language Standard 81--85
William J. Cody, Jr. and
Jerome T. Coonen and
David M. Gay and
K. Hanson and
David G. Hough and
William Kahan and
Richard Karpinski and
John F. Palmer and
Frederic N. Ris and
David Stevenson A Proposed Radix- and
Word-length-independent Standard for
Floating-Point Arithmetic . . . . . . . 86--100
Doug MacGregor and
Dave Mothersole and
Bill Moyer The Motorola MC68020 . . . . . . . . . . 101--118
J. Ryshpan The MC68020 --- Corrections and
Comparisons . . . . . . . . . . . . . . 3--6
D. Macgregor The MC68020 --- Corrections and
Comparisons --- Reply . . . . . . . . . 3--6
J. D. Nicoud Advances in Microcomputer Peripherals
--- Introduction . . . . . . . . . . . . 7--8
Andrew Allison Microcomputer Peripherals --- Status and
Trends . . . . . . . . . . . . . . . . . 9--17
Roy J. Lahr The Non-Death of Paper . . . . . . . . . 18--25
P. D. Noakes and
R. Aish A new peripheral for three-dimensional
computer input . . . . . . . . . . . . . 26--35
Wolfgang Doster and
Richard Oed Word processing with on-line script
recognition . . . . . . . . . . . . . . 36--43
Ernst Habekotte and
Stefan Cserveny A Smart Digital-Readout Circuit for a
Capacitive Microtransducer . . . . . . . 44--54
James J. Farrell III The advancing technology of Motorola's
microprocessors and microcomputers . . . 55--63
R. H. Stern Micro Law: 9th Circuit Overturns Data
General Decision, Rules That
Software-Hardware Tie-in Is Illegal per
Se . . . . . . . . . . . . . . . . . . . 66--67
J. A. Humphry Fault Tolerance and Micros in the Real
World . . . . . . . . . . . . . . . . . 3--5
Barry W. Johnson Fault-Tolerant Microprocessor-Based
Systems . . . . . . . . . . . . . . . . 6--21
William F. McGill and
Steven E. Smith Fault Tolerance in Continuous
Process-Control . . . . . . . . . . . . 22--33
Richard Emmerson and
Michael J. McGowan Fault Tolerance Achieved in VLSI . . . . 34--43
C. S. Raghavendra Fault Tolerance in Regular Network
Architectures . . . . . . . . . . . . . 44--53
Cedric V. W. Armstrong and
Eli T. Fathi A Fault-Tolerant
Multimicroprocessor-Based
Computer-System for Space-Based
Signal-Processing . . . . . . . . . . . 54--65
Theodore J. Williams The development of reliability in
industrial control systems . . . . . . . 66--80
R. Jeffries PC Stat Packages (Reprinted from the
Jeffries Report, Vol 3, 1984) . . . . . 81--83
R. H. Stern Micro Law: Copy-Protection-Defeating
Programs --- Should Congress Act? . . . 84--85
J. H. Chafee Congress Enacts Its High-Tech Agenda . . 3--6
Richard E. Wainwright and
Randy H. Moss A Microcomputer-Based Model Robot System
with Pulse-Width Modulation Control . . 7--21
Malcolm C. Harrison and
Owen Smith The Ampos multiprocessor --- a computer
system for laboratory use . . . . . . . 22--30
Wayne Fischer IEEE P1014 --- a standard for the
high-performance VME bus . . . . . . . . 31--41
Thiruvengadam Radhakrishnan and
Clifford P. Grossner Cuenet --- a Distributed Computing
Facility . . . . . . . . . . . . . . . . 42--52
Hubert Kirrmann Events and Interrupts in Tightly Coupled
Multiprocessors . . . . . . . . . . . . 53--66
T. Byles and
W. Myers Software Tool AIDS Problem-Solving . . . 67--71
W. Myers The AT&T Personal Computer-6300 . . . . . 68--71
P. Leahy Electronic Data Communications Privacy 4--5
Neng Fred Yao The Computer-Aided Programming System
--- a Friendly Programming Environment 9--19
Donald F. Hanson and
Peggy Cook Power Electronic scanners with speech output
--- a communication system for the
physically handicapped and mentally
retarded . . . . . . . . . . . . . . . . 20--52
Alberto Faro and
Orazio Mirabella and
Lorenzo Vita A Multimicrocomputer-Based Structure for
Computer Networking . . . . . . . . . . 53--66
D. V. Shouse `On the fly' CRC-16 byte-wise
calculation for 8088-based computers . . 67--75
David K. Kahaner and
Jeffrey Horlick and
Webb L. Wyman Mathematical software in BASIC-DINT:
data integration . . . . . . . . . . . . 76--82
R. G. Stewart In Search of Excellence in High
Technology Companies . . . . . . . . . . 86--87
R. H. Stern Micro Law: Source Code Difference No
Protection Against Infringement Suit . . 88--91
R. H. Stern Micro Law: Is Microcode Hardware or
Software? . . . . . . . . . . . . . . . 89--91
W. Myers PFS --- Write Version-B . . . . . . . . 92--94
D. B. Gustavson More on Big-Endian vs Little-Endian Byte
Ordering . . . . . . . . . . . . . . . . 4--4
W. Lunscher Semaphore Strategy for Z80 . . . . . . . 4--4
James J. Farrell III Large-Scale Cost-Effective Packaging . . 5--10
Brian E. Corrigan and
Everett L. Johnson An Evaluation of 8085-Based
Multiprocessing on a Timeshared Bus . . 11--21
Eric H. Stelzer and
Randy H. Moss A microcomputer-based control system for
a three-joint robot arm . . . . . . . . 22--40
Chuck Hastings Second-sourcing CPUs --- emulation,
ethics, and electropolitics . . . . . . 41--52
Jackie Marsh and
James J. Farrell III Motorola's Silver Quill program . . . . 53--57
D. Mange and
E. Sanchez and
A. Thayse and
Paul J. A. Zsombor-Murray and
L. J. Vroomen and
R. Hudson and
T. Le-Ngoc and
Darryl J. Stewart Binary-decision-based programmable
controllers . . . . . . . . . . . . . . 58--72
P. J. Zsombormurray and
L. J. Vroomen and
R. Hudson and
T. Lengoc Comments on Binary-Decision-Based
Programmable Controllers --- Reply . . . 60--63
P. J. Zsombormurray and
L. J. Vroomen Logical Choice and the Discriminating
Designer . . . . . . . . . . . . . . . . 63--68
D. J. Stewart Logical Choice and the Discriminating
Designer . . . . . . . . . . . . . . . . 68--70
P. J. Zsombormurray and
L. J. Vroomen and
R. Hudson Logical Choice and the Discriminating
Designer --- Reply . . . . . . . . . . . 71--72
R. H. Stern Micro Law: Proprietary Rights in Cell
Libraries . . . . . . . . . . . . . . . 73--78
D. L. Hannum Juki Model 6300 Daisywheel Printer . . . 79--82
R. G. Stewart 8 Long Years \ldots But Success at Last 80--82
R. Landry What Is an Engineering Workstation? . . 83--85
R. Landry Micromouse Squeaks at Microprocessor
Forum . . . . . . . . . . . . . . . . . 84--84
Jonathan Rose and
Wayne Loucks and
Zvonko Vranesic Fermtor --- a Tunable Multiprocessor
Architecture . . . . . . . . . . . . . . 5--17
Frits van der Linden and
Ian Wilson An Interactive Debugging Environment . . 18--31
E. Pearse O'Grady and
Raul Lozano A performance study of mutual
exclusion/synchronization mechanisms in
an IEEE 796 bus multiprocessor . . . . . 32--47
Daniel A. Crowl A Real-Time Fortran Executive . . . . . 48--66
M. F. Smith and
Yigal Hoffner and
Mark A. Sealey Mapping High-Level Syntax and Structure
into Assembly Language . . . . . . . . . 67--81
H. Kirrmann Report on the Paris Multibus-II Meeting
and Some Thoughts About the Future of
the Committee . . . . . . . . . . . . . 82--89
R. H. Stern Micro Law: Further Chip Rights
Developments . . . . . . . . . . . . . . 90--92
F. J. Buckley August Microstandards Brings Comments 4, 93
T. Cain and
D. Hannum and
J. Aylor and
B. Stewart and
D. Jaeger Review Referee States Concerns . . . . . 5
D. O. Knight The Engineering Workstation and the
Engineering Support System --- Present
Status, Future-Directions ---
Introduction . . . . . . . . . . . . . . 6--9
Mike Merritt and
Bob Cavett and
Lou Fields and
Dick Kaplan and
Tom Lazear and
Don Miller and
Brice Carnahan and
Dave Bray and
Harry Lundgren and
Mark Turnquist and
Gary Whitehouse Desires and Aspirations of the
Engineering Support System User . . . . 10--17
Les Holland and
Granino Korn and
John Matson and
Bob Seader and
Phil Wolfe Engineering Support System Software . . 17--21
Don Knight and
Mikel J. Harry and
Jim Howard and
Juan Rivero Engineering Support Systems for
Engineering Managers . . . . . . . . . . 22--26
Duncan Mellichamp and
Dave Bedworth and
Odd Pettersen and
Peter Rony and
Lew Bezanson and
Walter Higgins and
Granino Korn Real-Time Computing and the Engineering
Support System . . . . . . . . . . . . . 27--35
Llewellyn Bezanson and
Louis G. Fields and
Donald O. Knight and
Michael J. Merritt and
Bruce R. Millard and
Donald S. Miller and
Peter R. Rony Engineering Support System User
Requirements . . . . . . . . . . . . . . 36--51
Neal K. Riedel and
David A. McAninch and
Cameron Fisher and
Nahum B. Goldstein A signal processing implementation for
an IBM-PC-based workstation . . . . . . 52--67
Esther R. Marx EDIF: the standard for workstation
intercommunication . . . . . . . . . . . 68--75
P. L. Borill The 32-Bit Bus Standards Issue Revisited 76--84
W. T. Higgins Turning a PC into an Engineering
Workstation --- 2 Approaches . . . . . . 80--84
R. N. Noyce Action on Imports Needed Now . . . . . . 85--85
Anonymous Reader Interest Survey . . . . . . . . . 85--85
S. Kartashev Review Referee States Concerns --- Reply 91--93
Khaled A. El-Ayat and
Rakesh K. Agarwal The Intel 80386 --- Architecture and
Implementation . . . . . . . . . . . . . 4--22
David Phillips The Z80000 Microprocessor . . . . . . . 23--36
Steven G. Morton and
Enrique Abreu and
Fred Tse ITT Cap --- Toward a Personal
Supercomputer . . . . . . . . . . . . . 37--49
Doug MacGregor and
Jon Rubinstein A Performance Analysis of MC68020-Based
Systems . . . . . . . . . . . . . . . . 50--70
Paul L. Borrill MicroStandards special feature --- a
comparison of 32-bit buses . . . . . . . 71--79
R. H. Stern Answers to Readers Questions . . . . . . 86--88
I. McIntosh What's New? . . . . . . . . . . . . . . 88--88
M. F. Smith What's New? --- Reply . . . . . . . . . 88--88
P. B. Wettersten America's Trade-Policy . . . . . . . . . 4--6
G. Smith Assembler Study Praised . . . . . . . . 4--6
M. F. Smith Assembler Study Praised --- Reply . . . 5--5
J. Williams When is a von Neumann not a von Neumann? 5--6
A. Busigin FFT Software for the IBM PC . . . . . . 6--6
C. T. Dorcey When is a von Neumann not a von Neumann? 6--6
Giovanni Neri and
Tullio Salmon Cinotti The Modiac Multiprocessor --- a
286-Based Design . . . . . . . . . . . . 7--15
David Gabbay and
Joseph Appelbaum The design of a DC/AC inverter with the
MC68HC11 microcomputer . . . . . . . . . 16--23
Daniel A. Mange A high-level-language programmable
controller. I. A controller for
structured microprogramming . . . . . . 25--41
Henriecus Koeman Application-Specific IC Design
Technologies --- a System Designers
Overview . . . . . . . . . . . . . . . . 42--50
James H. Aylor and
Barry W. Johnson and
Bruce J. Rector Structured design for testability in
semicustom VLSI . . . . . . . . . . . . 51--58
John F. Stockton Megacells . . . . . . . . . . . . . . . 59--67
R. H. Stern Micro Law: Protecting Semicustom Chips 72--76
L. R. Morris Good FFT Software Stretches Processor
Performance . . . . . . . . . . . . . . 4--5
N. K. Riedel and
C. Fisher and
N. B. Goldstein and
D. A. McAninch Good FFT Software Stretches Processor
Performance --- Reply . . . . . . . . . 5--5
Moshe Gavrielov and
Lev Epstein The NS32081 Floating-Point Unit ---
Architecture and Implementation . . . . 6--12
Brad Cohen and
Ralph McGarity The design and implementation of the
MC68851 paged memory management unit . . 13--28
Michael L. Fuccio and
Benjamin Ng Hardware architecture considerations in
the WE32100 chip set . . . . . . . . . . 29--46
Daniel A. Mange A high-level-language programmable
controller. II Microcompilation of the
high-level language Micropascal . . . . 47--63
R. H. Stern Micro Law: The Look, Feel, Taste, and
Smell of Software . . . . . . . . . . . 64--65
S. Prital The VME Subsystem Bus . . . . . . . . . 66--71
J. D. Marr Von Neumann Versus Microcoding . . . . . 5--5
A. R. Miller 1986 --- The Year of Networking . . . . 6--7
Sunil P. Joshi High-Performance Networks --- a Focus on
the Fiber Distributed Data Interface
(FDDI) Standard . . . . . . . . . . . . 8--14
Rhonda Alexis Dirvin and
Arthur R. Miller The MC68824 token bus controller: VLSI
for the factory LAN . . . . . . . . . . 15--25
Paolo Corsini and
Cosimo Antonio Prete Multibug: Interactive Debugging in
Distributed Systems . . . . . . . . . . 26--33
Beatrice Lazzerini and
Cosimo Antonio Prete and
Lanfranco Lopriore A Programmable Debugging Aid for
Real-Time Software Development . . . . . 34--42
Clifford P. Grossner and
Thiruvengadam Radhakrishnan and
Alex Schena An intelligent Braille display device 43--51
David K. Kahaner and
Jeffrey Horlick and
Debra K. Foer Mathematical software in BASIC: RV,
generation of uniform and normal random
variables . . . . . . . . . . . . . . . 52--60
T. W. Curtis and
Paul Allison and
James A. Howard A CORDIC Processor for Laser Trimming 61--71
Michael D. Rap and
R. Scott Tetrick Microstandards --- P1296: the
interprocessor communication standard 72--77
Anonymous MicroCourses . . . . . . . . . . . . . . 78--78
D. A. Mange Correction . . . . . . . . . . . . . . . 78--78
R. H. Stern Micro Law: Reverse Engineering of Chips.
1. The Legislative Background . . . . . 79--83
C. Sen Design Case-Study . . . . . . . . . . . 4, 79
V. K. L. Huang and
P. M. Lu Operating-Systems --- Introduction . . . 6--7
James F. Ready VRTX: a Real-Time Operating System for
Embedded Microprocessor Applications . . 8--17
William A. Jackson and
Paul C. Rogers and
Robert J. Hearn and
Jeffrey S. Mattiace Performance and availability in a
network file server . . . . . . . . . . 18--34
Eric J. Berglund An Introduction to the V-System . . . . 35--52
Thayne C. Cooper and
Wayne D. Bell and
Frank C. Lin and
Norm J. Rasmussen A Benchmark Comparison of 32-Bit
Microprocessors . . . . . . . . . . . . 53--58
R. H. Stern Micro Law: Reverse Engineering of Chips.
2. A Case Example . . . . . . . . . . . 59--75
R. G. Stewart Microstandards --- Promises, Promises,
Promises . . . . . . . . . . . . . . . . 66--68
R. Bronson CRC Revisited . . . . . . . . . . . . . 79--79
J. Farrell Benchmarks (Continued\ldots) . . . . . . 3--3
B. W. Johnson Multiprocessing . . . . . . . . . . . . 5--5
John P. Hayes and
Trevor Mudge and
Quentin F. Stout and
Stephen Colley and
John Palmer A Microprocessor-Based Hypercube
Supercomputer . . . . . . . . . . . . . 6--17
Jean-Luc Gaudiot and
Michel Dubois and
Liang-Teh Lee and
Nadim G. Tohme The TX 16: a highly programmable
multi-microprocessor architecture . . . 18--31
James M. Butler and
A. Yavuz Oruc A Facility for Simulating
Multiprocessors . . . . . . . . . . . . 32--44
Marc A. Baker and
Vincent J. Coli The PAL20RA10 story --- the
customization of a standard product . . 45--60
R. H. Stern Micro Law: Field-Programmable Logic
Devices --- Are They Hardware or
Software --- Can Their Programmed
Configurations Be Protected Against
Copying . . . . . . . . . . . . . . . . 61--78
M. D. Smolin Microstandards . . . . . . . . . . . . . 63--64
A. Allison Bus Wars . . . . . . . . . . . . . . . . 5--5
M. Taub Bus Wars . . . . . . . . . . . . . . . . 5--5
R. G. Stewart Bus Wars --- Response . . . . . . . . . 5
L. R. Morris Digital Signal-Processing
Microprocessors --- Forward to the Past 6--8
Gene A. Frantz and
Kun-Shan Lin and
Jay B. Reimer and
Jon Bradley The Texas Instruments TMS320C25 digital
signal microcomputer . . . . . . . . . . 10--28
Kevin L. Kloker The Motorola DSP56000 Digital Signal
Processor . . . . . . . . . . . . . . . 29--48
John P. Roesgen The ADSP-2100 DSP Microprocessor . . . . 49--59
Bill Eichen NEC's Mu-Pd77230 Digital Signal
Processor . . . . . . . . . . . . . . . 60--69
R. H. Stern Micro Law: Software Copyright
Developments . . . . . . . . . . . . . . 74--79
M. Smolin Publish and or Perish (or, Who Wants to
Use a Trial-Use Standard?) . . . . . . . 80--80
Anonymous Reader Interest Survey . . . . . . . . . 80--80
A. Allison IEEE Standards During the Great Bus Wars
--- Another View . . . . . . . . . . . . 82--83
F. J. Buckley Standards and Lances . . . . . . . . . . 2--2
G. A. Hill Change the Approach of Microstandards 4--4
Reinhard Maenner and
Richard L. Shoemaker and
Peter H. Bartels The Heidelberg Polyp System . . . . . . 5--13
Kin Fun Li and
Nikitas J. Dimopoulos and
J. William Atwood The HM-Nucleus: distributed kernel
design for the Homogeneous
Multiprocessor . . . . . . . . . . . . . 14--24
Anna S. Melamed Performance analysis of Unix-based
network file systems . . . . . . . . . . 25--38
H. Van der Auweraer and
R. Snoeys FFT implementation alternatives in
advanced measurement systems . . . . . . 39--49
Steve L. Landry `Designer' logic and symbols with logic
cell arrays . . . . . . . . . . . . . . 51--59
Kevin J. McNeley and
Veljko M. Milutinovic Emulating a complex instruction set
computer with a reduced instruction set
computer . . . . . . . . . . . . . . . . 60--72
R. H. Stern Micro Law: Legal Mythology, or
Micromyths . . . . . . . . . . . . . . . 73--75
M. Smolin Microstandards . . . . . . . . . . . . . 76--77
D. L. Hannum Graphics Packages for the PC and
Compatibles --- 2 of the Best . . . . . 78--79
Anonymous Hughes Develops 18-GHz IC . . . . . . . 80--83
Anonymous Chips --- Lasers = New-Generation Wave
Devices Systems . . . . . . . . . . . . 81--81
Anonymous ISDN Field-Tests in Process . . . . . . 81--81
Anonymous Homebrewers Disband . . . . . . . . . . 82--82
Anonymous Hardening Material Protects Computers 82--82
Anonymous Map Network Tested . . . . . . . . . . . 82--82
Anonymous Wafer Sharing --- Slicing Costs While
Experimenting . . . . . . . . . . . . . 82--82
J. Farrell An Open-Letter to Austin . . . . . . . . 3--91
K. Sakamura Looking into the Future with Tron . . . 4--6
Ken Sakamura The Tron Project . . . . . . . . . . . . 8--14
Ken Sakamura Architecture of the Tron VLSI CPU . . . 17--31
Toshikazu Ohkubo and
Tetsuo Wasano and
Ichizo Kogiku Configuration of the Ctron Kernel . . . 33--44
Hiroshi Monden Introduction to ITRON --- the
industry-oriented operating system . . . 45--52
Ken Sakamura Btron --- The Business-Oriented
Operating System . . . . . . . . . . . . 53--65
Arno J. H. M. Peels Designing digital systems --- SSI and
MSI vs. LSI and VLSI . . . . . . . . . . 66--80
R. H. Stern Micro Law: Microcode Revisited ---
Further Implications of the NEC vs Intel
Case --- Microcode, Instruction Sets,
and Compatibility . . . . . . . . . . . 81--92
M. Smolin Rebuttal --- Them Windmills Got Teeth 90--91
Yousif A. El-Imam A Personal Computer-Based Speech
Analysis and Synthesis System . . . . . 4--21
G. J. Dekker and
A. J. van de Goor AMORE --- address mapping with
overlapped rotating entries . . . . . . 22--34
Paolo Corsini and
Lanfranco Lopriore The Architecture of a Capability-Based
Microprocessor System . . . . . . . . . 35--51
D. Matthew Taub Improved control acquisition scheme for
the IEEE 896 Futurebus . . . . . . . . . 52--62
John C. McCallum and
Tat-Seng Chua A synthetic instruction mix for
evaluating microprocessor performance 63--80
R. H. Stern Micro Law: Software Copyright
Developments . . . . . . . . . . . . . . 81--89
K. Majithia The New Generation of Microprocessors 4--5
C. B. Hunter Introduction to the Clipper Architecture 6--26
M. Johnson System Considerations in the Design of
the AM29000 . . . . . . . . . . . . . . 28--41
D. Perlmutter and
A. K. W. Yuen The 80387 and Its Applications . . . . . 42--57
S. Iacobovici and
C. C. Ng VLSI and System Performance Modeling . . 59--72
M. A. Sanamrad and
K. Wada and
H. Matsumoto A Hardware Syntactic Analysis Processor 73--80
D. Delcorso and
K. E. Grosspietsch European Approaches for Advanced
Architectures . . . . . . . . . . . . . 4--5
Derek J. McLauchlan European cooperation in the information
technology industry . . . . . . . . . . 6--9
Mark Homewood and
David May and
David Shepherd and
Roger Shepherd The IMS T800 transputer . . . . . . . . 10--26
Hubert D. Kirrmann Fault Tolerance in Process-Control ---
An Overview and Examples of European
Products . . . . . . . . . . . . . . . . 27--50
Wim J. H. J. Bronnenberg and
Loek Nijman and
Eddy A. M. Odijk and
Rob A. H. van Twist DOOM --- a Decentralized Object-Oriented
Machine . . . . . . . . . . . . . . . . 52--69
Giancarlo Micheletti and
Claudio Salati A Low-Cost Distributed Architecture for
Telecommunication Systems . . . . . . . 70--82
Raymond Vachss The Cordic Magnification Function . . . 83--84
R. H. Stern Micro Law: Software Models of Hardware 85--89
M. Smolin MicroStandards --- more on IEEE
standards generation . . . . . . . . . . 92--94
Richard Mateosian Producing Technical Papers . . . . . . . 4, 89
C. Miller Neurocomputing --- a New
Information-Processing Paradigm . . . . 6, 91
Barbara A. Naused and
Barry K. Gilbert A 32-Bit, 200-MHz GaAs RISC for
High-Throughput Signal-Processing
Environments . . . . . . . . . . . . . . 8--20
Eli T. Fathi and
Eloi Bosse and
Jean Caseault A Distributed System for Real-Time
Applications . . . . . . . . . . . . . . 21--28
Eduardo Sanchez and
Patrick Sommer and
Jacques Menu and
Christian Iseli A General Heap Processor . . . . . . . . 29--40
Reinhard Maenner A Fast Integer Binary Logarithm of Large
Arguments . . . . . . . . . . . . . . . 41--45
Thomas L. Sterling and
Albert J. Musciano and
Ellery Y. Chan and
Douglas A. Thomae Effective implementation of a parallel
language on a multiprocessor . . . . . . 46--62
Robert E. Jenkins and
D. Gilbert Lee, Jr. An Application-Specific Coprocessor for
High-Speed Cellular Logic Operations . . 63--70
Walter S. Heath Software design for real-time
multiprocessor VMEbus systems . . . . . 71--80
R. H. Stern Micro Law: Manufacturers Disclaimers of
Liability . . . . . . . . . . . . . . . 86--87
M. Smolin Future Micro Standards Projects . . . . 88--89
C. Miller CISC, RISC, WISC --- What's in a Name 6--7
Jean-Daniel D. Nicoud Video RAMs --- Structure and
Applications . . . . . . . . . . . . . . 8--27
Harry Vlahos and
Veljko Milutinovic GaAs Microprocessors and Digital
Systems: an Overview of R&D Efforts . . . 28--56
Shreekant Thakkar and
Paul Gifford and
Garay Fielland The Balance multiprocessor system . . . 57--69
R. H. Stern Micro Law: Reflections on Dirty Harry
and dBASE . . . . . . . . . . . . . . . 70--72
P. Koopman WISCs Propagate . . . . . . . . . . . . 5--5
R. H. Stern Micro Law: The Berne Convention --- a
Bad Idea Whose Time Has Come . . . . . . 6--7
Richard Mateosian Macworld Expo . . . . . . . . . . . . . 8
K. Sakamura Recent Trends . . . . . . . . . . . . . 10--11
Hideo Inayoshi and
Ikuya Kawasaki and
Tadahiko Nishimukai and
Ken Sakamura Realization of Gmicro/200 . . . . . . . 12--21
Shinya Kimura and
Yasuhiko Komoto and
Yoichi Yano Implementation of the V60/V70 and its
FRM function . . . . . . . . . . . . . . 22--36
Misao Miyata and
Hidechika Kishigami and
Kosei Okamoto and
Shigeo Kamiya The TX1 32-Bit Microprocessor ---
Performance Analysis, and Debugging
Support . . . . . . . . . . . . . . . . 37--46
Ken Sakamura and
Ryoichi Sano and
Kazuhiko Honma Introducing Tobus: the system bus in the
TRON architecture . . . . . . . . . . . 47--59
Ken Sakamura and
Kanehisa Tsurumi and
Hiro Kato Applying the Mu-Btron Bus to a Music LAN 60--66
Borivoje Furht A RISC architecture with two-size,
overlapping register windows . . . . . . 67--80
M. Smolin Excitement in Standards . . . . . . . . 81--81
C. Miller After the Breakthrough . . . . . . . . . 82--83
C. Miller Why RISC? . . . . . . . . . . . . . . . 84--85
J. J. Farrell The Adams Report . . . . . . . . . . . . 3--4
M. Smolin IEEE 32-Bit, Backplane Bus Comparisons 5--7
J. Grimes and
J. Hootman Embedded Processors --- Another
Cost-Effective Design Tool . . . . . . . 8--9
Clif Purkiser and
Jim Kardach The Intel 376 family for embedded
processor applications . . . . . . . . . 10--26
Ron Cates Processor architecture considerations
for embedded controller applications . . 28--38
Karl M. Guttag and
Thomas M. Albers and
Michael D. Asal and
Kevin G. Rose The TMS34010 --- An Embedded
Microprocessor . . . . . . . . . . . . . 39--52
Chris Rowen and
Mark Johnson and
Paul Ries The MIPS R3010 Floating-Point
Coprocessor . . . . . . . . . . . . . . 53--62
David P. Ryan Intel's 80960: an architecture optimized
for embedded control . . . . . . . . . . 63--76
Sorin Iacobovici A pipelined interface for high
floating-point performance with precise
exceptions . . . . . . . . . . . . . . . 77--87
G. Hauptman Protection Against Piracy . . . . . . . 88--88
R. H. Stern Micro Law: Protection Against Piracy ---
Reply . . . . . . . . . . . . . . . . . 88--89
D. Karjala Protection Against Piracy --- Comments 89--89
C. Miller and
B. Gross Hypercard --- Tool or Toy . . . . . . . 92--93
Anonymous Technology Research --- Ultrafast
Devices, X-Ray-Lithography, and
Micromachines . . . . . . . . . . . . . 94--95
J. Farrell Meetings in Anaheim . . . . . . . . . . 2--2
G. Hauptman A Good Idea Has Arrived . . . . . . . . 3
R. H. Stern Micro Law: Copywriting Screen Displays 4--5
Steven W. Yates and
Ronald D. Williams A Fault-Tolerant Multiprocessor
Controller for Magnetic Bearings . . . . 6--17
Ronald D. Williams and
Barry W. Johnson and
Thomas E. Roberts An operating system for a fault-tolerant
multiprocessor controller . . . . . . . 18--29
Brenda M. Ozaki and
Eduardo B. Fernandez and
Ehud Gudes Software fault tolerance in
architectures with hierarchical
protection levels . . . . . . . . . . . 30--43
Donald B. Alpert and
Michael J. Flynn Performance Trade-Offs for
Microprocessor Cache Memories . . . . . 44--54
Elvira Argon and
I.-Lok Chang and
Gamini Gunaratna and
David K. Kahaner and
Martin A. Reed Mathematical software: Plod . . . . . . 56--61
Tenkasi V. Ramabadran and
Sunil S. Gaitonde A Tutorial on CRC Computations . . . . . 62--75
M. Smolin What's Happening with Study-Groups? . . 78--81
Anonymous Deskpro 386-20 Outperforms PS/2 Model-80 82--82
Anonymous Tiny Computer Promises Massive Speeds 82--82
Anonymous Crystal Growth . . . . . . . . . . . . . 83--83
Anonymous Organic Computers a Possibility . . . . 83--83
Anonymous Did You Ever Think You'd Like a Robot? 83--84
Anonymous Computer History, Rev-1 . . . . . . . . 84--84
Anonymous ESDI Standard Open for Comment . . . . . 84--84
D. S. Karjala Copyright Losses to Foreign Pirates . . 2
H. Kirrmann Europe in 1992 . . . . . . . . . . . . . 5--5
R. H. Stern Micro Law: On Emulators and the
Procreation of Porcupines . . . . . . . 6--7
D. Delcorso and
K. E. Grosspietsch European Approaches for Advanced
Architectures . . . . . . . . . . . . . 8--9
R. M. Lea AsP --- a Cost-Effective Parallel
Microcomputer . . . . . . . . . . . . . 10--29
Jorg Kaiser MUTABOR, a coprocessor supporting memory
management in an object-oriented
architecture . . . . . . . . . . . . . . 30--46
Bjorn Bergsten and
Ruben Gonzalez-Rubio and
Brigitte Kerherve and
Jean Rohmer An Advanced Database Accelerator . . . . 47--63
David F. Hinnant Accurate Unix benchmarking: art,
science, or black magic? . . . . . . . . 64--75
C. Miller The Reason Processor . . . . . . . . . . 76
G. A. Hauptman Joining Berne Is Wise --- Abolishing
Copyright Isn't . . . . . . . . . . . . 3--3
H. Kirrmann Europe's Industrial Bus Scene . . . . . 6--7
S. A. Dyer and
L. R. Morris Floating-Point Digital Signal-Processing
Chips --- a New Era for DSP
Systems-Design . . . . . . . . . . . . . 10--12
Panos Papamichalis and
Ray Simar, Jr. The TMS320C30 Floating-Point Digital
Signal Processor . . . . . . . . . . . . 13--29
Michael L. Fuccio and
Renato N. Gadenz and
Craig J. Garen and
Joan M. Huser and
Benjamin Ng and
Steven P. Pekarich and
Kreg D. Ulery The DSP32C: AT&T's Second-Generation
Floating-Point Digital Signal Processor 30--48
Guy R. L. Sohie and
Kevin L. Kloker A Digital Signal Processor with IEEE
Floating-Point Arithmetic . . . . . . . 49--67
L. Robert Morris A PC-Based Digital Speech Spectrograph 68--85
L. R. Morris and
S. A. Dyer Floating-Point Digital Signal-Processing
Chips --- The End of the Supercomputer
Era . . . . . . . . . . . . . . . . . . 86--86
Stephen A. Dyer and
L. Robert Morris Afterword: Floating-Point Digital Signal
Processing Chips, The End of the
Supercomputer Era? . . . . . . . . . . . 86
J. Hootman Past, Present, Future . . . . . . . . . 1--2
Richard H. Stern Micro Law: Protecting hardware against
competition by copyrighting it as a
compilation of data . . . . . . . . . . 2--5
H. Kirrmann Multiprocessors and Supercomputer
Research in Europe . . . . . . . . . . . 7--8
D. Delcorso and
K. E. Grosspietsch Guest Editors' Introduction --- European
Approaches for Advanced Architectures. 2 9--9
Pierluigi Civera and
Gianluca Piccinini and
Maurizio Zamboni Implementation studies for a VLSI Prolog
coprocessor . . . . . . . . . . . . . . 10--23
Hermann Kopetz and
Andreas Damm and
Christian Koza and
Marco Mulazzani and
Wolfgang Schwabl and
Christoph Senft and
Ralph Zainlinger Distributed Fault-Tolerant Real-Time
Systems --- The Mars Approach . . . . . 25--40
Enrico Appiani and
Bruno Conterno and
Vildo Luperini and
Leonardo Roncarolo EMMA2, a High-Performance Hierarchical
Multiprocessor . . . . . . . . . . . . . 42--56
Beatrice Lazzerini Effective VLSI processor architectures
for HLL computers: the RISC approach . . 57--65
Mansur Kabuka and
Rodrigo Escoto Real-time implementation of the
Newton-Euler equations of motion on the
NEC mu PD77230 DSP . . . . . . . . . . . 66--76
C. Miller The Quantum Leap . . . . . . . . . . . . 95--96
H. Kirrmann Fault-Tolerant Computing in Europe . . . 5--7
R. H. Stern Micro Law: Framing Prints, Giving the
Mona Lisa a Moustache, Speeding Up Video
Games, and Marketing Add-on Software ---
a Comment on the Mirage Case . . . . . . 8
Victor K. L. Huang and
James W. Seery and
William S. Wu and
Saul K. Altabet and
Michael J. Killian and
Simeon Aymeloglu and
Thaddeus J. Gabara and
Aaron L. Fisher and
Inseok S. Hwang and
David W. Thompson The AT&T WE32200 Design Challenge . . . . 14--25
Charles Melear The Design of the 88000-RISC Family . . 26--38
Ioan Dancea Dynamically changing the logical
behavior of a microcomputer interface 39--51
Mike P. Papazoglou An Extensible DBMS for Small and Medium
Systems . . . . . . . . . . . . . . . . 52--68
Bernd Ingenbleek and
Klaus Woelcken and
Claudia Matthaus Information flow in digital metal-oxide
semiconductor circuits . . . . . . . . . 69--79
Anonymous Diamond --- a Chip's Best Friend . . . . 96
R. P. Colwell RISC Tutorial Comments . . . . . . . . . 4--4
J. Hootman RISC Tutorial Comments . . . . . . . . . 4--4
H. Kirrmann Neural Computing --- The New Gold Rush
in Informatics . . . . . . . . . . . . . 7--8
K. Sakamura Special Far-East Issue --- Computer
Projects in Japan --- Introduction . . . 12--13
Ken Sakamura and
Yoshiaki Kushiki and
Kazuhiro Oda An Overview of the BTRON/286
Specification . . . . . . . . . . . . . 14--25
Shumpei Kawasaki and
Mitsuru Watabe and
Shigeki Morinaga A floating-point VLSI chip for the TRON
architecture: an architecture for
reliable numerical programming . . . . . 26--44
Shinji Komori and
Kenji Shima and
Souichi Miyata and
Toshiya Okamoto and
Hiroaki Terada The Data-Driven Microprocessor . . . . . 45--59
Jean-Daniel D. Nicoud and
Andrew Martin Tyrrell The Transputer-T414 Instruction Set . . 60--75
M. Mehdi Owrang O. and
W. Gamini Gunaratna A Logical Design Tool for Relational
Databases . . . . . . . . . . . . . . . 76--83
Richard H. Stern Micro Law: Appropriate and inappropriate
legal protection of user interfaces and
screen displays. I . . . . . . . . . . . 84--88
W. Myers Design Choices Power the Next Wave . . . 96
Richard H. Stern Micro Law: Appropriate and inappropriate
legal protection of user interfaces and
screen displays. II. Technical aspects
of screen design raising legal policy
issues . . . . . . . . . . . . . . . . . 7--10, 92--94
Richard Mateosian A New Macintosh Environment . . . . . . 11--12
V. K. L. Huang High-Performance Microprocessors --- The
RISC Dilemma . . . . . . . . . . . . . . 13--14
Les Kohn and
Neal Margulis Introducing the Intel i860 64-Bit
Microprocessor . . . . . . . . . . . . . 15--30
Joe Jelemensky and
Vernon Goler and
Brad Burgess and
James Eifert and
Gary Miller The MC68332 Microcontroller . . . . . . 31--50
Richard S. Piepho and
William S. Wu A Comparison of RISC Architectures . . . 51--62
Matthew Johnson A Fixed-Point DSP for Graphics Engines 63--77
H. Kirrmann The Smaky Story --- The Swiss
Personal-Computer . . . . . . . . . . . 78--79
W. Myers The Road to the Supersmart Card . . . . 96
Richard Mateosian Macintosh Issues Welcomed --- Reply . . 7--7
L. F. West Macintosh Issues Welcomed . . . . . . . 7--7
Richard H. Stern Micro Law: Appropriate and inappropriate
legal protection of user interfaces and
screen displays. III. Copyright law, the
courts, and the copyright office . . . . 8--9, 75--79
N. Jagadish and
J. Mohan Kumar and
L. M. Patnaik An efficient scheme for interprocessor
communication using dual-ported RAMs . . 10--19
Tho Le-Ngoc and
Minh Tue Vo Implementation and Performance of the
Fast Hartley Transform . . . . . . . . . 20--27
Walter J. Price A Benchmark Tutorial . . . . . . . . . . 28--43
An-Chi C. Liu and
Ranjani Parthasarathi Hardware Monitoring of a Multiprocessor
System . . . . . . . . . . . . . . . . . 44--51
David F. Franklin and
David V. Ostler The P1073 Medical Information Bus . . . 52--60
William P. Birmingham and
Anurag P. Gupta and
Daniel P. Siewiorek The Micon System for Computer Design . . 61--67
Mark Walker and
Paul Hasler and
Lex Akers A CMOS Neural Network for Pattern
Association . . . . . . . . . . . . . . 68--74
J. Hootman Neural Networks --- Problem-Solving
Tools . . . . . . . . . . . . . . . . . 4
D. Delcorso and
K. E. Grosspietsch and
P. Treleaven European Approaches to VLSI Neural
Networks . . . . . . . . . . . . . . . . 5--7
Philip Treleaven and
Marco Pacheco and
Marley Vellasco VLSI Architectures for Neural Networks 8--27
Karl Goser and
Ulrich Hilleringmann and
Ulrich Rückert and
Klaus Schumacher VLSI Technologies for Artificial Neural
Networks . . . . . . . . . . . . . . . . 28--44
Michel Verleysen and
Paul G. A. Jespers An analog VLSI implementation of
Hopfield's neural network . . . . . . . 46--55
Olivier Rossetto and
Christian Jutten and
Jeanny Herault and
Ingo Kreuzer Analog VLSI synaptic matrices as
building blocks for neural networks . . 56--63
Alan F. Murray Pulse Arithmetic in VLSI Neural Networks 64--74
Eduardo R. Caianiello Is There a Silicon Way to Intelligence? 75--76
R. H. Stern Micro Law: Appropriate and Inappropriate
Legal Protection of User Interfaces and
Screen Displays. IV. Screen Display
Protection and Policy Concerns . . . . . 84--89
C. Warren Establishing the Basics . . . . . . . . 92--94
C. Warren Update on Standards . . . . . . . . . . 95--97
M. Slater VLIW, Superscalar, and 64 Bit or Not . . 104
H. Kirrmann COCOM --- The Next Wall to Fall . . . . 4--6
Richard Mateosian The Problems of Japanese-Language
Computing . . . . . . . . . . . . . . . 7--8
W. Myers Users Said --- No Sacrifices . . . . . . 9
Emil W. Brown and
Anant Agrawal and
Trevor Creary and
Michael F. Klein and
David Murata and
Joseph Petolino Implementing Sparc in ECL . . . . . . . 10--22
Stephen C. Johnson Hot Chips and Soggy Software: RISC
success springs partially from good
system design. Take note and eliminate
the software bottleneck from your new
design . . . . . . . . . . . . . . . . . 23--26
John H. Crawford The i486 CPU: executing instructions in
one clock cycle . . . . . . . . . . . . 27--36
Thomas J. Pennello Compiler Challenges with RISCs . . . . . 37--43
Curtis R. Priem Developing the GX graphics accelerator
architecture . . . . . . . . . . . . . . 44--54
Mark Birman and
Allen Samuels and
George Chu and
Ting Chuk and
Larry Hu and
John McLeod and
John Barnes Developing the WTL3170/3171 Sparc
Floating-Point Coprocessors . . . . . . 55--64
Robin W. Edenfield and
Michael G. Gallup and
William B. Ledbetter, Jr. and
Ralph C. McGarity and
Eric E. Quintana and
Russell A. Reininger The 68040 Processor: Part I, Design and
Implementation . . . . . . . . . . . . . 66--78
Richard H. Stern Micro Law: Appropriate and inappropriate
legal protection of user interfaces and
screen displays. V. How different forms
of copyright protection interact with
policy . . . . . . . . . . . . . . . . . 79--84
C. Warren A Busy Year Ahead . . . . . . . . . . . 85--86
C. Warren Wire-to-Wire Interaction . . . . . . . . 87--88
J. Chrzaszcz One Person's Cup of Tea Is \ldots . . . 93--93
M. J. Johnson One Person's Cup of Tea Is --- Reply . . 93--93
M. Slater The View from 10,000 Feet . . . . . . . 96
J. Hootman The Far-East Issue for 1990 . . . . . . 3--3
J. Luu On 2nd Thought \ldots . . . . . . . . . 5--5
T. Paterson On 2nd Thought \ldots . . . . . . . . . 5--5
J. Luu Comments on `A comparison of RISC
architectures' by R. S. Piepho and W. S.
Wu . . . . . . . . . . . . . . . . . . . 5--5
K. Sakamura The Tron Intelligent House . . . . . . . 6--7
Richard H. Stern Micro Law: Software Patents . . . . . . 8--11
Ken Sakamura Guest Editor's Introduction: The Current
Japanese Computer Scene . . . . . . . . 12--13
Hideto Hidaka and
Yoshio Matsuda and
Mikio Asakura and
Kazuyasu Fujishima The cache DRAM architecture: a DRAM with
an on-chip cache memory . . . . . . . . 14--25
Katsuyuki Kaneko and
Masaitsu Nakajima and
Yasuhiro Nakakura and
Junji Nishikawa and
Ichiro Okabayashi and
Hiroshi Kadota Processing Element Design for a Parallel
Computer . . . . . . . . . . . . . . . . 26--38
Yuji Hatano and
Shinichiro Yano and
Hiroyuki Mori and
Hiroji Yamada and
Mikio Hirano and
Ushio Kawabe A 4-Bit, 250-MIPS Processor Using
Josephson-Technology . . . . . . . . . . 40--55
Hiroaki Kaneko and
Nariko Suzuki and
Hiroshi Wabuka and
Koji Maemura Realizing the V80 and Its System Support
Functions . . . . . . . . . . . . . . . 56--69
Milan Milenkovic Microprocessor Memory Management Units 70--85
H. Kirrmann Minitel --- The French Love Affair with
Telematics . . . . . . . . . . . . . . . 88--90
M. Slater Who Needs Faster Processors? . . . . . . 96
H. Beasley The Futurebus+ Protocol Stack and
Profiles . . . . . . . . . . . . . . . . 2
J. Hootman Hot Chips. 2 . . . . . . . . . . . . . . 3--4
C. Miller and
R. Crawford Silicon Glen --- The European Challenge 7--8
David V. James Multiplexed Buses --- The Endian Wars
Continue . . . . . . . . . . . . . . . . 9--21
Robin W. Edenfield and
Michael G. Gallup and
William B. Ledbetter, Jr. and
Ralph C. McGarity and
Eric E. Quintana and
Russel A. Reininger The 68040 Processor: Part 2, Memory
Design and Chip Verification . . . . . . 22--35
Merrick Darley and
Bill Kronlage and
David Bural and
Bob Churchill and
David Pulling and
Paul Wang and
Rick Iwamoto and
Larry Yang The TMS390C602A Floating-Point
Coprocessor for Sparc Systems . . . . . 36--47
Mitch Alsup Motorola's 88000 Family Architecture . . 48--66
Takeshi Kitahara and
Taizo Satoh The Gmicro/300 32-Bit Microprocessor . . 68--75
C. Warren Realizing a Transmission Model . . . . . 76--79
C. Warren The Scalable Coherent Interface . . . . 80--82
R. H. Stern Micro Law: Professional Ethics and the
Law . . . . . . . . . . . . . . . . . . 83--84
M. Slater What Is RISC? . . . . . . . . . . . . . 96
J. Hootman Letters and Articles . . . . . . . . . . 2--3
D. K. Kahaner Assignment Japan . . . . . . . . . . . . 4--6
R. H. Stern Micro Law: More on Software Patents . . 7--9
Roger D. Chamberlain and
Mark A. Franklin Hierarchical Discrete-Event Simulation
on Hypercube Architectures . . . . . . . 10--20
F. N. Sibai and
K. L. Watson and
Mi Lu A Parallel Unification Machine . . . . . 21--33
Michael Rumsey and
John Sackett An ASIC methodology for mixed
analog-digital simulation . . . . . . . 34--40
A. J. van der Hoeven and
A. A. J. de Lange and
E. F. Deprettere and
P. M. Dewilde A model for the high-level description
and simulation of VLSI networks . . . . 41--48
K. H. Lee and
K. S. Leung and
S. M. Cheang A microprogrammable list processor for
personal computers . . . . . . . . . . . 50--61
Yousif A. El-Imam and
Karima Banat Text-to-Speech Conversion on a Personal
Computer . . . . . . . . . . . . . . . . 62--74
C. Warren Backplane Measurements . . . . . . . . . 75--77
S. J. Stock Low-Cost CAD Drawings . . . . . . . . . 77--78
H. Kirrmann Train Control-Systems . . . . . . . . . 79--80
Richard Mateosian Impressive Software . . . . . . . . . . 81--82
M. Slater Failings of the Patent System . . . . . 96
J. Hootman How Micro Survives . . . . . . . . . . . 3--4
David K. Kahaner Software Report --- The Pax parallel
computer . . . . . . . . . . . . . . . . 5--6, 91--93
R. H. Stern Micro Law: The Paperback Case . . . . . 7--10
Stephen A. Dyer and
Richard J. Higgins Guest Editor's Introduction: The
Maturing of DSP . . . . . . . . . . . . 11--13
Edward A. Lee Programmable DSPs --- a Brief Overview 14--16
Henry Davis and
Robert Fine and
Denis Regimbal Merging data converters and DSPs for
mixed-signal processors . . . . . . . . 17--27
Jeffrey C. Bier and
Edwin E. Goei and
Wai H. Ho and
Philip D. Lapsley and
Maureen P. O'Reilly and
Gilbert C. Sih and
Edward A. Lee Gabriel --- a Design Environment for DSP 28--45
Krishna A. Kumar and
Brian Petrasko Designing a Custom DSP Circuit Using
VHDL . . . . . . . . . . . . . . . . . . 46--53
Rulph Chassaing and
Wayne A. Peterson and
Darrell W. Horning A TMS320C25-Based Multirate Filter . . . 54--62
Guido Albertengo and
Riccardo Sisto Parallel CRC Generation . . . . . . . . 63--71
C. Warren Keeping Up with Uncle Sam . . . . . . . 72--73
Francis X. Govers III and
Michael J. Pierson On the edge --- analysis of transactions
and computers . . . . . . . . . . . . . 73--75
Richard Mateosian A Writing Course for Engineers . . . . . 76--77
H. Kirrmann Train Buses . . . . . . . . . . . . . . 79--80
M. Slater Protecting Computer Architectures . . . 96
H. Kirrmann Reunifying East-West Electronics
Industries . . . . . . . . . . . . . . . 5--7
Jean-François Omnes and
Thierry Van der Pyl and
Philip Treleaven Guest Editors' Introduction: Parallel
Computing in Europe . . . . . . . . . . 8--10
Pierre H. M. America and
Ben J. A. Hulshof and
Eddy A. M. Odijk and
Frans Sijstermans and
Rob A. H. van Twist and
Rogier H. H. Wester Parallel computers for advanced
information processing . . . . . . . . . 12--15, 61--75
Colin Whitby-Strevens Transputers --- Past, Present, and
Future . . . . . . . . . . . . . . . . . 16--19, 76--82
Guy Haworth and
Steve Leunig and
Carsten Hammer and
Mike Reeve The European Declarative System,
database, and languages . . . . . . . . 20--23, 83--88
Peter A. Rounce and
Jose Delgado Architectures Within the Esprit Span
Project . . . . . . . . . . . . . . . . 24--27, 88--97
Bernard Angeniol Pygmalion: ESPRIT II Project 2059,
Neurocomputing . . . . . . . . . . . . . 28--31, 99--102
R. H. Stern Micro Law: The Paperback Case. 2. A
Nonliteral Analysis . . . . . . . . . . 39--41
C. Warren A Standard to Consider . . . . . . . . . 42--45
D. K. Kahaner Quality Improvement . . . . . . . . . . 48--51
M. Slater AMD v. Intel . . . . . . . . . . . . . . 104
D. Delcorso Launching the 2nd Decade . . . . . . . . 2--4
True Seaborn and
Peter R. Rony and
Richard C. Jaeger and
James J. Farrell and
Joe Hootman Sometimes a Good Idea Beats a Good Plan
(But Not Often) . . . . . . . . . . . . 5--6
P. R. Rony and
R. C. Jaeger A Magazine Is Born . . . . . . . . . . . 7--8
J. J. Farrell A Decade of Contributors . . . . . . . . 8--9
J. Hootman The Role of the EIC . . . . . . . . . . 9
Ware Myers The Drive to the Year 2000 . . . . . . . 10--13, 68--74
Jean-Daniel D. Nicoud Dedicated Tools for Microprocessor
Education . . . . . . . . . . . . . . . 14--17, 62--68
John A. Fulcher Fun and Games and Microcomputer
Interfacing . . . . . . . . . . . . . . 18--21, 75--78
L. Howard Pollard and
Ramiro Jordan An Advanced Educational Microprocessor
System . . . . . . . . . . . . . . . . . 22--25, 78--79
David W. Russell and
Kirtley B. Haden A configurable, virtual microprocessor
system for instructional use in
real-time, real-world studies . . . . . 26--29
Thomas W. Schultz Peripheral Hardware and a Hands On
Multitasking Lab . . . . . . . . . . . . 30--33, 80--82
Douglas V. Hall Adapting curriculum materials for
different course sequences . . . . . . . 34--37, 82--83
Simon L. Peyton Jones and
Mark S. Hardie A Futurebus Interface from Off-the-Shelf
Parts . . . . . . . . . . . . . . . . . 38--41, 84--93
H. Kirrmann When the Computer Was Still Personal . . 42--44
C. Warren There's a Standard Hiding Out There . . 45
Carl Warren On the edge --- evaluating shielded
twisted-pair cable . . . . . . . . . . . 46--47
R. H. Stern Micro Law: The Paperback Case. 3.
Misconceptions About Functionality . . . 48--51
R. H. Stern Micro Law: Computer Software Rentals
Restricted in United States . . . . . . 52--52
D. K. Kahaner Optical Computing Activities . . . . . . 53--56
M. Slater Evolving Architectures . . . . . . . . . 96
Anonymous Improving the Product --- Reply . . . . 2--2
J. R. Chrzaszcz Precisely Speaking . . . . . . . . . . . 2--2
D. Tabak Improving the Product . . . . . . . . . 2--2
D. Delcorso The Ultimate Solution . . . . . . . . . 6--7
W. Myers HDTV Faces Intertwined Challenges . . . 8--9
D. K. Kahaner 6th Generation Project . . . . . . . . . 11
Xiaodong D. Zhang System effects of interprocessor
communication latency in multicomputers 12--15, 52--55
Cosimo A. Prete RST Cache Memory Design for a Tightly
Coupled Multiprocessor System . . . . . 16--19, 40--52
Antonella Di Stefano and
Orazio Mirabella and
Fabio Presente Implementing a DSP-Based Petri-Net
Simulation Tool . . . . . . . . . . . . 20--23, 56--64
Ahmed Louri Three-dimensional optical architecture
and data-parallel algorithms for
massively parallel computing . . . . . . 24--27, 65--82
R. H. Stern Micro Law: The Paperback Case. 4. What's
Really Going on . . . . . . . . . . . . 30--33
C. Warren Sorry, Captain Kirk . . . . . . . . . . 34--35
M. Slater The End of the 386-Monopoly . . . . . . 88
T. Pittman IEEE and the Software Rental Act . . . . 2--2
R. H. Stern Micro Law: IEEE and the Software Rental
Act --- Reply . . . . . . . . . . . . . 3
H. Kirrmann Light at the End of the Chunnel . . . . 4--6
X. D. Zhang Correction . . . . . . . . . . . . . . . 6--6
Mark D. Hill and
David A. Wood Guest Editors' Introduction: Hot Chips
II Symposium . . . . . . . . . . . . . . 8--9
Val Popescu and
Merle Schultz and
John Spracklen and
Gary Gibson and
Bruce Lightner and
David Isaman The Metaflow Architecture . . . . . . . 10--13, 63--73
Richard R. Oehler and
Michael W. Blasgen IBM RISC System/6000: architecture and
performance . . . . . . . . . . . . . . 14--17, 56--62
Howard G. Sachs and
Harlan McGhan and
Lee F. Hanson and
Nathan A. Brookwood Design and implementation trade-offs in
the Clipper C400 architecture . . . . . 18--21, 74--80
Ulrich Schmidt and
Knut Caesar Datawave --- a Single-Chip
Multiprocessor for Video Applications 22--25, 88--94
Craig Peterson and
James Sutton and
Paul Wiley Iwarp --- a 100-Mops, LIW Microprocessor
for Multicomputers . . . . . . . . . . . 26--29, 81--87
Lui Sha and
Ragunathan Rajkumar and
John P. Lehoczky Special Feature: Real-Time Computing
with IEEE Futurebus+ . . . . . . . . . . 30
J. D. Gafford Rate Monotonic Scheduling . . . . . . . 34
D. K. Kahaner Computer Growth in Taiwan . . . . . . . 39--41
R. H. Stern Micro Law: (C) --- Greater-Than-Software
Legal HLP . . . . . . . . . . . . . . . 42--46
W. Myers News from Compcon 91 . . . . . . . . . . 47--49
Richard H. Stern Micro Law: The first chip-layout copying
case . . . . . . . . . . . . . . . . . . 3--6, 94
D. K. Kahaner Software Report: Fuzzy theory,
applications . . . . . . . . . . . . . . 8--11
Ken Sakamura Guest Editor's Introduction: Presenting
the Far East Special Issue for 1991 . . 12--15
Akira Fukuda and
Kazuaki Murakami and
Shinji Tomita Toward advanced parallel processing:
exploiting parallelism at task and
instruction levels . . . . . . . . . . . 16--19, 50--61
Toyohiko Yoshida and
Toru Shimizu and
Shigeo Mizugaki and
Junichi Hinata The Gmicro/100 32-Bit Microprocessor . . 20--23, 62--72
Hiroaki Takada and
Ken Sakamura Itron-MP --- An Adaptive Real-Time
Kernel Specification for Shared-Memory
Multiprocessor Systems . . . . . . . . . 24--27, 78--85
Akira Kabemoto and
Hiroshi Yoshida The architecture of the Sure System 2000
communications processor . . . . . . . . 28--31, 73--78
Yau-Hwang Kuo and
Ling-Yang Kung and
Ching-Chung Tzeng and
Guang-Huei Jeng and
Wei-Kuo Chia KMDS: an expert system for integrated
hardware/software design of
microprocessor-based digital systems . . 32--35, 86--92
H. Kirrmann Europe on the Way to the Metric System 36--39
C. Warren A Bountiful Return . . . . . . . . . . . 40--41
Anonymous PILOT, SCI, Futurebus+ . . . . . . . . . 40
Richard Mateosian Mathematica Help Stack . . . . . . . . . 43--43
Richard Mateosian Mouse-Trak . . . . . . . . . . . . . . . 43--44
D. Delcorso Bioengineering Applications . . . . . . 2--3
Richard Mateosian Computers and Creativity . . . . . . . . 4--6
Hua Li and
Ching-Ho H. Chen Simulating a function of visual
peripheral processes with an analog VLSI
network . . . . . . . . . . . . . . . . 8--11, 44--47
Marco Knaflitz and
Gabriella Balestra Computer Analysis of the Myoelectric
Signal . . . . . . . . . . . . . . . . . 12--15, 48--58
Hans-Ruedi R. Aschmann and
Niklaus Giger and
Elisabeth Hoepli and
Peter Janak and
Hubert Kirrmann Alphorn: a remote procedure call
environment for fault-tolerant,
heterogeneous, distributed systems . . . 16--19, 60--67
Charles E. Roberts A RISC processor for embedded
applications within an ASIC . . . . . . 20--23, 68--72
Mark Atkins Performance and the I860 Microprocessor 24--27, 72--78
C. Warren IEEE Standard P1754 --- An Open
Microprocessor Architecture . . . . . . 30--33
R. H. Stern Micro Law: Fraud on the Copyright Office 33--34
D. K. Kahaner Software Report: a glimpse of the future 35
J. M. Schachner On an Open Architecture . . . . . . . . 2--2
R. Usselmann On an Open Architecture --- Reply . . . 2--2
Anonymous Micro News: PLA copyright infringement 4
M. Abdelguerfi and
A. K. Sood Guest Editors' Introduction: Database
Machines --- Trends and Opportunities 6--7
Kuo Chu Lee and
Takako Matoba Hickey and
Victor W. Mak and
Gary E. Herman VLSI Accelerators for Large Database
Systems . . . . . . . . . . . . . . . . 8--20
Pascal Faudemay and
Mongia Mhiri An Associative Accelerator for Large
Databases . . . . . . . . . . . . . . . 22--34
M. Abdelguerfi and
A. K. Sood A Fine-Grain Architecture for Relational
Database Aggregation Operations . . . . 35--43
David K. Hsiao A parallel, scalable,
microprocessor-based database computer
for performance gains and capacity
growth . . . . . . . . . . . . . . . . . 44--60
Ushio Inoue and
Tetsuji Satoh and
Haruo Hayami and
Hideaki Takeda and
Toshio Nakamura and
Hideki Fukuoka Rinda: a relational database processor
with hardware specialized for searching
and sorting . . . . . . . . . . . . . . 61--70
R. H. Stern Micro Law: Database System Copyrights 78--80
C. Warren Sbus --- An Open Bus Architecture . . . 80--83
C. Warren Computing Interconnections . . . . . . . 84--86
R. H. Stern Micro Law: Engineers Can Be
Disqualified, Too . . . . . . . . . . . 4
D. K. Kahaner Research-and-Development in Japan . . . 7
David B. Gustavson The Scalable Coherent Interface and
related standards projects . . . . . . . 10--22
Daniel Mann Unix and the Am29000 Microprocessor . . 23--31
Bernhard E. Boser and
Eduard Sackinger and
Jane Bromley and
Yann leCun and
Lawrence D. Jackel Hardware requirements for neural network
pattern classifiers: a case study and
implementation . . . . . . . . . . . . . 32--40
Ophir Frieder and
Vijaykumar A. Topkar and
Ramesh K. Karne and
Arun K. Sood Experimentation with Hypercube Database
Engines . . . . . . . . . . . . . . . . 42--56
Marcus Adams and
Yi Qian and
Jacek Tomaszunas and
Josef Burtscheidt and
Edgar Kaiser and
Csaba Juhasz Conformance testing of VMEbus and
Multibus II products . . . . . . . . . . 57--64
Richard Mateosian How I Spent My Christmas Vacation . . . 65--68
C. Warren Understanding the Acronym Tower-of-Babel 69--72
C. Warren Firmware Standards . . . . . . . . . . . 73--75
W. Myers The Limits of Chip Density . . . . . . . 75--77
H. Kirrmann Hermes, the European Space-Shuttle . . . 3--5
Norman P. Jouppi Hot Chips-III --- Introduction . . . . . 8--9
Sunil Mirapuri and
Michael Woodacre and
Nader Vasseghi The MIPS R4000 Processor . . . . . . . . 10--22
William J. Dally and
J. A. Stuart Fiske and
John S. Keen and
Richard A. Lethin and
Michael D. Noakes and
Peter R. Nuth and
Roy E. Davison and
Gregory A. Fyler The Message-Driven Processor --- a
Multicomputer Processing Node with
Efficient Mechanisms . . . . . . . . . . 23--39
Keith Diefendorff and
Michael Allen Organization of the Motorola 88110
superscalar RISC microprocessor . . . . 40--63
Jack Regula The proposed SSBLT standard doubles the
VME64 transfer rate . . . . . . . . . . 64--71
C. Warren PCMCIA --- The Other Interface . . . . . 72--73
R. H. Stern Micro Law: Game Genie --- Copyrights and
Add-Ons . . . . . . . . . . . . . . . . 74--79
Lee White and
Hareton K. N. Leung On the Edge --- Regression testability 81--84
W. Myers Second-generation RISCs . . . . . . . . 86--87
R. H. Stern Micro Law: No Accolades for Accolade
Court . . . . . . . . . . . . . . . . . 3--6
Anonymous No more software reverse engineering? 3
W. Myers From Desk-Top to Palmtop . . . . . . . . 7
K. E. Grosspietsch Guest Editor's Introduction: Associative
Processors and Memories . . . . . . . . 10--11
K. E. Grosspietsch Associative-Processors and Memories ---
a Survey . . . . . . . . . . . . . . . . 12--19
Ian N. Robinson Pattern-Addressable Memory . . . . . . . 20--30
Frederick P. Herrmann and
Charles G. Sodini A dynamic associative processor for
machine vision applications . . . . . . 31--41
Richard Storer and
Mike R. Pout and
Andrew R. Thomson and
Erik L. Dagless and
Andrew W. G. Duller and
A. Paul Marriott and
Peter J. Hicks An associative processing module for a
heterogeneous vision architecture . . . 42--55
Tim Moors and
Antonio Cantoni Cascading Content-Addressable Memories 56--66
D. K. Kahaner ISA in Taiwan . . . . . . . . . . . . . 69--71
Anonymous Meet the experts . . . . . . . . . . . . 72
Anonymous Object encyclopedia technology . . . . . 74
C. Warren A Plan for the Future . . . . . . . . . 76--77
R. H. Stern Micro Law: Current Developments in
United States Computer and
Electronics-Industry Tie-in Law . . . . 3
Anonymous Databases; C++; science writing . . . . 6
Egon Hoerbst Microelectronics in Europe --- Guest
Editors' Introduction . . . . . . . . . 8--9
Armin W. Weider and
Franz Neppl CMOS Technology Trends and Economics . . 10--19
Rob Woudsma and
Jef L. van Meerbergen Consumer applications: a driving force
for high-level synthesis of
signal-processing architectures . . . . 20--33
Edgard Laes and
Herman J. Casier and
Eric Schutz Analog-Digital Technologies for
Mixed-Signal Processing --- The Driving
Force to Success for the European
Industry . . . . . . . . . . . . . . . . 34--42
Jean Pierre Moreau and
Joseph Borel and
Davoud Samani European Trends in Library Development 43--53
Anton Sauer and
Jean Pierre Tual and
Robin La Fontaine European Activities for EDA
Standardization . . . . . . . . . . . . 54--59
Ray Simar, Jr. and
Peter Koeppen and
Jerald Leach and
Steve Marshall and
Dave Francis and
Greg Mekras and
Jeffrey Rosenstrauch and
Scott Anderson Floating-Point Processors Join Forces in
Parallel Processing Architectures . . . 60--69
David Kahaner Special Report --- MITI's Real World
Computing Program . . . . . . . . . . . 70--80
M. R. Lindeburg Electrical-Engineer Registration . . . . 82--84
D. K. Kahaner Melco Neural Chip --- Holography
Research . . . . . . . . . . . . . . . . 85--87
Anonymous Atomic fountains; laser tweezers;
optical molasses . . . . . . . . . . . . 88
Anonymous Chips; CAD tools; signal processing
hardware/software . . . . . . . . . . . 90
R. H. Stern Micro Law: Penalties for Reverse
Engineering . . . . . . . . . . . . . . 2--4
D. K. Kahaner ISDN Progress, Civil vs Military
Technology . . . . . . . . . . . . . . . 7
Gilles Privat and
Eric Petajan Processing Hardware for Real-Time Video
Coding --- Introduction . . . . . . . . 9--12
Eric Petajan Digital video coding techniques for US
high-definition TV . . . . . . . . . . . 13--21
Obed Duardo and
Scott C. Knauer and
John N. Mailhot and
Kalyan Mondal and
Tommy C. Poon Architecture and implementation of ICs
for a DSC-HDTV video decoder system . . 22--27
Peter A. Ruetz and
Po Tong A 160 Mpixel/s IDCT processor for HDTV 28--32
Doug Bailey and
Matt Cressa and
Jan Fandrianto and
Doug Neubauer and
Hedley Rainnie and
Chi-Shin Wang Programmable vision processor/controller
for flexible implementation of current
and future image compression standards 33--39
Clark Thomborson The V.42bis Standard for
Data-Compressing Modems . . . . . . . . 41--53
Urs A. Muller and
Bernhard Baumle and
Peter Kohler and
Anton Gunzinger and
Walter Guggenbuhl Achieving Supercomputer Performance for
Neural Net Simulation with an Array of
Digital Signal Processors . . . . . . . 55--65
C. Warren and
J. Gafford Tools to Make the Engineer's Life Easier 66--68
Richard Mateosian Instant Definitions . . . . . . . . . . 72--73
D. Delcorso Letters and Special Themes . . . . . . . 2--2
S. L. Diamond Quality Standards . . . . . . . . . . . 3--5
R. H. Stern Micro Law: Unobserved Demise of
Exhaustion Doctrine . . . . . . . . . . 5--7
John L. Schmalzel and
Parimal A. Patel Guest Editors' Introduction:
Transforming the World of Digital Signal
Processing . . . . . . . . . . . . . . . 8--9
Michael R. Smith How RISCy Is DSP? . . . . . . . . . . . 10--23
Parimal A. Patel and
Hemal N. Kothari and
James F. Robb Development of an ASIC Set for Signal
Processing . . . . . . . . . . . . . . . 24--33
Jeff Brauch and
Simon M. Tam and
Mark A. Holler and
Arthur L. Shmurun Analog VLSI neural networks for impact
signal processing . . . . . . . . . . . 34--45
Jin Luo and
Christof Koch and
Bimal Mathur Figure-ground segregation using an
analog VLSI chip . . . . . . . . . . . . 46--57
Karl E. Grosspietsch and
Ralf Reetz The Associative Processor System CAPRA:
Architecture and Applications . . . . . 58--67
Charles D. Stormon and
Nikos B. Troullinos and
Edward M. Saleh and
Abhijeet V. Chavan and
Mark R. Brule and
John V. Oldfield A General-Purpose CMOS Associative
Processor IC and System . . . . . . . . 68--78
Richard Mateosian PC Miscellany . . . . . . . . . . . . . 86--87
D. K. Kahaner Transputers and Databases . . . . . . . 88--89
D. Delcorso Check Point 2 . . . . . . . . . . . . . 2--3
W. Myers ICs per Vehicle Increasing Rapidly . . . 4--6
Bernd Hoefflinger Guest Editor's Introduction: An
Electronic Copilot in Your Car? . . . . 7--10
Steven E. Shladover Research and development needs for
advanced vehicle control systems . . . . 11--19
Ulf Palmquist Intelligent Cruise Control and Roadside
Information . . . . . . . . . . . . . . 20--28
E. Zanoni and
P. Pavan Improving the reliability and safety of
automotive electronics . . . . . . . . . 30--48
Ulrich Seger and
Heinz-Gerd G. Graf and
Marc E. Landgraf Vision Assistance in Scenes with Extreme
Contrast . . . . . . . . . . . . . . . . 50--56
Stefan Neusser and
Jos Nijhuis and
Lambert Spaanenburg and
Bernd Hoefflinger and
Uwe Franke and
Hans Fritz Neurocontrol for Lateral Vehicle
Guidance . . . . . . . . . . . . . . . . 57--66
David K. Kahaner Special report: Supercomputing --- the
view from Japan . . . . . . . . . . . . 67--70
S. L. Diamond Fair Is Foul, and Foul Is Fair . . . . . 71--72
Richard H. Stern Micro Law: a guardedly cheerful note ---
for a change (computer program
copyright) . . . . . . . . . . . . . . . 73--75
D. K. Kahaner Malaysia and Singapore . . . . . . . . . 75--77
Richard Mateosian Microsoft Word 5.1 for the Macintosh and
Word for Windows 2.0 . . . . . . . . . . 79--80
Richard Mateosian MKS Toolkit 4.1 for DOS . . . . . . . . 80--80
Richard Mateosian Speed Reader Windows Version . . . . . . 80--80
W. Myers Market Volume Drives Neural-Net
Technology . . . . . . . . . . . . . . . 3--5
David Misunas Guest Editor's Introduction: Advanced
Packaging and Interconnection Technology 7--9
Dennis J. Herrell Addressing the Challenges of Advanced
Packaging and Interconnection . . . . . 10--18
David H. Carey Trends in Low-Cost, High-Performance
Substrate Technology . . . . . . . . . . 19--27
Surendra Burman and
Naveed A. Sherwani Programmable Multichip Modules . . . . . 28--35
Yakov Belopolsky Interaction of multichip module
substrates with high-density connectors 36--44
Colin A. MacKay Amalgams for Improved Electronics
Interconnection . . . . . . . . . . . . 46--58
A. R. Hurson and
Patrick M. Miller A 16-Kbit Theta --- search associative
memory . . . . . . . . . . . . . . . . . 59--65
David K. Kahaner Special Report: Virtual Reality in Japan 66--73
Richard H. Stern Micro Law: a back door to protecting
look and feel? . . . . . . . . . . . . . 74--76
S. L. Diamond Standards and Innovation . . . . . . . . 77--78
D. K. Kahaner Micromachines --- High-Tech Odds and
Ends . . . . . . . . . . . . . . . . . . 79--82
S. L. Diamond Desk-Top Document Management . . . . . . 4--6
J. R. Mashey Hot and Cool Chips --- Guest Editors'
Introduction . . . . . . . . . . . . . . 9--10
D. Alpert and
D. Avnon Architecture of the Pentium
Microprocessor . . . . . . . . . . . . . 11--21
T. Asprey and
G. S. Averill and
E. DeLano and
R. Mason and
B. Weiner and
J. Yetter Performance Features of the PA7100
Microprocessor . . . . . . . . . . . . . 22--35
E. McLellan The Alpha AXP Architecture and 21064
Processor . . . . . . . . . . . . . . . 36--47
A. Agarwal and
J. Kubiatowicz and
D. Kranz and
B. H. Lim and
D. Yeung and
G. D'Souza and
M. Parkin Sparcle: an evolutionary processor
design for large-scale multiprocessors 48--61
D. Talia Message-Routing Systems for
Transputer-Based Multicomputers . . . . 62--72
W. Myers Get to Market Faster with FPGAs . . . . 73--74
Richard H. Stern Micro Law: Glitches left in software
copyright system . . . . . . . . . . . . 75--77
S. L. Diamond Micro Standards: Organizing the
corporate standards function . . . . . . 81--83
Richard Mateosian Framemaker 3.0 . . . . . . . . . . . . . 84--85
Richard Mateosian MS-DOS 6 . . . . . . . . . . . . . . . . 85--85
D. K. Kahaner Software report: completely automated
assembly . . . . . . . . . . . . . . . . 88--92
D. Delcorso Best Article Award for 1992 . . . . . . 2--2
D. Price Berkeley's Patterson Predicts Exciting
Times . . . . . . . . . . . . . . . . . 4
Richard H. Stern Micro Law: Reverse engineering for
future compatibility . . . . . . . . . . 6--7, 76--79
Steven W. White and
Phil D. Hester and
Jack W. Kemp and
G. Jeanette McWilliams How does processor MHz relate to
end-user performance? Part 1: Pipelines
and functional units . . . . . . . . . . 8--16
Jeffrey D. Gee and
Mark D. Hill and
Dionisios N. Pnevmatikatos and
Alan Jay Smith Cache Performance of the Spec92
Benchmark Suite . . . . . . . . . . . . 17--27
Gordon Russell and
Paul Shaw Shifting Register Windows . . . . . . . 28--35
Chia-Jiu J. Wang and
Frank Emnett Implementing precise interruptions in
pipelined RISC processors . . . . . . . 36--43
David K. Kahaner Special Report: India and China Hurdle
Computing Obstacles . . . . . . . . . . 44--48
Mark Kahrs Short Note: Dream Chip #1: Timed
Priority Queue . . . . . . . . . . . . . 49--51
A. K. Sood On the edge --- thermal resistance (ICs) 52--58
S. L. Diamond Micro Standards: Building standards . . 59--60
Anonymous Programming and compressing . . . . . . 61
R. H. Stern Micro Law: Hewlett--Packard's License
Finesses Intel's Patent in Foundry Deal 64--67
Richard H. Stern Micro Law: Protecting
Industrial-Property Rights . . . . . . . 2--3, 100
Richard Mateosian Programming Windows . . . . . . . . . . 4
Ken Sakamura Toward a World Filled with Computers . . 6--11
Kunio Uchiyama and
Fumio Arakawa and
Susumu Narita and
Hirokazu Aoki and
Ikuya Kawasaki and
Shigezumi Matsui and
Mitsuyoshi Yamamoto and
Norio Nakagawa and
Ikuo Kudo The Gmicro/500 superscalar
microprocessor with branch buffers . . . 12--22
Makoto Awaga and
Hiromasa Takahashi The $ \mu $VP 64-Bit Vector Coprocessor:
a New Implementation of High-Performance
Numerical Computation . . . . . . . . . 24--36
Kazuo Nakamura and
Narumi Sakashita and
Yasuhiko Nitta and
Ken'ichi Shimomura and
Takeshi Tokuda Fuzzy Inference and a Fuzzy Inference
Processor . . . . . . . . . . . . . . . 37--48
David K. Kahaner HDTV Research in Japan . . . . . . . . . 49--53
Michael C. Becker and
Michael S. Allen and
Charles R. Moore and
John S. Muhich and
David P. Tuttle The PowerPC 601 Microprocessor . . . . . 54--68
Uwe Kleinhans and
Joerg Kaiser and
Karol Czaja Spearmints: hardware support for
performance measurements in distributed
systems . . . . . . . . . . . . . . . . 69--78
Steven W. White and
Phil D. Hester and
Jack W. Kemp and
G. Jeanette McWilliams How does processor MHz relate to
end-user performance? Part 2: Memory
subsystem and instruction set . . . . . 79--89
D. K. Kahaner Cooperation: Japan's new watchword?
(software industry) . . . . . . . . . . 90--92
A. K. Sood and
J. C. Carson and
M. F. Suer and
R. Raphael Developing $3$D Memories . . . . . . . . 6--7
Stephen L. Diamond Guest Editor's Introduction:
Reengineering Standards . . . . . . . . 8--9
Chris Halliwell Camp development: the art of building a
market through standards . . . . . . . . 10--18
G. Gervaise Davis III War of the words: intellectual property
laws and standardization . . . . . . . . 19--27
D. Linda Garcia Standard setting in the United States:
public and private sector roles . . . . 28--35
Shane Greenstein Micro Economics: Markets, standards, and
the information infrastructure . . . . . 36--51
Andrew Updegrove Forming, funding, and operating
standard-setting consortia . . . . . . . 52--61
Richard Vickers The development of ATM standards and
technology: a retrospective . . . . . . 62--73
Burt Kaliski A Survey of Encryption Standards . . . . 74--81
R. H. Stern Micro Law: Patents and
International-Trade Issues . . . . . . . 89--92
D. Price Cows and Computers . . . . . . . . . . . 95--97
D. Price and
J. H. Crawford Intel Chief Gauges Chip Trends . . . . . 104--104
Richard H. Stern Micro Law: Disassembling Object Code ---
a Misdeed . . . . . . . . . . . . . . . 2--4, 78
Karl E. Grosspietsch Guest Editor's Introduction: Fault
Tolerance . . . . . . . . . . . . . . . 6--7
Johan Karlsson and
Peter Liden and
Peter Dahlgren and
Rolf Johansson and
Ulf Gunneflo Using Heavy-Ion Radiation to Validate
Fault-Handling Mechanisms . . . . . . . 8--23
Janusz Sosnowski Transient Fault Tolerance in Digital
Systems . . . . . . . . . . . . . . . . 24--35
David Powell Distributed Fault-Tolerance --- Lessons
from Delta-4 . . . . . . . . . . . . . . 36--47
Lisa Spainhower and
Thomas A. Gregg and
Ram Chillarege IBM's ES/9000 Model 982S Fault-Tolerant
Design for Consolidation . . . . . . . . 48--59
K. E. Grosspietsch Fault Tolerance in Highly Parallel
Hardware Systems . . . . . . . . . . . . 60--68
John F. Stockton Portable Electronic Storage Systems . . 69--76
B. Briggs The War of the Words Continues . . . . . 2
Richard H. Stern Micro Law: Sweat equity investments . . 3--4, 80
Anonymous How's your computing life going to
evolve in the near future? You might
consider electronic villages and DTP
tools that release engineers and
scientists from dependency on publishing
professionals . . . . . . . . . . . . . 5
Ruby B. Lee Trends in Microprocessor Design . . . . 7--9
Steve Undy and
Mick Bass and
Dave Hollenbeck and
Wayne Kever and
Larry Thayer A Low-Cost Graphics and Multimedia
Workstation Chip Set . . . . . . . . . . 10--22
Peter Yan-Tek Hsu Designing the TFP Microprocessor . . . . 23--33
Keith Diefendorff and
Rich Oehler and
Ron Hochsprung Evolution of the PowerPC Architecture 34--49
Norman P. Jouppi and
Patrick Boyle and
John S. Fitch Designing, packaging, and testing a
300-MHz, 115 W ECL microprocessor . . . 50--58
Nathaniel J. Davis IV and
F. Gail Gray and
Joseph A. Wegner and
Shannon E. Lawson and
Vinay Murthy and
Tennis S. White Reconfiguring fault-tolerant
two-dimensional array architectures . . 60--69
Alan E. Clapp and
Thomas L. Harman Combining microcontroller units and PLDs
for best system design . . . . . . . . . 70--78
G. G. Daivs The War of the Words Continues --- Reply 79--79
Anonymous If you want to learn about computer
organization, here's one book you should
read, especially if you're planning to
teach a course on the subject. Also,
what's happening to conferences? . . . . 2
Richard H. Stern Micro Law: US intellectual property law
can protect almost any technical advance
in neural network design . . . . . . . . 5--5
John Lazzaro and
John Wawrzynek and
Alan Kramer Systems Technologies for Silicon
Auditory Models . . . . . . . . . . . . 7--15
Michel Verleysen and
Philippe Thissen and
Jean-Luc Voz and
Jordi Madrenas An analog processor architecture for a
neural network classifier . . . . . . . 16--28
Alan F. Murray and
Stephen Churcher and
Alister Hamilton and
Andrew J. Holmes and
Geoff B. Jackson and
H. Martin Reekie and
Robin J. Woodburn Pulse Stream VLSI Neural Networks . . . 29--39
Peter Masa and
Klaas Hoen and
Hans Wallinga A High-Speed Analog Neural Processor . . 40--50
Juan M. Moreno and
Francisco Castillo and
Joan Cabestany and
Jordi Madrenas and
Andrzej Napieralski An Analog Systolic Neural Processing
Architecture . . . . . . . . . . . . . . 51--59
Isaac Yi-Yuan Y. Lee and
Sheng-De D. Wang A Versatile Ring-Connected Hypercube . . 60--67
Daniel P. Foty and
Edward J. Nowak MOSFET technology for
low-voltage/low-power applications . . . 68--77
D. Price A surprising source of material ---
organic compounds --- may lead to
devices one-hundredth the size of
current silicon chips . . . . . . . . . 80
D. Delcorso Untitled . . . . . . . . . . . . . . . . 2--3
S. L. Diamond A new PC parallel interface standard
(IEEE Std 1284-1994) . . . . . . . . . . 3, 78
Richard H. Stern Micro Law: Setting Standards on the
Information Superhighway . . . . . . . . 4--5
G. Demicheli Hardware-Software Codesign ---
Introduction . . . . . . . . . . . . . . 8--9
Giovanni De Micheli Computer-Aided Hardware-Software
Codesign . . . . . . . . . . . . . . . . 10--16
Xiaobo Hu and
Joseph G. D'Ambrosio and
Brian T. Murray and
Dah-Lain Tang Codesign of architectures for automotive
powertrain modules . . . . . . . . . . . 17--25
Massimiliano Chiodo and
Paolo Giusto and
Attila Jurecska and
Harry C. Hsieh and
Alberto Sangiovanni-Vincentelli and
Luciano Lavagno Hardware-Software Codesign of Embedded
Systems . . . . . . . . . . . . . . . . 26--36
Pai Chou and
Elizabeth A. Walkup and
Gaetano Borriello Scheduling for Reactive Real-Time
Systems . . . . . . . . . . . . . . . . 37--47
Kunle A. Olukotun and
Rachid Helaihel and
Jeremy Levitt and
Ricardo Ramirez A Software-Hardware Cosynthesis Approach
to Digital System Simulation . . . . . . 48--58
Keith Boland and
Apostolos Dollas Predicting and precluding problems with
memory latency . . . . . . . . . . . . . 59--67
Chu-Sing S. Yang and
Shun-Yue Y. Wu Modular Fault-Tolerant Boolean $
{N}$-Cubes . . . . . . . . . . . . . . . 68--77
D. Price Micro view: Clipper: soon a de facto
standard? . . . . . . . . . . . . . . . 80, 79
Richard H. Stern Micro Law: Tilting at Gates's windmill
(Microsoft licensing) . . . . . . . . . 5--6, 79--80
Richard Mateosian The PowerPC in Perspective . . . . . . . 7--7
S. P. Song and
M. Denman and
J. Chang The PowerPC-604 RISC Microprocessor . . 8--17
T. Potter and
M. Vaden and
J. Young and
N. Ullah Resolution of data and control-flow
dependencies in the PowerPC 601 . . . . 18--29
K. Diefendorff and
E. Silha The PowerPC User Instruction Set
Architecture . . . . . . . . . . . . . . 30--41
M. S. Allen and
M. Alexander and
C. Wright and
J. Chang Designing the PowerPC 60X Bus . . . . . 42--51
Milo Toma\vsevi\'c and
Veljko Milutinovi\'c Hardware Approaches to Cache Coherence
in Shared-Memory Multiprocessors, Part 1 52--59
B. Weiler and
E. Nett SpeedLog. A generic log service
supporting efficient node-crash recovery 60--71
B. Haskell Portable Electronics Packaging
Technologies . . . . . . . . . . . . . . 72--78
D. Delcorso White Beards and Clock Ticks . . . . . . 2--3
M. Fraase The Windows Internet Tour Guide . . . . 5--5
Anonymous Eudora . . . . . . . . . . . . . . . . . 5--6
B. Pfaffenberger Internet in Plain English . . . . . . . 6--6
R. H. Stern Micro Law: a Short Look at Time Bombs 6--7
H. Rajbenbach The Exotic Becomes the Credible . . . . 8--9
M. R. Taghizadeh and
J. M. Miller and
P. Blair and
F. A. P. Tooley Developing Diffractive Optics for
Optical Computing . . . . . . . . . . . 10--19
P. J. Marchand and
P. Ambs Developing a Parallel-Readout
Optical-Disk System . . . . . . . . . . 20--27
E. Lange and
Y. Nitta and
K. Kyuma Optical Neural Chips . . . . . . . . . . 29--41
E. R. Washwell and
G. O. Cheen and
C. H. Huang Optical correlators for space
applications: prospects and problems . . 42--47
F. Reichel and
W. Loeffler and
E. Gaertner Using optical space-frequency analysis
for real-time pattern recognition . . . 49--60
M. Tomasevic and
V. Milutinovic Hardware Approaches to Cache Coherence
in Shared-Memory Multiprocessors, Part 2 61--66
S. L. Diamond Architecture Neutral Distribution Format
(ANDF) . . . . . . . . . . . . . . . . . 73--76
Anonymous Micro View: Spiritual Computing . . . . 80
S. L. Diamond Life-Cycles . . . . . . . . . . . . . . 4--5
Richard H. Stern Micro Law: Hauling manufacturers into
the ITC (US International Trade
Commission) . . . . . . . . . . . . . . 6--7, 80
Paul L. Borrill and
David E. Culler and
Kathleen M. Nichols Hot Interconnects --- Introduction . . . 9--10
R. Minnich and
D. Burns and
F. Hady The Memory-Integrated Network Interface 11--19
Matthias A. Blumrich and
Cezary Dubnicki and
Edward W. Felten and
Kai Li and
Malena R. Mesarina Virtual-Memory-Mapped Network Interfaces 21--28
N. J. Boden and
D. Cohen and
R. E. Felderman and
A. E. Kulawik and
C. L. Seitz and
J. N. Seizovic and
Wen-King K. Su Myrinet --- a Gigabit-per-Second
Local-Area-Network . . . . . . . . . . . 29--36
R. W. Horst Tnet --- a Reliable System Area Network 37--45
T. Von Eicken and
A. Basu and
V. Buch Low-latency communication over ATM
networks using active messages . . . . . 46--53
T. E. Anderson and
D. E. Culler and
D. A. Patterson A Case for NOW (Networks of
Workstations) . . . . . . . . . . . . . 54--64
Yakov I. Fet Vertical Processing Systems --- a Survey 65--75
Stephen L. Diamond Micro Standards: Preparing for global
participation . . . . . . . . . . . . . 76--77
W. H. Auden Nightmail . . . . . . . . . . . . . . . 4--5
Richard H. Stern Micro Law: Microsoft and vaporware:
``Sticking it to Phillippe'' . . . . . . 6--7
Donald Alpert and
Alan Jay Smith Guest Editors' Introduction: Hot Chips
VI . . . . . . . . . . . . . . . . . . . 8--9
Joe Circello and
Greg Edgington and
Dan McCarthy and
James Gay and
David Schimke and
Steven Sullivan and
Richard Duerden and
Chris Hinds and
Danny Marquette and
Lal Sood and
Al Crouch and
Daniel Chow The Superscalar Architecture of the
MC68060 . . . . . . . . . . . . . . . . 10--21
Ruby B. Lee Accelerating multimedia with enhanced
microprocessors . . . . . . . . . . . . 22--32
John H. Edmondson and
Paul Rubinfeld and
Ronald Preston and
Vidya Rajagopalan Superscalar instruction execution in the
21164 Alpha microprocessor . . . . . . . 33--43
Karl Wang and
Chris Bryant and
Mike Carlson and
Tom Elmer and
Adrian Harris and
Michael Garcia and
C. S. Hui and
C. K. Leung and
Brian Reynolds and
Raymond Tang and
Laura Weber and
Jim Wenzel and
Glen Wilson and
Mike Becker Designing the MPC105 PCI bridge/memory
controller . . . . . . . . . . . . . . . 44--49
Janice M. Stone and
Robert P. Fitzgerald Storage in the PowerPC . . . . . . . . . 50--58
Roger D. Chamberlain and
Robert R. Krchnavek Optically interconnected multicomputers
using inverted-graph topologies . . . . 59--69
Bernd Klauer and
Andreas Bleck and
Klaus Waldschmidt The AM$^3$ associative processor . . . . 70--78
Richard Mateosian Micro Review: From the profound to the
mundane: digital mantras and MacInTax 79--80
Stephen L. Diamond Micro Standards: IEEE Std P1394: This
convenient, easy-to-use serial bus
standard supports low-cost desktop and
portable-computing applications . . . . 81--83
Dick Price Pentium FDIV Flaw --- Lessons Learned 88, 86--87
S. L. Diamond Riding the Waves of Technology . . . . . 5--6
Richard H. Stern Micro Law: Fuzziness versus all or
nothing . . . . . . . . . . . . . . . . 7, 77--78
Shane Greenstein Micro Economics: The market and computer
technology . . . . . . . . . . . . . . . 8--9, 78
Hans Peter Graf and
Leonardo M. Reyneri Guest Editors' Introduction: The
Expanding World of Neural and Fuzzy
Systems . . . . . . . . . . . . . . . . 10--11
Herbert Eichfeld and
Martin Klimke and
Manfred Menke and
Jürgen Nolles and
Thomas Künemund A General-Purpose Fuzzy Inference
Processor --- Defining, debugging, and
processing complete fuzzy systems in
real time . . . . . . . . . . . . . . . 12--17
Richard Coggins and
Marwan Jabri and
Barry Flower and
Stephen Pickard A Low-Power Network for On-Line
Diagnosis of Heart Patients --- Boosting
performance of implantable devices that
detect killer arrhythmias . . . . . . . 18--25
Andreas Konig and
Peter Windirsch and
Michael Gasteier and
Manfred Glesner Visual Inspection in Industrial
Manufacturing --- Using a specially
developed, easily trainable, dedicated
VLSI neural network architecture to
detect anomalies . . . . . . . . . . . . 26--31
Eric Cosatto and
Hans Peter Graf A Neural Network Accelerator for Image
Analysis --- Analyzing complex images by
decomposing them into a hierarchy of
simple, ``building-block'' shapes . . . 32--38
Marcello Chiaberge and
Leonardo M. Reyneri Cintia: a Neuro-Fuzzy Real-Time
Controller for Low-Power Embedded
Systems --- Supporting a variety of
intelligent control strategies . . . . . 40--47
Hans Peter Graf and
Leonardo M. Reyneri Neural Networks --- Extraordinary
Variation . . . . . . . . . . . . . . . 48--59
D. C. Burns and
I. Underwood and
A. F. Murray and
D. G. Vass An optoelectronic Neural Network with
Temporally Multiplexed Gray-Scale
Weights . . . . . . . . . . . . . . . . 49--51
Steven R. Skinner and
James E. Steck and
Elizabeth C. Behrman Optical neural network using Kerr-type
nonlinear materials . . . . . . . . . . 52--54
Graham Cairns and
Lionel Tarassenko Precision issues for learning with
analog VLSI multilayer perceptrons . . . 54--56
Stefan Ruping and
Karl Goser and
Ulrich Ruckert A Chip for Self-Organizing Feature Maps 57--59
Ahmed Louri and
James A. Hatch, Jr. and
Jongwhoa Na A Constant-Time Parallel Sorting
Algorithm and Its Optical Implementation
--- Using optics to achieve newer and
more efficient solutions to old problems 60--71
Richard Mateosian Past Themes . . . . . . . . . . . . . . 72--74
Anonymous Micro Review: The Internet, WWW, and
tools to get you there . . . . . . . . . 72
Anonymous Micro News: 3D stacked memory, network
attack scanner . . . . . . . . . . . . . 75
Richard H. Stern Micro Law: The PTO on software patents 2--3, 77--78
Shane Greenstein Micro economics: Diamonds are forever;
computers are not . . . . . . . . . . . 4--5
Abraham Kandel Guest Editor's introduction: The fuzzy
boom . . . . . . . . . . . . . . . . . . 6--7
Tsutomu Miki and
Takeshi Yamakawa Fuzzy Inference on an Analog Fuzzy Chip 8--18
Witold Pedrycz and
C. Hart Poskar and
Peter J. Czezowski A reconfigurable fuzzy neural network
with in-situ learning . . . . . . . . . 19--30
Donald L. Hung Dedicated Digital Fuzzy Hardware . . . . 31--39
Hartmut Surmann and
Ansgar P. Ungering Fuzzy-rule-based systems on general
purpose processors . . . . . . . . . . . 40--48
Fernando Vidal-Verdu and
Angel Rodriguez-Vazquez Using building blocks to design analog
neuro-fuzzy controllers . . . . . . . . 49--57
Michael K. Milligan and
Harvey G. Cragon Processor Implementations Using Queues 58--66
Timothy J. Drabik and
Albert H. Titus and
Mark A. Handschy and
David Banas and
Stephen D. Gaalema and
David J. Ward $2$D silicon/ferroelectric liquid
crystal spatial light modulators . . . . 67--76
R. A. Pease 3rd Thoughts on Fuzzy-Logic . . . . . . 78--80
Anonymous Micro view: Are claims made for fuzzy
logic preposterous or true? . . . . . . 80
Richard Mateosian Micro Review: Upgrading to Windows 95
won't be painless, but you can do it.
Also, how should we address Internet
privacy and publishing concerns? . . . . 2--3, 84--85
Richard Mateosian Backlog . . . . . . . . . . . . . . . . 2
Shane Greenstein Micro Economics: Why aren't the
mainframes disappearing as fast as
everyone thought? . . . . . . . . . . . 4--5
Gianluigi Castelli Guest Editor's Introduction: The
Seemingly Unlimited Market for
Microcontroller-Based Embedded Systems 6--8
Vijay K. Madisetti and
Thomas W. Egolf Virtual prototyping of embedded
microcontroller-based DSP systems . . . 9--21
Simon Segars and
Keith Clarke and
Liam Goudge Embedded control problems, Thumb, and
the ARM7TDMI . . . . . . . . . . . . . . 22--30
Michael Dolle and
Manfred Schlett A cost-effective RISC/DSP microprocessor
for embedded systems . . . . . . . . . . 32--40
Gianluigi Castelli and
Gianluca Ragazzini EOS --- a Real-Time Operating System
Adapts to Application Architectures . . 41--49
Manthos A. Tsoukarellas and
Vasilis C. Gerogiannis and
Kostis D. Economides Systematically Testing a Real-Time
Operating System . . . . . . . . . . . . 50--60
Luis de Salvador and
Julio Gutierrez A multilevel systolic approach for fuzzy
inference hardware . . . . . . . . . . . 61--71
Michael Bekerman and
Avi Mendelson A performance analysis of Pentium
processor systems . . . . . . . . . . . 72--83
J. Wilson Data-Security Hits Home . . . . . . . . 86--88
Janet Wilson Micro View: Anyone who doesn't design
computer networks for security is
providing irresponsible engineering . . 88, 86--87
Stephen L. Diamond From the Editor-in-Chief --- Introducing
Micro Web and $ \mu $RAP . . . . . . . . 2--2
Shane Greenstein Micro Economics: Operating systems, soap
operas: What's the difference? . . . . . 3--4
Tom Pittman Micro View: The RISC penalty . . . . . . 5, 76--80
Richard H. Stern Micro Law: Winsocking the competition 6--7
Ken Sakamura Guest Editor's Introduction:
Microelectronics in Japan . . . . . . . 8--10
Atsushi Hasegawa and
Ikuya Kawasaki and
Kouji Yamada and
Shinichi Yoshioka and
Shumpei Kawasaki and
Prasenjit Biswas SH3 --- High Code Density, Low-Power . . 11--19
Kouhei Nadehara and
Ichiro Kuroda and
Masayuki Daito and
Takashi Nakayama Low-Power Multimedia RISC . . . . . . . 20--29
Masaki Kumanoya and
Toshiyuki Ogawa and
Kazunari Inoue Advances in DRAM Interfaces . . . . . . 30--36
Makoto Awaga and
Tatsushi Ohtsuka and
Hideki Yoshizawa and
Shigeru Sasaki $3$D Graphics Processor Chip Set . . . . 37--45
Hiroaki Takada and
Ken Sakamura $ \mu $ITRON for small-scale embedded
systems . . . . . . . . . . . . . . . . 46--54
Angel L. Enriquez and
Adel H. Eltimsahy and
Mohsin M. Jamali Flexible Control for Robot Manipulators 55--60
Anonymous Call for Articles --- August 1996
special issue on media processing:
native and digital signal processing
approaches . . . . . . . . . . . . . . . 60
Abraham Kandel and
Giuseppe Ascia and
Vincenzo Catania and
Biagio Giacalone and
Marco Russo and
Lorenzo Vita and
Andres Jaramillo-Botero and
Yoichi Miyake and
Hua Harry Li and
Nowell Godfrey and
Yuandong Ji and
Shuwei Guo and
Liliane Peters and
Krishna Rao Valavala and
Mahmoud A. Manzoul and
Antonio Ruiz and
Julio Gutierrez and
J. A. Felipe Fernandez Fuzzy Hardware Challenges . . . . . . . 61--67
G. Ascia and
V. Catania and
B. Giacalone and
M. Russo and
L. Vita Designing for Parallel Fuzzy Computing 62--62
A. Jaramillo-Botero and
Y. Miyake Parallel, High-Speed PC Fuzzy Control 63--63
H. H. Li and
N. Godfrey and
Yuandong D. Ji A fuzzy logic beam-and-ball controller
prototype . . . . . . . . . . . . . . . 64--64
S. W. Guo and
L. Peters A high-speed, reconfigurable fuzzy logic
controller . . . . . . . . . . . . . . . 65--65
K. Rao Valavala and
M. A. Manzoul A Fuzzy Partitioning System . . . . . . 66--66
A. Ruiz and
J. Gutierrez and
J. A. Felipe Fernandez A fuzzy controller with an optimized
defuzzification algorithm . . . . . . . 67--67
Richard Mateosian Micro Review: Fireside reading: How is
technology shaping our lives? . . . . . 74--75
T. Pittman RISC Versus CISC --- Reply . . . . . . . 2--2
A. Ruiz and
J. Gutierrez and
J. A. F. Fernandez Correction: A Fuzzy Controller with an
Optimized Defuzzification Algorithm
(vol. 15, p. 67, 1995) . . . . . . . . . 2--2
J. Schachner RISC Versus CISC . . . . . . . . . . . . 2--2
Anonymous News --- Celebrating the 25th
anniversary of the microprocessor . . . 3--3
Anonymous Computer Society Turns 50 . . . . . . . 4--4
Anonymous Smart Cards Get Wise . . . . . . . . . . 4--4
Anonymous Verilog HDL Becomes IEEE Standard . . . 4--4
Richard Mateosian Micro Review: \em The Road Ahead
outlines Gates' vision of the coming
information highway and the critical
issues it presents . . . . . . . . . . . 5--6, 72
Richard H. Stern Micro Law: Should a BB or net access
provider be liable for copyright
infringement when a user posts
infringing material on a user newsgroup
of forum? . . . . . . . . . . . . . . . 7--9, 70--72
Thomas E. Anderson and
Kathleen M. Nichols and
Vivian Shen Guest Editors' Introduction: Developing
Interconnect Technology . . . . . . . . 10--11
Richard B. Gillett Memory Channel Network for PCI . . . . . 12--18
David R. Engebretsen and
Daniel M. Kuchta and
Richard C. Booth and
John D. Crow and
Wayne G. Nation Parallel Fiber-Optic SCI Links . . . . . 20--26
Steve Scott The GigaRing Channel . . . . . . . . . . 27--34
David E. Culler and
Lok Tin Liu and
Richard P. Martin and
Chad O. Yoshikawa Assessing Fast Network Interfaces . . . 35--43
Stuart Cheshire and
Mary Baker A Wireless Network in MosquitoNet . . . 44--52
Alexander G. Fraser Future Wan Telecommunications . . . . . 53--57
Mayan Moudgill and
Stamatis Vassiliadis Precise Interrupts . . . . . . . . . . . 58--67
Shane Greenstein Micro Economics: a case study
illustrates innovative computing and
what makes it work . . . . . . . . . . . 68--69
B. Burgess What RISC Penalty? . . . . . . . . . . . 79--80
T. Pittman RISC Proponents in Denial . . . . . . . 2--2
Shane Greenstein Micro economics: Why should technical
curmudgeons celebrate the
microprocessor's anniversary? . . . . . 3--4
Richard H. Stern Micro Law: Patenting software, revisited 5, 77--79
Norman P. Jouppi and
Hasan S. Alkhatib Guest Editors' introduction: Hot chips
and the microprocessor . . . . . . . . . 6--7
David B. Papworth Tuning the Pentium Pro
microarchitecture: Refining a design
from the initial goals, performance
simulations, trade-offs, and dies to the
final product . . . . . . . . . . . . . 8--15
Dave Christie Developing the AMD-K5 architecture:
Flying without instruments: the
independent development on the x86
processor . . . . . . . . . . . . . . . 16--26
Kenneth C. Yeager The MIPS R10000 superscalar
microprocessor: Emphasizing concurrency
and latency-hiding techniques to
efficiently run large, real-world
applications . . . . . . . . . . . . . . 28--41
Marc Tremblay and
J. Michael O'Connor UltraSparc I: a four-issue processor
supporting multimedia: Combining on-chip
multimedia instructions with a
high-performance, four-issue
architecture . . . . . . . . . . . . . . 42--50
Toshio Kondo and
Kazuhito Suguri and
Mitsuo Ikeda and
Tetsuya Abe and
Hiroaki Matsuda and
Tsuneo Okubo and
Kenji Ogura and
Yutaka Tashiro and
Naoki Ono and
Toshihiro Minami and
Ritsu Kusaba and
Takeshi Ikenaga and
Nobutaro Shibata and
Ryota Kasai and
Koji Otsu and
Fumiaki Nakagawa and
Yasuhiko Sato Two-chip MPEG-2 video encoder: Switching
to simple profile at main level for a
cost-effective encoder . . . . . . . . . 51--58
Weijia J. Jia and
Jorg Kaiser and
Edgar Nett RMP: Fault-tolerant group communication:
Rethinking the token ring approach to
decrease overhead and increase
reliability . . . . . . . . . . . . . . 59--67
Jason Moore and
Mahmoud A. Manzoul An interactive fuzzy CAD tool: Mapping
fuzzy controllers onto VLSI systolic
arrays . . . . . . . . . . . . . . . . . 68--74
Richard Mateosian Micro Review: The microprocessor at 25:
It's invisible . . . . . . . . . . . . . 75--76
Shane Greenstein Micro Economics: Shooting for par: Are
designers and consumers playing on the
same course? . . . . . . . . . . . . . . 2, 79
Richard Mateosian Micro Review: Unlike C++, which seeks to
extend C and maintain a large degree of
backward compatibility, Java starts from
C and rips out its most troublesome and
error-prone features . . . . . . . . . . 3--5
Richard H. Stern Micro Law: Net access --- divvying up
the pie . . . . . . . . . . . . . . . . 6--9
Mahdi Abdelguerfi and
Burton S. Kaliski, Jr. and
Wayne Patterson Guest Editors' Introduction: Public-Key
Security Systems . . . . . . . . . . . . 10--13
David Naccache and
David M'Ra\"\ihi Cryptographic Smart Cards --- Comparing
the existing cryptography-dedicated
microprocessors and describing possible
directions for their evolution . . . . . 14, 16--24
S. Ondrusch Toward Available Personal Security
Tokens . . . . . . . . . . . . . . . . . 15--15
C. H. Fancher Motorola's SC-49 --- a Public-Key
Microcontroller . . . . . . . . . . . . 18--18
Çetin Kaya Koç and
Tolga Acar and
Burton S. Kaliski, Jr. Analyzing and Comparing Montgomery
Multiplication Algorithms --- Assessing
five algorithms that speed up modular
exponentiation, the most popular method
of encrypting and signing digital data 26--33
Andre Zuquete and
Paulo Guedes Transparent Authentication and
Confidentiality for Stream Sockets:
Ensuring private network communications
for Unix and Windows systems . . . . . . 34--41
Jean-François Dhem and
Daniel Veithen and
Jean-Jacques Quisquater SCALPS: Smart Card for Limited Payment
Systems: Merging a processor and a
coprocessor on a fast, secure, low-cost
chip dedicated to public-key
cryptography . . . . . . . . . . . . . . 42--51
L. Hollaar and
A. Asay Legal Recognition of Digital-Signatures 44--45
Saman P. Amarasinghe and
Jennifer M. Anderson and
Christopher S. Wilson and
Shih-Wei Liao and
Brian R. Murphy and
Robert S. French and
Monica S. Lam and
Mary W. Hall Multiprocessors from a Software
Perspective --- Automatically
parallelizing benchmark programs to
yield the highest SPECfp ratios recorded 52--61
Giuseppe Ascia and
Vincenzo Catania and
Marco Russo and
Lorenzo Vita Rule-Driven VLSI Fuzzy Processor ---
Implementing a scalable inference
processor with analog fuzzy gates . . . 62--74
Stephen L. Diamond Micro Standards: IEEE Std 1394-1955 High
Performance Serial Bus is ready for
second-generation standardization . . . 75--78
Shane Greenstein Micro Economics: Is the productivity
paradox to blame for your computing
woes? . . . . . . . . . . . . . . . . . 2--3
Richard H. Stern Micro Law: Anti-knockoff article
protection law . . . . . . . . . . . . . 4--5
Ruby B. Lee and
Michael D. Smith Guest Editors' Introduction: Media
Processing: a New Design Target . . . . 6--9
Marc Tremblay and
J. Michael O'Connor and
Venkatesh Narayanan and
Liang He VIS Speeds New Media Processing ---
Enhancing conventional RISC instruction
sets to significantly accelerate
media-processing algorithms . . . . . . 10--20
Jeremiah Golston Single-Chip H.324 Videoconferencing ---
Using the TMS320C82 DSP for multimedia
processing in cost-sensitive consumer
and PC markets . . . . . . . . . . . . . 21--33
Craig Hansen MicroUnity's MediaProcessor
Architecture: Extending general-purpose
systems for media processing and
communications while reducing initial
and life cycle system costs . . . . . . 34--41
Alex Peleg and
Uri Weiser MMX Technology Extension to the Intel
Architecture --- Improving multimedia
and communications application
performance by 1.5 to 2 times . . . . . 42--50
Ruby B. Lee Subword Parallelism with MAX-2:
Accelerating media processing with a
minimal set of instruction extensions
supporting efficient subword parallelism 51--59
Antonio J. Torralba and
Jorge Chavez and
L. G. Franquelo Fuzzy-Logic-Based Analog Design Tools
Combining fuzzy logic with conventional
approaches to automate difficult analog
design tasks . . . . . . . . . . . . . . 60--68
Ran Giladi Evaluating the Mflops Measure: Searching
for a consistent performance measure to
cover a variety of computer
configurations . . . . . . . . . . . . . 69--75
Richard Mateosian Micro Review: Books, books, books . . . 77--79
Anonymous Virtual Socket Interface Alliance . . . 4--4
Anonymous Micro News: Extreme-Ultraviolet
Lithography 2 Steps Closer . . . . . . . 2
Anonymous Micro News: Virtual Socket Interface
Alliance . . . . . . . . . . . . . . . . 2
S. Diamond Micro News: Fletcher Buckley, 30-Year CS
Volunteer, Dies . . . . . . . . . . . . 2
Anonymous New $3$D Display Technology . . . . . . 4
Richard H. Stern Micro Law: Patents on selling via the
Net --- really? . . . . . . . . . . . . 6--7, 74--75
Richard Mateosian Micro Review: Software that makes your
life easier . . . . . . . . . . . . . . 8--9, 75
Anonymous Hotmetal-Pro-3.0 for Windows . . . . . . 9--9
Anonymous Visual-Slickedit-V2.0 for Windows 95 . . 9
Eric A. Vittoz and
Jean-Daniel D. Nicoud Guest Editors' Introduction:
Biology-lnspired Circuits . . . . . . . 10--11
Marc Duranton Image Processing by Neural Networks:
Tackling real-world image analysis
problems with a 12-DSP vector processor 12--19
Alan H. Kramer Array-Based Analog Computation:
Computing billions of regular low-level
operations efficiently on mW of power 20--29
Kwabena A. Boahen A Retinomorphic Vision System ---
Mimicking the structure and function of
the vertebrate retina to optimize the
information-gathering capacity of
machine-vision systems . . . . . . . . . 30--39
Giacomo Indiveri and
Jorg Kramer and
Christof Koch System Implementations of Analog VLSI
Velocity Sensors --- Developing
architectures that incorporate new,
compact velocity sensors for
applications in space exploration,
driver assistance, and autonomous
navigation . . . . . . . . . . . . . . . 40--49
Olivier Landolt Analog Nonlinear Function Synthesis ---
Designing low-power microsensor,
microactuator interfaces . . . . . . . . 50--52
Bhusan Gupta and
Rodney Goodman and
Fukang Jiang and
Yu-Chong Tai and
Steev Tung and
Chih-Ming Ho Analog VLSI System for Active Drag
Reduction --- Using a biological
inspiration to build a drag-reducing
surface with VLSI technology . . . . . . 53--59
Claus Assmann and
Andreas Huth Compiling C on a Multiple-Stack
Architecture --- Introducing Fast, a
RISC processor designed for functional
language needs, and its C compiler . . . 60--67
Jon Tombs and
Antonio J. Torralha and
Leopoldo G. Franguelo A PWM Fuzzy Logic Controller: Using
pulse width modulation to improve fuzzy
digital controller design . . . . . . . 68--71
Shane Greenstein Micro Economics: Repetitive stress
injuries: Who pays? . . . . . . . . . . 72--73
Anonymous Electronic Library, Bookstore . . . . . 76--76
Anonymous IBM Unveils Network Computer . . . . . . 76--76
Anonymous Wireless LANs Standardization . . . . . 76--76
Anonymous Micro View: Can designers resist the
allure of sexy, high-visibility apps? 80--80
J. Wilson An Outsider's View . . . . . . . . . . . 80--80
S. L. Diamond Celebrating the Microprocessor . . . . . 2--3
Anonymous Exponential Speeds for PowerPC . . . . . 3--3
Anonymous Micro News: 533-MHz processor, laurels
for the 8051, CS publisher retires . . . 3, 80
Anonymous Will the Net Self-Destruct . . . . . . . 3
Richard H. Stern Micro Law: Patenting computerized
methods of doing business . . . . . . . 4--6, 75
Federico Faggin Guest Editors' Introduction --- The
Microprocessor . . . . . . . . . . . . . 7--9
Federico Faggin and
Marcian E. Hoff, Jr. and
Stanley Mazor and
Masatoshi Shima The History of the 4004 --- The 4004
design team tells its story . . . . . . 10--20
H. Smith Marketing the Early Microprocessors . . 18--18
R. Gary Daniels A Participant's Perspective --- The
``father'' of the 6805 MCU relates his
role in the history of the
microprocessor . . . . . . . . . . . . . 21--31
R. A. Shaffer The Personal-Computer . . . . . . . . . 23--23
J. Hennessy RISC Microprocessors . . . . . . . . . . 27--27
P. Smith Microprocessor Design in the Mid-1990s 29--29
Michael Slater The Microprocessor Today --- MicroDesign
Resources' founder outlines technology
and business issues in today's
microprocessor industry . . . . . . . . 32--44
Albert Y. C. Yu The Future of Microprocessors ---
Intel's head of microprocessor products
looks 10 years ahead to 2006 . . . . . . 46--53
C. A. Mead Scaling of MOS Technology . . . . . . . 48--48
J. Moussouris Mediaprocessors . . . . . . . . . . . . 51--51
G. Bell The System-on-a-Chip, Microsystems
Computer Industry . . . . . . . . . . . 52--52
John Markoff The Microprocessor's Impact on Society:
At 25 years old, has the microprocessor
fulfilled its early promise? What does
it offer for the future? . . . . . . . . 54--59
Alberto Ferrari and
Antonella Bellettini and
Roberto Guerrieri and
Giorgio Baccarani An ASIC Chip Set for Parallel Fuzzy
Database Mining --- Parallel hardware
that executes fuzzy queries speeds up a
computationally intensive task . . . . . 60--67
Anonymous 1996 Annual Index --- Volume 16 --- This
section provides a complete author and
subject listing . . . . . . . . . . . . 68--73
S. L. Diamond Micro Standards: SyncLink: High-speed
DRAM for the future . . . . . . . . . . 74--75
Richard Mateosian Micro Review: Heavy-duty publishing: the
thud factor . . . . . . . . . . . . . . 77--77
Shane Greenstein Micro Economics: Don't call it a
highway! . . . . . . . . . . . . . . . . 78--79
Anonymous China Legend Chooses K5 . . . . . . . . 80--80
Anonymous DVDs to Overtake CDs at Millennium . . . 80--80
Anonymous Javastation Arrives . . . . . . . . . . 80--80
Anonymous Longtime CS Publisher Retires . . . . . 80--80
Shane Greenstein Micro Economics: How coinvention shapes
our market . . . . . . . . . . . . . . . 2--3
Anonymous Micro Review: The Microsoft Way;
object-relational databases . . . . . . 4--6
Anonymous Advanced Encryption Standard . . . . . . 6--6
Anonymous 56-Kbps Modems to Come . . . . . . . . . 6--6
Anonymous TI Drops Off Intel Bandwagon . . . . . . 6--6
Anonymous X-Ray Resolution Times 10 . . . . . . . 6
Qiang N. Li and
Chuck Thacker and
Kai Li Guest Editors' Introduction: The Hottest
Interconnects . . . . . . . . . . . . . 7--7
Stefanos N. Damianakis and
Angelos Bilas and
Cezary Dubnicki and
Edward W. Felten Client-Server Computing on Shrimp ---
Delivering almost undiminished hardware
performance to user applications . . . . 8--18
Richard Gillett and
Richard Kaufmann Using the Memory Channel Network: Using
a cluster of standard PCI-based servers
with a low-cost network to improve
communication performance . . . . . . . 19--25
Nick McKeown and
Martin Izzard and
Adisak Mekkittikul and
William Ellersick and
Mark Horowitz Tiny Tera: a Packet Switch Core: Using
new scheduling algorithms to build a
1-terabits packet switch with a central
hub no larger than a can of soda . . . . 26--33
Mike Galles Spider: a High-Speed Network
Interconnect --- Raising the bandwidth
ceiling with a scalable, pipelined
interconnect for distributed endpoint
routing . . . . . . . . . . . . . . . . 34--39
David J. Skellern and
L. H. Charles Lee and
Tom McDermott and
Neil H. E. Weste and
John Dalton and
Jeffrey Graham and
Tan F. Wong and
Andrew F. Myles and
Terence M. P. Percival and
Philip J. Ryan A High-Speed Wireless LAN --- Using
millimeter-wave frequencies, which can
accommodate link speeds of hundreds of
Mbits per second, for indoor
communications systems . . . . . . . . . 40--47
William J. Dally and
John Poulton Transmitter Equalization for 4-Gbps
Signaling --- Applying the density and
speed of modern VLSI technology to
overcome the I/O bottleneck with
high-speed signaling . . . . . . . . . . 48--56
Fadi N. Sibai and
Sunil D. Kulkarni A Time-Multiplexed Reconfigurable
Neuroprocessor --- Combining analog and
digital technology in a neuroprocessor
using time-multiplexed pulse stream
communication . . . . . . . . . . . . . 58--65
Alessandra Costa and
Alessandro De Gloria and
Fabrizio Giudici and
Mauro Olivieri Fuzzy Logic Microcontroller: Limiting
system costs for fuzzy control
applications by optimizing data
structures and hardware . . . . . . . . 66--74
Richard H. Stern Micro Law: Shrink-wrap license
restrictions --- preempted? . . . . . . 75--78
Anonymous New Process Battles Warpage . . . . . . 78--78
Anonymous Support for 533-MHz Processor . . . . . 78--78
J. Wilson Micro View: VSI Alliance: Selfish
interests the key? . . . . . . . . . . . 80--80
Anonymous Micro View: VSI Alliance: Selfish
interests the key? . . . . . . . . . . . 80
J. Wharton Letters: Setting the record straight . . 2--2
Anonymous Smart Phones Debut in Japan . . . . . . 2--3
Anonymous Micro News: ACM's 50th . . . . . . . . . 3--3
Anonymous Micro Review: Only the paranoid survive;
recent Java books . . . . . . . . . . . 4--77
S. Greenstein Micro Economics: Why fun is so often
associated with our technology . . . . . 5--6
R. H. Stern Micro Law: AOL: essential for sending
junk e-mail? . . . . . . . . . . . . . . 7--8
Winfried Wilcke and
Robert Garner Guest Editors' Introduction: Celebrating
Chips and Architectures . . . . . . . . 9--10
Martin Randall Talisman --- Multimedia for the PC . . . 11--19
Paul Kalapathy Hardware-Software Interactions on Mpact 20--26
Ashok Kumar The HP PA-8000 RISC CPU . . . . . . . . 27--32
David Patterson and
Thomas Anderson and
Neal Cardwell and
Richard Fromm and
Kimberly Keeton and
Christoforos Kozyrakis and
Randi Thomas and
Katherine Yelick A Case for Intelligent RAM . . . . . . . 34--44
J. Michael O'Connor and
Marc Tremblay Picojava-I --- The Java Virtual Machine
in Hardware . . . . . . . . . . . . . . 45--53
Alex Semenov and
Albert M. Koelmans and
Lee Lloyd and
Alexandre Yakovlev Designing an Asynchronous Processor
Using Petri Nets . . . . . . . . . . . . 54--64
Alfredo Sanz A Unified Tool for Fuzzy/Neural Network
Systems . . . . . . . . . . . . . . . . 65--69
G. S. Robinson Micro Standards: Active projects list 70--75
Anonymous Micro Standards: Active projects list 70--75
M. Weatherford Micro View: MOSIS eyes the future . . . 80, 79
Richard Mateosian Real Sips . . . . . . . . . . . . . . . 3--5
Anonymous Micro Review: Java, SGML: Destabilizing
forces for companies and careers? . . . 3--5
B. Sanders Javaone-97 --- Catching the Buzz . . . . 5--6
Anonymous Intel vs DEC . . . . . . . . . . . . . . 6--6
Anonymous Motorola Ships 2 Billionth 68HC05 . . . 6--6
Anonymous Quick-Turn MCM Prototypes . . . . . . . 6--6
R. H. Stern Micro Law: Content pirates, beware! . . 7--9, 76--77
Ken Urquhart Guest Editor's Introduction: Java's Open
Future . . . . . . . . . . . . . . . . . 10--13
Li Gong Java Security: Present and Near Future:
Coping with the rapidly evolving
security issues of cross-platform
computing . . . . . . . . . . . . . . . 14--19
Vartan Piroumian Internationalization Support in Java:
Making software globalization easy . . . 20--29
Stuart Ritchie Systems Programming in Java: Reducing
complexity and shortening debugging time
by using Java at the system level . . . 30--35
Timothy Cramer and
Richard Friedman and
Terrence Miller and
David Seherger and
Robert Wilson and
Mario Wolczko Compiling Java Just in Time: Using
runtime compilation to improve Java
program performance . . . . . . . . . . 36--43
Ann Wollrath and
Jim Waldo and
Roger Riggs Java-Centric Distributed Computing:
Providing a homogeneous view of a
heterogeneous group of machines . . . . 44--53
Bruce R. Montague JN: OS for an Embedded Java Network
Computer: Supporting Java's Virtual
Machine on a single-chip embedded PC
attached to the Internet . . . . . . . . 54--60
Vincenzo Catania and
Michele Malgeri and
Marco Russo Applying Fuzzy Logic to Codesign
Partitioning --- Using soft computing
techniques to automate partitioning for
hardware-software codesign . . . . . . . 62--70
G. S. Robinson Micro Standards: So, you want fast-track
standards . . . . . . . . . . . . . . . 71--72
S. Greenstein Micro Economics: Let's play Monopoly . . 73--74
M. Weatherford Micro View: IBM bets on JavaBeans . . . 80
Anonymous Micro News: Lattices --- a New Key for
Cryptography . . . . . . . . . . . . . . 2--2
Anonymous Micro News: a Monopoly on Naming . . . . 2--2
S. Greenstein Micro Economics: Can biology explain the
economics of technology? . . . . . . . . 3--5
G. S. Robinson Micro Standards: How does the IEEE do
it? . . . . . . . . . . . . . . . . . . 5--6
Anonymous Micro Review: Deep and ambitious books
for lazy summer days . . . . . . . . . . 7--8
Dave Jaggar Guest Editor's Introduction: ARM
Architecture and Systems: ARM licenses
three basic processor cores for
high-performance, low-cost, and
low-power implementations . . . . . . . 9--11
Simon Segars ARM7TDMI Power Consumption: Reducing
power in CPUs for portable and handheld
products through efficient circuit- and
system-level design . . . . . . . . . . 12--19
David Flynn AMBA: Enabling Reusable On-Chip Designs:
Supporting the first-time-right design
of low-power embedded systems . . . . . 20--27
Richard W. Earnshaw and
Lee D. Smith and
Kevin Welton Challenges in Cross-Development: Coping
with debugging and simulation for
increasingly complex deeply embedded
systems . . . . . . . . . . . . . . . . 28--36
Dave Walsh Reducing System Cost with Software
Modems: Accelerating product
development, simplifying international
approval, and ensuring upgradability . . 37--43
Lyle Adams and
Michael Ou Processor Integration in a Disk
Controller: Embedding a RISC processor
in a complex ASIC to reduce cost and
improve performance . . . . . . . . . . 44--48
George Milne and
Ashis Khan and
Simon Rayne and
Juha Christensen Microcontroller Design Advantages for
Portable Computing: Using the ARM7100
microcontroller to enable two OEM
applications to reach the market quickly 49--55
Peter Soderquist and
Miriam Leeser Division and Square Root: Choosing the
Right Implementation: Exploring the
major design choices for microprocessor
implementations of floating-point
division and square root . . . . . . . . 56--66
Cosimo Antonio Prete and
Marco Graziano and
Francesco Lazzarini The ChARM Tool for Tuning Embedded
Systems: Selecting and tuning system
configurations to meet cost,
performance, and power consumption
requirements . . . . . . . . . . . . . . 67--76
R. H. Stern Micro Law: Being right isn't everything 77--78
Anonymous All-Electronic Journal . . . . . . . . . 79--79
Anonymous Measuring Submicron Dimensions . . . . . 79--79
Anonymous Spec Benchmark for MPEG-2 . . . . . . . 79--79
Anonymous Product Summary . . . . . . . . . . . . 79
R. H. Stern Micro Law: The tyranny of paradigms . . 3--4
R. M. Mateosian Micro News: Visiting Hot Chips IX . . . 5, 72
R. M. Mateosian Micro News: DARPA aids Tera MTA . . . . 5--6
Anonymous Building a Single-Electron Diode . . . . 6--6
Anonymous Optimizing the IA-64 . . . . . . . . . . 6--6
Anonymous Studying Extreme-Ultraviolet . . . . . . 6--6
Anonymous Year 2000 Compliance . . . . . . . . . . 6
S. Greenstein Micro Economics: Convergence hype . . . 7--8
G. S. Robinson Micro Standards: Truth and spurious
urban myths . . . . . . . . . . . . . . 9--10
Anonymous 1998 Editorial Calendar . . . . . . . . 11
Susan J. Eggers and
Joel S. Emer and
Henry M. Levy and
Jack L. Lo and
Rebecca L. Stamm and
Dean M. Tullsen Simultaneous Multithreading: a Platform
for Next-Generation Processors . . . . . 12--19
Roger Espasa and
Mateo Valero Exploiting Instruction-Level and
Data-Level Parallelism . . . . . . . . . 20--27
Dezsõ Sima Superscalar Instruction Issue . . . . . 28--39
Chenxi X. Zhang and
Xiaodong D. Zhang and
Yong Yan Two Fast and High-Associativity Cache
Schemes . . . . . . . . . . . . . . . . 40--49
R. González and
A. Torralba and
L. G. Franquelo AFAN --- Tool for Optimizing Fuzzy
Controllers . . . . . . . . . . . . . . 50--54
R. M. Suresh babu and
B. B. Biswas and
G. Govindarajan Developing Highly Reliable Software . . 56--63
Michel Cekleov and
Michel Dubois Virtual-Address Caches, Part 1: Problems
and Solutions in Uniprocessors . . . . . 64--71
Anonymous Consuming Less Power . . . . . . . . . . 72--72
Anonymous Integrating Image Sensor, Signal
Conditioner . . . . . . . . . . . . . . 72--72
Anonymous Micro Review: Bending computers to our
will . . . . . . . . . . . . . . . . . . 74--76
Anonymous Product Summary . . . . . . . . . . . . 77
J. R. Hurt Micro View: OMIs collaborative approach 80, 79
R. H. Stern Micro Law: Episode 2, Part 1: The
browser wars . . . . . . . . . . . . . . 2--5
S. Greenstein Micro Economics: Looking at software
from an academic perspective . . . . . . 6--7
Ken Sakamura Guest Editors' Introduction: DRAM
Technology . . . . . . . . . . . . . . . 8--9
Yasunao Katayama Trends in Semiconductor Memories . . . . 10--17
Richard Crisp Direct Rambus Technology: The Next Main
Memory Standard . . . . . . . . . . . . 18--28
Peter Gillingham and
Bill Vogley SLDRAM --- High-Performance,
Open-Standard Memory . . . . . . . . . . 29--39
Y. Nunomura and
T. Shimizu and
O. Tomisawa M32R/D---Integrating DRAM and
Microprocessor . . . . . . . . . . . . . 40--48
Yasuhiro Nanomura and
Toru Shimizu and
Osamu Tomisawa M32R/D---Integrating DRAM and
Microprocessor . . . . . . . . . . . . . 40--48
Ichiro Sase and
Nobuyuki Shimizu and
Takashi Yoshikawa Multimedia LSI Accelerator with Embedded
DRAM . . . . . . . . . . . . . . . . . . 49--54
Doug Burger and
James R. Goodman and
Alain Kägi Limited Bandwidth to Affect Processor
Design . . . . . . . . . . . . . . . . . 55--62
Robert L. Geiger and
James D. Solomon and
Kenneth J. Crisler Wireless Network Extension Using Mobile
IP . . . . . . . . . . . . . . . . . . . 63--68
Michel Cekleov and
Michel Dubois Virtual-Address Caches, Part 2:
Multiprocessor Issues . . . . . . . . . 69--74
Anonymous 1997 Annual Index-Complete Author and
Subject Listings . . . . . . . . . . . . 75
G. S. Robinson Micro Standards: ANSI's role in
developing standards . . . . . . . . . . 84--85
Richard Mateosian Micro Review: Adobe Framemaker-5.5 for
Windows, Macintosh, and UNIX Systems . . 86--88
Richard Mateosian Micro Review: MKS-Toolkit-6.1 for
Windows-95 and Windows-NT . . . . . . . 87--87
Anonymous Special Features . . . . . . . . . . . . ??
G. S. Robinson Java and the PAS Process . . . . . . . . 4--5
R. H. Stern Micro Law: The Gnat Versus the Borg . . 6--8
Richard Mateosian Looking Forward . . . . . . . . . . . . 9
R. Rettberg and
W. J. Dally and
D. E. Culler Guest Editors' Introduction --- The
Bleeding Edge . . . . . . . . . . . . . 10--11
M. Horowitz and
C. K. K. Yang and
S. Sidiropoulos High-Speed Electrical Signaling ---
Overview and Limitations . . . . . . . . 12--24
J. Poulton and
W. J. Dally and
S. Tell A Tracking Clock Recovery Receiver for
4-Gbps Signaling . . . . . . . . . . . . 25--27
B. Y. Yu and
P. Toliver and
R. J. Runser and
K. L. Deng and
D. Y. Zhou and
I. Glesk and
P. R. Prucnal Packet-Switched Optical Networks . . . . 28--38
A. Charlesworth Starfire --- Extending the SMP Envelope 39--49
C. Dubnicki and
A. Bilas and
Y. Q. Chen and
S. N. Damianakis and
K. Li Shrimp Project Update --- Myrinet
Communication . . . . . . . . . . . . . 50--52
B. N. Chun and
A. M. Mainwaring and
D. E. Culler Virtual Network Transport Protocols for
Myrinet . . . . . . . . . . . . . . . . 53--63
S. R. Goldberg and
S. J. Upadhyaya Implementing Degradable Processing
Arrays . . . . . . . . . . . . . . . . . 64--74
S. Greenstein To Have and to Have Not . . . . . . . . 76--84
J. R. Hurt Cyrix Faces Slot-1 Challenge . . . . . . 88
Anonymous Micro News: 1-GHz Microprocessors . . . 2--2
Anonymous Micro News: Merced Update . . . . . . . 2--2
Anonymous Micro News: ECIX Adoption . . . . . . . 2--3
Anonymous News on Notebooks . . . . . . . . . . . 3--3
E. Scannell Windows-98 Debut . . . . . . . . . . . . 3--3
S. Greenstein Micro Economics: Closing the door on
foreclosure . . . . . . . . . . . . . . 4--5, 83--84
R. H. Stern Micro Law: Should signals be patented? 6--8
Richard Mateosian Micro Review: a vision for distributed
objects; interface design analysis . . . 9--10
Allen J. Baum and
Alan Jay Smith Guest Editors' Introduction: Hot
Chips---Hot Stuff . . . . . . . . . . . 11--13
Anonymous Call for Articles . . . . . . . . . . . 13
Kevin B. Normoyle and
Michael A. Csoppenszky and
Allan Tzeng and
Timothy P. Johnson and
Christopher D. Furman and
Jamshid Mostoufi UltraSPARC-IIi: Expanding the Boundaries
of a System on a Chip . . . . . . . . . 14--24
Fumio Arakawa and
Osamu Nishii and
Kunio Uchiyama and
Norio Nakagawa SH4 RISC Multimedia Microprocessor . . . 26--34
Kazumasa Suzuki and
Tomohisa Arai and
Kouhei Nadehara and
Ichiro Kuroda V830R/AV: An Embedded Multimedia
Superscalar RISC Processor . . . . . . . 36--47
Tim Litch and
Jeff Slaton StrongARMing Portable Communications . . 48--55
Anton Chernoff and
Mark Herdeg and
Ray Hookway and
Chris Reeve and
Norman Rubin and
Tony Tye and
S. Bharadwaj Yadavalli and
John Yates FX!32: a Profile-Directed Binary
Translator . . . . . . . . . . . . . . . 56--64
Dave Dunning and
Greg Regnier and
Gary McAlpine and
Don Cameron and
Bill Shubert and
Frank Berry and
Anne Marie Merritt and
Ed Gronke and
Chris Dodd The Virtual Interface Architecture . . . 66--76
Matt Welsh and
Anindya Basu and
Xun Wilson Huang and
Thorsten von Eicken Memory Management for User-Level Network
Interfaces . . . . . . . . . . . . . . . 77--82
Anonymous Author Guide . . . . . . . . . . . . . . 85
Anonymous Product Summary . . . . . . . . . . . . 87
L. Mar Letters: Microsoft supporter speaks out 2--3
R. H. Stern Micro Law: Microsoft Wins Readers'
Support --- The Author Responds . . . . 3--3
Richard Mateosian Micro Review: Year 2000, Windows 98;
Help! . . . . . . . . . . . . . . . . . 5--79
Richard H. Stern Micro Law: Inviting participants in
standard setting . . . . . . . . . . . . 6--7, 79
Eric R. Fossum Digital Camera System on a Chip . . . . 8--15
Gary S. Robinson Guest Editor's Introduction: Standards
and the Market . . . . . . . . . . . . . 16--17
Carl F. Cargill Standardization --- Art or Discipline 18--24
Stacy Leistner Avoiding Surprises --- Some Thoughts on
Standards . . . . . . . . . . . . . . . 25--32
Colm MacKernan Avoiding the Legal Mire . . . . . . . . 34--42
Shane Greenstein Micro Economics: Industrial Economics
and Strategy: Computing Platforms . . . 43--53
David V. James and
David B. Gustavson and
Balint Fleischer SerialExpress: a High-Performance
Workstation Interconnect . . . . . . . . 54--65
H. Peter Hofstee and
Sang H. Dhong and
David Meltzer and
Kevin J. Nowka and
Joel A. Silberman and
Jeffrey L. Burns and
Stephen D. Posluszny and
Osamu Takahashi Designing for a Gigahertz . . . . . . . 66--74
Anonymous Micro News: Did the PC Industry Get
Ahead of Itself? . . . . . . . . . . . . 75--75
Anonymous Micro News: Intergraph Wins Federal
Court Order . . . . . . . . . . . . . . 75--75
Anonymous Micro News: National Standards Strategy
Proposed . . . . . . . . . . . . . . . . 75--75
Anonymous Micro News: Programmable Digital Camera 75--75
Anonymous Cyrix Adds to CPU Line . . . . . . . . . 76--76
Anonymous Electron Behavior Investigated . . . . . 76--76
Anonymous The iMac . . . . . . . . . . . . . . . . 76--76
Anonymous Multithreaded System . . . . . . . . . . 76--76
Anonymous Mac OS-X . . . . . . . . . . . . . . . . 76--76
Anonymous It's Official . . . . . . . . . . . . . 76--76
Anonymous Is Packaging Everything? . . . . . . . . 76--76
Anonymous IBM's New PC Lineup . . . . . . . . . . 76--77
Anonymous EDA Industry Thrives . . . . . . . . . . 77--77
Anonymous High-Tech Entrepreneurs . . . . . . . . 77--77
Anonymous Online Technical Journal . . . . . . . . 77--77
Richard Mateosian Robohelp-5.5 . . . . . . . . . . . . . . 78--79
Anonymous New Products: Design tools, portables,
and DSPs . . . . . . . . . . . . . . . . 81
Anonymous Editorial Calendar . . . . . . . . . . . 84
Anonymous Product Summary . . . . . . . . . . . . 85
J. L. Ferrero Micro View: History of Computing on
Display . . . . . . . . . . . . . . . . 88
Gary S. Robinson Micro Standards: Starting an
International Standard . . . . . . . . . 2--3
Richard H. Stern Micro Law: Restraints on Technology
Advances . . . . . . . . . . . . . . . . 4--6, 78--81
Gerhard Tröster Guest Editor's Introduction: New Route
in System Integration: Chip-Package
Codesign . . . . . . . . . . . . . . . . 7--9
Happy Holden Microvias: The Next Generation of
Substrates and Packages . . . . . . . . 10--16
Mitsumasa Koyanagi and
Hiroyuki Kurino and
Katsuyuki Sakuma and
Kang Wook Lee and
Nobuaki Miyakawa and
Hikotaro Itani Future System-on-Silicon LSI Chips . . . 17--22
Jenshan Lin Chip-Package Codesign for High-Frequency
Circuits and Systems . . . . . . . . . . 24--32
Evan E. Davidson Large Chip vs. MCM for a
High-Performance System . . . . . . . . 33--41
Etienne Hirt and
Michael Scheffler and
Jean-Pierre P. Wyss Area I/O's Potential for Future
Processor Systems . . . . . . . . . . . 42--49
Andreas C. Cangellaris Electrical Modeling and Simulation
Challenges in Chip-Package Codesign . . 50--59
Bruce Jacob and
Trevor Mudge Virtual Memory in Contemporary
Microprocessors . . . . . . . . . . . . 60--75
Shane Greenstein Micro Economics: Uncertainty,
Prediction, and the Unexpected . . . . . 76--77
Anonymous News: Carbon Computers Possible? . . . . 82--82
Anonymous News: Intel's New Pentium-II Processor 82--82
Anonymous News: New Packaging from Siemens . . . . 82--82
Anonymous News: Single-Unit RF Power Delivery . . 82--82
Anonymous Los Alamos Engineers Develop Solvent . . 83--83
Anonymous Collaboration for Imec and Ericsson . . 83--83
Anonymous Joint Project Certificate Program . . . 83--83
Anonymous Microlasers . . . . . . . . . . . . . . 83--83
Anonymous Options for Mac Designers . . . . . . . 83--83
Anonymous Systems on a Chip . . . . . . . . . . . 83--83
Anonymous New Products: Design services,
portables, SBCs, software, memories . . 84
Anonymous Product Summary . . . . . . . . . . . . 86
Jim Isaak and
Lowell Johnson Micro View: POSIX/UNIX Standards ---
Foundation for 21st-Century Growth . . . 88
Richard Mateosian Micro Review: Working on the Web . . . . 2--3
S. Greenstein Micro Economics: Return of the Jaded:
What would a Hollywood film about the PC
industry look like? . . . . . . . . . . 4--5
G. S. Robinson Micro Standards: Standards give you
control . . . . . . . . . . . . . . . . 6--6
R. H. Stern Micro Law: Y2K product liability . . . . 7--7
Dimiter R. Avresky and
Karl E. Grosspietsch and
Barry W. Johnson and
Fabrizio Lombardi Guest Editors' Introduction: Embedded
Fault-Tolerant Systems . . . . . . . . . 8--11
Edna Barros and
Marcus V. D. dos Santos A Safe, Accurate Intravenous Infusion
Control System . . . . . . . . . . . . . 12--21
Volker Strumpen Portable and Fault-Tolerant Software
Systems . . . . . . . . . . . . . . . . 22--32
Matthias Pflanz and
Heinrich Theodor Vierhaus Generating Reliable Embedded Processors 33--41
Giorgos Efthivoulidis and
Evangelos A. Verentziotis and
Apostolos N. Meliones and
Theodora A. Varvarigou and
Antonios Kontizas and
Geert Deconinck and
Vincenzo De Florio Fault-Tolerant Communication in Embedded
Supercomputing . . . . . . . . . . . . . 42--52
Adel Cherif and
Takuya Katayama Replica Management for Fault-Tolerant
Systems . . . . . . . . . . . . . . . . 54--65
Reinhard von Hanxleden and
Ali Botorabi and
Slawomir Kupczyk A Codesign Approach for Safety-Critical
Automotive Applications . . . . . . . . 66--79
Anonymous Product Summary . . . . . . . . . . . . 86
J. L. Ferrero Micro View: Wearable computing: One
man's mission . . . . . . . . . . . . . 88--88
Anonymous Call for Articles . . . . . . . . . . . 2
S. L. Diamond Editor-in-Chief's Message: Life recycles 3--3
Anonymous New Products: Design tools; portables,
online tools . . . . . . . . . . . . . . 4
S. Greenstein Micro Economics: Commercializing the
Internet . . . . . . . . . . . . . . . . 6--7
G. S. Robinson Micro Standards: Exploiting the acronym
craze . . . . . . . . . . . . . . . . . 8--8
Anonymous Micro Review: Metaclasses; intellectual
property; understanding the new media;
Adobe Photoshop 5 . . . . . . . . . . . 9
H. S.-Philip P. Wong and
Albert J. P. Theuwissen Guest Editors' Introduction: Digital
Imaging . . . . . . . . . . . . . . . . 12--13
Shoji Kawamura Capturing Images with Digital Still
Cameras . . . . . . . . . . . . . . . . 14--19
Jim Adams and
Ken Parulski and
Kevin Spaulding Color Processing in Digital Cameras . . 20--30
Minerva M. Yeung and
Boon-Lock L. Yeo and
Matthew Holliman Digital Watermarks --- Shedding Light on
the Invisible . . . . . . . . . . . . . 32--41
Paul M. Alt Displays for Electronic Imaging . . . . 42--53
Jacob R. Lorch and
Alan Jay Smith Apple Macintosh's Energy Consumption . . 54--63
Yiming M. Hu and
Qing Yang A New Hierarchical Disk Architecture . . 64--76
Anonymous 1998 Annual Index --- Complete Author
and Subject Listings . . . . . . . . . . 77
Anonymous Author Guide: Details for submissions to
IEEE Micro . . . . . . . . . . . . . . . 85
Anonymous Product Summary . . . . . . . . . . . . 88--88
Ken Sakamura Editor-in-Chief Message: Welcoming the
21st century . . . . . . . . . . . . . . 2--3
Richard Mateosian Micro Review: Happy New Year: MacWorld
Expo; Handbook of Programming Languages 4--5
Richard H. Stern Micro Law: When elephants dance, mice
watch out! . . . . . . . . . . . . . . . 6--7, 82
Shane Greenstein Micro Economics: When technologies
converge . . . . . . . . . . . . . . . . 8--9
Anonymous Micro News: Microelectronics Research in
Europe . . . . . . . . . . . . . . . . . 10--10
Anonymous Micro News: NIST Project Competition . . 10--10
Anonymous Micro News: Photobit Secures Broad
Camera-on-a-Chip Patent . . . . . . . . 10--10
Anonymous Micro News: Creating Virtual Sculpture 10--11
Anonymous Micro News: System-on-a-chip design . . 10--11
Nick McKeown and
Chase Bailey Guest Editors' Introduction: The
Increasingly Important Interconnect . . 12--13
Kenichi Ishibashi and
Tsutomu Goto and
Takehisa Hayashi and
Tetsuhiko Okada and
Akira Yamagiwa and
Masabumi Shibata and
Kazuhiro Akimoto and
Naoki Hamanaka and
Toshiro Takahashi and
Akio Koyama and
Tatsuhiro Aida Simultaneous Bidirectional Transceiver
Logic . . . . . . . . . . . . . . . . . 14--19
Pankaj Gupta and
Nick McKeown Designing and Implementing a Fast
Crossbar Scheduler . . . . . . . . . . . 20--28
Anonymous Call for Articles . . . . . . . . . . . 29--29
Georgios Kornaros and
Dionisios Pnevmatikatos and
Panagiota Vatsolaki and
Georgios Kalokerinos and
Chara Xanthaki and
Dimitrios Mavroidis and
Dimitrios Serpanos and
Manolis Katevenis ATLAS I: Implementing a Single-Chip ATM
Switch with Backpressure . . . . . . . . 30--41
Steven R. Kleiman and
Scott Schoenthal and
Alan Rowe and
Steven H. Rodrigues and
Arputham Benjamin Using NUMA Interconnects for Highly
Available Filers . . . . . . . . . . . . 42--49
Stefan Savage and
Thomas Anderson and
Amit Aggarwal and
David Becker and
Neal Cardwell and
Andy Collins and
Eric Hoffman and
John Snell and
Amin Vahdat and
Geoff Voelker and
John Zahorjan Detour --- Informed Internet Routing and
Transport . . . . . . . . . . . . . . . 50--59
Karen Panetta Lentz and
Jamie Heller and
Pier Luca Montessoro System Verification Using Multilevel
Concurrent Simulation . . . . . . . . . 60--67
Alessandro Gabrielli and
Enzo Gandolfi A Fast Digital Fuzzy Processor . . . . . 68--79
Gary S. Robinson Micro Standards: The little committee
that grew . . . . . . . . . . . . . . . 80--81
Anonymous New Products: Development tools;
security solutions; multimedia . . . . . 84--85
Anonymous Product Summary . . . . . . . . . . . . 86--87
Anonymous Editorial Calendar . . . . . . . . . . . 88--88
Ken Sakamura Editor-in-Chief Message: Selecting a
processor's architecture must be based
on more than its technical impact . . . 2--2
Gary S. Robinson Micro Standards: IEEE Registration
Authority Committee . . . . . . . . . . 3--4
Richard Mateosian Micro Review: Words of wisdom . . . . . 5, 85
Richard H. Stern Micro Law: Web concerns . . . . . . . . 6--7
Shane Greenstein Micro Economics: Bill, adopt a mensch
strategy! . . . . . . . . . . . . . . . 8, 83--84
Anonymous Micro News: The Provocative ISSCC99;
Pentium III and ``Intel Inside'';
Semiconductor IP service; Open
industry-standard language; a virtual
reading room; IEEE 1394 IC protects
digital content . . . . . . . . . . . . 9, 82
S. Savage Corrigendum: ``Detour: Informed Internet
Routing and Transport'' (vol. 19, p. 55,
1999) . . . . . . . . . . . . . . . . . 9--9
Anonymous Pentium-III and Intel Inside . . . . . . 9, 82
Norman P. Jouppi and
John Wawrzynek Guest Editors' Introduction: Real
Products, Real Technology . . . . . . . 10--11
Timothy J. Slegel and
Robert M. Averill III and
Mark A. Check and
Bruce C. Giamei and
Barry W. Krumm and
Christopher A. Krygowski and
Wen H. Li and
John S. Liptay and
John D. MacDougall and
Thomas J. McPherson and
Jennifer A. Navarro and
Eric M. Schwarz and
Kevin Shum and
Charles F. Webb IBM's S/390 G5 Microprocessor Design . . 12--23
R. E. Kessler The Alpha-21264 Microprocessor . . . . . 24--36
Stuart Oberman and
Greg Favor and
Fred Weber AMD 3DNow! Technology: Architecture and
Implementations . . . . . . . . . . . . 37--48
Thomas C. Savell The EMU10K1 Digital Audio Processor . . 49--57
Joel McCormack and
Robert McNamara and
Christopher Gianos and
Norman P. Jouppi and
Todd Dutton and
John Zurawski and
Larry Seiler and
Ken Correll Implementing Neon: a 256-Bit Graphics
Accelerator . . . . . . . . . . . . . . 58--69
Feng-hsiung H. Hsu IBM's Deep Blue Chess Grandmaster Chips 70--81
Anonymous Product Summary . . . . . . . . . . . . 87--87
Ken Sakamura Editor-in-Chief's Message: Relying on
market forces . . . . . . . . . . . . . 2--2
Anonymous Micro Review: Bringing up the rear . . . 3--4
G. S. Robinson Micro Standards: Healthcare Needs
Standards . . . . . . . . . . . . . . . 5--5
S. Greenstein Micro Economics: Forecasting Commercial
Change . . . . . . . . . . . . . . . . . 6--7
Pradip Bose and
Thomas M. Conte and
Todd M. Austin Guest Editors' Introduction: Challenges
in Processor Modeling and Validation . . 9--14
Mayan Moudgill and
John-David D. Wellman and
Jaime H. Moreno Environment for PowerPC
Microarchitecture Exploration . . . . . 15--25
Candice Bechem and
Jonathan Combs and
Noppanunt Utamaphethai and
Bryan Black and
R. D. Shawn Blanton and
John Paul Shen An Integrated Functional Performance
Simulator . . . . . . . . . . . . . . . 26--35
Arvind and
Xiaowei W. Shen Using Term Rewriting Systems to Design
and Verify Processors . . . . . . . . . 36--46
Warren A. Hunt, Jr. and
Jun Sawada Verifying the FM9801 Microarchitecture 47--55
Steven Kunkel and
Bill Armstrong and
Philip Vitale System Optimization for OLTP Workloads 56--65
Sudheendra Hangal and
Mike O'Connor Performance Analysis and Validation of
the picoJava Processor . . . . . . . . . 66--72
Anonymous Call for Articles . . . . . . . . . . . 72--72
Tim Horel and
Gary Lauterbach UltraSPARC-III: Designing
Third-Generation 64-Bit Performance . . 73--85
Ken Sakamura Editor-in-Chief's Message: Designing
low-power CPUs . . . . . . . . . . . . . 2--2
Gary S. Robinson Micro Standards: When is two too many? 3--3
Richard Mateosian Micro Review: Creating documents . . . . 4, 85
Shane Greenstein Micro Economics: Building the Virtual
World . . . . . . . . . . . . . . . . . 5--6, 86
Richard H. Stern Micro Law: Licensing IP embodied in
standards . . . . . . . . . . . . . . . 7--8, 82--83
Tadao Nakamura Guest Editor's Introduction: Introducing
Cool Chips . . . . . . . . . . . . . . . 9--10
Michael J. Flynn and
Patrick Hung and
Kevin W. Rudd Deep-Submicron Microprocessor Design
Issues . . . . . . . . . . . . . . . . . 11--22
Shekhar Borkar Design Challenges of Technology Scaling 23--29
David Ruimy Gonzales Micro-RISC Architecture for the Wireless
Market . . . . . . . . . . . . . . . . . 30--37
Hidehiro Takata and
Tetsuya Watanabe and
Tetsuo Nakajima and
Takashi Takagaki and
Hisakazu Sato and
Atsushi Mohri and
Akira Yamada and
Toshiki Kanamoto and
Yoshio Matsuda and
Shuhei Iwade and
Yasutaka Horiba The D30V/MPEG Multimedia Processor . . . 38--47
Jack Choquette and
Mayank Gupta and
Dominic McCarthy and
Jack Veenstra High-Performance RISC Microprocessors 48--55
Mitsuo Ikeda and
Toshio Kondo and
Koyo Nitta and
Kazuhito Suguri and
Takeshi Yoshitome and
Toshihiro Minami and
Hiroe Iwasaki and
Katsuyuki Ochiai and
Jiro Naganuma and
Makoto Endo and
Yutaka Tashiro and
Hiroshi Watanabe and
Naoki Kobayashi and
Tsuneo Okubo and
Takeshi Ogura and
Ryota Kasai SuperEnc: MPEG-2 Video Encoder Chip . . 56--65
Jean Arlat and
Jérome Boué and
Yves Crouzet Validation-Based Development of
Dependable Systems . . . . . . . . . . . 66--79
Anonymous Micro News: Mobile computing without
PCs/laptops; Intel delays Coppermine;
Internet backbone support/privacy laws 80--80
Anonymous Micro News: FTC Holds Off on Internet
Privacy Laws . . . . . . . . . . . . . . 80--81
Anonymous Micro News: Internet Backbone
Support/Privacy Laws . . . . . . . . . . 80--80
Anonymous Broad-Band Deployment Act . . . . . . . 81--81
Anonymous Micro News: Intel delays Coppermine . . 81--81
Anonymous Managing SANs . . . . . . . . . . . . . 81--81
Anonymous Single-Sourcing Webworks Publisher-2000
for Windows . . . . . . . . . . . . . . 85--85
Anonymous Product Summary . . . . . . . . . . . . 87--88
Ken Sakamura Editor-in-Chief's Message: Advancing
microelectronics technology . . . . . . 2--2
Gary S. Robinson Micro Standards: Skiing and standards
don't mix! . . . . . . . . . . . . . . . 3--4
Shane Greenstein Micro Economics: Banking on the
Information Age . . . . . . . . . . . . 5--6
Richard H. Stern Micro Law: Licensing IP embodied in
standards, Part 2: ANSI Position; The
Web Standards Project Position . . . . . 7--9, 81--83
W. K. Edwards Core Jini . . . . . . . . . . . . . . . 10--11
Richard Mateosian Micro Review: Pot Pourri: Jini . . . . . 10--11
D. Flanagan Micro Review: Java Power Reference . . . 10--11
Anonymous Micro Review: Adobe Acrobat 4 . . . . . 11--11
Richard Mateosian Micro Review: Pot Pourri: Winwriters . . 11--11
Dieter Gotz and
Anton Sauer Guest Editors' Introduction: MEDEA: a
Successful European Cooperation in
Microelectronics . . . . . . . . . . . . 12--15
Michel Haond and
Marie-Thér\`ese Basso and
Walter deCoster and
Eric Gerritsen and
Jos Guelen and
Christophe Lair Developing a 0.18-Micron CMOS Process 16--22
Edgard Laes and
Livio Baldi and
Claus Dahl and
Frits R. J. Huisman and
Ludo Deferm CMOS Options for Single-Chip
Applications . . . . . . . . . . . . . . 23--32
Albert Hasper and
Ed Oosterlaken and
Frank Huussen and
Tanja Claasen-Vujcic Advanced Manufacturing Equipment: a
Vertical Batch Furnace for 300-mm Wafer
Processing . . . . . . . . . . . . . . . 34--43
Teus Hazendonk and
Giuseppe Coppola Preparing for Multimedia Terminals . . . 44--51
Jean-Pierre P. Tual MASSC: a Generic Architecture for
Multiapplication Smart Cards . . . . . . 52--61
Modeste Addra and
Dominique Castel and
Jacques Dulongpont and
Pierre Genest Microelectronics in Mobile
Communications: a Key Enabler . . . . . 62--70
Joseph Borel Design Automation in MEDEA: Present and
Future . . . . . . . . . . . . . . . . . 71--79
Anonymous New Products . . . . . . . . . . . . . . 84--86
Anonymous Product Summary . . . . . . . . . . . . 87--87
Anonymous Micro News: AMD Announces New Athlon . . 2--2
Anonymous Micro News: Intel Unveils Itanium
Processor . . . . . . . . . . . . . . . 2--2
Anonymous Micro News: One-Millionth Copper Chip
Shipped . . . . . . . . . . . . . . . . 2--2
Anonymous Micro News: NAE prize awarded [to John
MacChesney, Charles Kao, and Robert
Maurer] . . . . . . . . . . . . . . . . 2--3
Anonymous Micro News: Electronic Paper Resurfaces 3--3
Anonymous Micro News: Hyundai Merges with LG
Semicon . . . . . . . . . . . . . . . . 3--3
Anonymous Micro News: R&D projects awarded . . . . 3--3
Gary S. Robinson Micro Standards: a different look at
standards . . . . . . . . . . . . . . . 4--5
Shane Greenstein Micro Economics: Virulent word of mouse 6--8
Alex (Sandy) Pentland Wearable Computing NEW!: Wearable
computers . . . . . . . . . . . . . . . 9--11
Richard H. Stern Micro Law: When compliance with a
standard gets too expensive . . . . . . 12--14, 86
Ken Sakamura Guest Editor's Introduction:
Entertainment and Edutainment . . . . . 15--19
Masaaki Oka and
Masakazu Suzuoki Designing and Programming the Emotion
Engine . . . . . . . . . . . . . . . . . 20--28
Shiro Hagiwara and
Ian Oliver Sega Dreamcast: Creating a Unified
Entertainment World . . . . . . . . . . 29--35
Ichiya Nakamura and
Hideki Mori Play and Learning in the Digital Future 36--42
Davin S. L. Ing Innovations in a Technology Museum . . . 44--52
Xiao-Tao T. Chen and
Wenyi Y. Feng and
Jun Zhao and
Fred J. Meyer and
Fabrizio Lombardi Reconfiguring One-Time Programmable
FPGAs . . . . . . . . . . . . . . . . . 53--63
Johannes Kneip and
Bernd Schmale and
Henning Möller Applying and Implementing the MPEG-4
Multimedia Standard . . . . . . . . . . 64--74
Anonymous IEEE Micro 1999 Annual Index . . . . . . 75--83
Richard Mateosian Micro Review: Changes: Extreme
Programming Explained; The Cathedral and
The Bazaar . . . . . . . . . . . . . . . 84--85
Stephen L. Diamond Micro View: Putting Children First: the
Lego MindStorms product . . . . . . . . 88, 87
Ken Sakamura Editor-in-Chief's Message: Performance
in the new millennium . . . . . . . . . 2--2
Anonymous Untitled --- Reply . . . . . . . . . . . 3--3
Hubert Kirrmann and
Ken Sakamura Letters: date formats . . . . . . . . . 3--3
Anonymous Micro News: Motorola expands IP and SOC
efforts; Market benefits again;
Customized VLIW cores proposed; Building
the world's fastest supercomputer;
Advancing wireless use . . . . . . . . . 4--5
Gary S. Robinson Micro Standards: Standards intellectual
property licensing . . . . . . . . . . . 6--8
Richard H. Stern Micro Law: IP-related refusals to deal:
Part 1: Updating the Intel-Intergraph
controversy . . . . . . . . . . . . . . 9--12
Shane Greenstein Micro Economics: Aggressive business
tactics: are there limits? . . . . . . . 13--14
Anujan Varma and
Mark Laubach Guest Editors' Introduction: Solving
Interconnection Problems . . . . . . . . 15--17
Charles D. Cranor and
R. Gopalakrishnan and
Peter Z. Onufryk Architectural Considerations for CPU and
Network Interface Integration . . . . . 18--26
Tzi-cker C. Chiueh and
Prashant Pradhan Cache Memory Design for Internet
Processors . . . . . . . . . . . . . . . 28--33
Pankaj Gupta and
Nick McKeown Classifying Packets with Hierarchical
Intelligent Cuttings . . . . . . . . . . 34--41
L. Louis Zhang and
Brent Beacham and
Massoud Reza Hashemi and
Paul Chow and
Alberto Leon-Garcia A Scheduler ASIC for a Programmable
Packet Switch . . . . . . . . . . . . . 42--48
Benjamin C. Reed and
Edward G. Chron and
Randal C. Burns and
Darrell D. E. Long Authenticating Network-Attached Storage 49--57
Dan Steinberg and
Yitzhak Birk An Empirical Analysis of the IEEE-1394
Serial Bus Protocol . . . . . . . . . . 58--65
Jose Fridman and
Zvi Greenfield The TigerSHARC DSP Architecture . . . . 66--76
Richard Mateosian Micro Review: Happy New Year . . . . . . 77--78
Stephen L. Diamond Micro View: Microdisplay applications
reach the mainstream . . . . . . . . . . 80, 79
Ken Sakamura Editor-in-Chief's message: New
Applications and demands . . . . . . . . 2--2
Gary S. Robinson Micro Standards: The good, the bad, and
the ugly . . . . . . . . . . . . . . . . 3--4
Behrooz Parhami Letters: Reinventing the mousetrap . . . 4--4
Shane Greenstein Micro Economics: a Revolution? How do
you know? . . . . . . . . . . . . . . . 5--7
Richard H. Stern Micro Law: IP-related refusals to deal:
Part 2: Pretext and misconduct as
standards . . . . . . . . . . . . . . . 8--11, 96
Richard Mateosian Micro Review: Windows 2000 . . . . . . . 12--13, 96
Monica Lam and
Forest Baskett Guest Editors' Introduction:
Cutting-Edge Designs . . . . . . . . . . 14--15
Henry Samueli The Broadband Revolution . . . . . . . . 16--26
Edward H. Frank and
Jack Holloway Connecting the Home With a Phone Line
Network Chip Set . . . . . . . . . . . . 27--37, 39
Atsushi Kunimatsu and
Nobuhiro Ide and
Toshinori Sato and
Yukio Endo and
Hiroaki Murakami and
Takayuki Kamei and
Masashi Hirano and
Fujio Ishihara and
Haruyuki Tago and
Masaaki Oka and
Akio Ohba and
Teiji Yutaka and
Toyoshi Okada and
Masakazu Suzuoki Vector Unit Architecture for Emotion
Synthesis . . . . . . . . . . . . . . . 40--47
Anonymous Call for papers . . . . . . . . . . . . 47--47
Chris Basoglu and
Woobin Lee and
John Setel O'Donnell The Map1000A VLIW Mediaprocessor . . . . 48--59
Ricardo E. Gonzalez Xtensa --- a Configurable and Extensible
Processor . . . . . . . . . . . . . . . 60--70
Anonymous IEEE Micro Editorial Calendar . . . . . 70--70
Lance Hammond and
Benedict A. Hubbert and
Michael Siu and
Manohar K. Prabhu and
Michael Chen and
Kunle Olukotun The Stanford Hydra CMP . . . . . . . . . 71--84
Keith Diefendorff and
Pradeep K. Dubey and
Ron Hochsprung and
Hunter Scales AltiVec Extension to PowerPC Accelerates
Media Processing . . . . . . . . . . . . 85--95
Ken Sakamura Editor-in-Chief's Message: Developing
new computer architectures . . . . . . . 2--2
Marie English Micro News: New benchmark for
Unigraphics V15; Wireless applications
grow; Tool set for the Java Card
platform; Biomechanical discovery
affects mobile applications, robots;
Hard to navigate Web . . . . . . . . . . 3--3, 86--87
Marie English Micro News: Chip Technology Breakthrough 3--3, 86--87
Marie English Micro News: Embedded Linux Consortium
Begun . . . . . . . . . . . . . . . . . 3--3
Marie English Micro News: Increased Fab Activity in
2000 . . . . . . . . . . . . . . . . . . 3--3
Marie English Micro News: Intel Releases Itanium Guide 3--3
Marie English Micro News: Single-Chip Device for
Set-Top Boxes . . . . . . . . . . . . . 3--3
Richard Mateosian Micro Review: Doing it right! . . . . . 4--5
Richard H. Stern Micro Law: IP-related refusals to deal:
Part $ 2 1 / 2 $: a postscript . . . . . 6--7
Shane Greenstein Micro Economics: The era of impatience 8--9
Alan Clements Guest Editor's Introduction: Computer
Architecture Education . . . . . . . . . 10--12
Alan Clements The Undergraduate Curriculum in Computer
Architecture . . . . . . . . . . . . . . 13--22
Daniel C. Hyde Teaching Design in a Computer
Architecture Course . . . . . . . . . . 23--28
James O. Hamblen Rapid Prototyping Using
Field-Programmable Logic Devices . . . . 29--37
Nirav H. Kapadia and
Renato J. Figueiredo and
José A. B. Fortes Punch --- Web Portal for Running Tools 38--47
Augustus K. Uht and
Jien-Chung Lo and
Ying Sun and
James C. Daly and
James Kowalski Building Real Computer Systems . . . . . 48--56
Roland N. Ibbett HASE DLX Simulation Model . . . . . . . 57--65
Jovan Djordjevic and
Aleksandar Milenkovic and
Nenad Grbanovic An Integrated Environment for Teaching
Computer Architecture . . . . . . . . . 66--74
Arvind and
Anton T. Dahbura and
Alejandro Caro From Monsoon to StarT-Voyager:
University-Industry Collaboration in
Research . . . . . . . . . . . . . . . . 75--84
Gary S. Robinson Micro Standards: Join a standards group
and see the world . . . . . . . . . . . 85--86
Anonymous New Benchmark for Unigraphics V15 . . . 86--86
Anonymous Wireless Applications Grow . . . . . . . 86--86
Anonymous Biomechanical Discovery Affects Mobile
Applications, Robots . . . . . . . . . . 87--87
Anonymous Hard to Navigate Web . . . . . . . . . . 87--87
Anonymous Tool Set for the Java Card Platform . . 87--87
Anonymous Product Summary . . . . . . . . . . . . 88--88
Marie English Micro News: Advancing Silk Technology 2--2
Marie English Micro News: Chip Production . . . . . . 2--2
Marie English Micro News: Microcode Development
Services . . . . . . . . . . . . . . . . 2--2
Marie English Micro News: Partnerships Continue to Aid
Industry . . . . . . . . . . . . . . . . 2--2
Marie English Micro News: SIA Forecasts Growth . . . . 2--2
Anonymous Micro Bits . . . . . . . . . . . . . . . 3--3
Marie English Micro News: Doubling Computer Memory . . 3--3
Marie English Micro News: Smaller, Faster, Cheaper
Chips . . . . . . . . . . . . . . . . . 3--4
Marie English Micro News: Digital-Signature
Legislation . . . . . . . . . . . . . . 4--4
Marie English Micro News: Have you heard the story
about bent nanowires? . . . . . . . . . 4--4
Shane Greenstein Micro Economics: Hung up on AT&T? . . . . 5--6
Richard Mateosian Micro Review: Summer cleanup . . . . . . 7--9, 85
Ken Sakamura EIC Message: 21st-century
microprocessors . . . . . . . . . . . . 10--11
Masato Edahiro and
Satoshi Matsushita and
Masakazu Yamashina and
Naoki Nishi A Single-Chip Multiprocessor for Smart
Terminals . . . . . . . . . . . . . . . 12--20
Atsuhiro Suga and
Kunihiko Matsunami Introducing the FR500 Embedded
Microprocessor . . . . . . . . . . . . . 21--27
Prasenjit Biswas and
Atsushi Hasegawa and
Srinivas Mandaville and
Mark Debbage and
Andy Sturges and
Fumio Arakawa and
Yasuhiko Saito and
Kunio Uchiyama SH-5 --- The 64-Bit SuperH Architecture 28--39
Shigeo Araki The Memory Stick . . . . . . . . . . . . 40--46
Srinivas K. Raman and
Vladimir Pentkovski and
Jagannath Keshava Implementing Streaming SIMD Extensions
on the Pentium III Processor . . . . . . 47--57
Jesús Sánchez and
Antonio González Analyzing Data Locality in Numeric
Applications . . . . . . . . . . . . . . 58--66
Michael J. Flynn and
Patrick Hung and
Armita Peymandoust Using Simple Tools to Evaluate Complex
Architectural Trade-offs . . . . . . . . 67--75
Silke Draber Optimizing Fault Tolerance in Embedded
Distributed Systems . . . . . . . . . . 76--87
Nick Tredennick and
Steven J. Wallach Micro View: Predicting the future . . . 88, 87
Ken Sakamura EIC Message: Connecting will be
commonplace . . . . . . . . . . . . . . 2--2
Marie English Micro News: IrDA and Bluetooth: down
with cords!; Targeting low-$k$; Help for
designers; IBM demos quantum computer;
GPS compatible with UWB?; Chip benefits
fiber optics; IEEE President's awards;
Price comparison for PDAs; IETF explores
standards . . . . . . . . . . . . . . . 3--4, 85--86
Richard Mateosian Micro Review: Interaction design . . . . 5--6
Shane Greenstein Micro Economics: Falling through the
cracks at Microsoft . . . . . . . . . . 7--7, 87--87
John H. Crawford Guest Editor's Introduction: Introducing
the Itanium Processors . . . . . . . . . 9--11
Jerry Huck and
Dale Morris and
Jonathan Ross and
Allan Knies and
Hans Mulder and
Rumi Zahir Introducing the IA-64 Architecture . . . 12--23
Harsh Sharangpani and
Ken Arora Itanium Processor Microarchitecture . . 24--43
Jay Bharadwaj and
William Y. Chen and
Weihaw Chuang and
Gerolf Hoflehner and
Kishore Menezes and
Kalyan Muthukumar and
Jim Pierce The Intel IA-64 Compiler Code Generator 44--53
Fumio Aono and
Masayuki Kimura The AzusA 16-Way Itanium Server . . . . 54--60
Nhon Quach High-Availability and Reliability in the
Itanium Processor . . . . . . . . . . . 61--69
Dezsö Sima The Design Space of Register Renaming
Techniques . . . . . . . . . . . . . . . 70--83
Gary S. Robinson Micro Standards: Formal SDOs: They're
still alive! . . . . . . . . . . . . . . 84--84
Anonymous Product Summary . . . . . . . . . . . . 88--88
Anonymous News: Hot Interconnects, Hot Chips,
InfiniBand standard, semiconductor
milestones . . . . . . . . . . . . . . . 2--3
Richard H. Stern Micro Law: Napster: a walking copyright
infringement? . . . . . . . . . . . . . 4--5, 95
Shane Greenstein Micro Economics: PCs, the Internet, and
you . . . . . . . . . . . . . . . . . . 6--7
Gary S. Robinson Micro Standards: Making standards simple 8--9
Ken Sakamura Guest Editor's Introduction: Stepping
Into the Future . . . . . . . . . . . . 10--11
Marc Tremblay and
Jeffrey Chan and
Shailender Chaudhry and
Andrew W. Conigliaro and
Shing Sheung Tse The MAJC Architecture: a Synthesis of
Parallelism and Scalability . . . . . . 12--25
David M. Brooks and
Pradip Bose and
Stanley E. Schuster and
Hans Jacobson and
Prabhakar N. Kudva and
Alper Buyuktosuno\uglu and
John-David Wellman and
Victor Zyuban and
Manish Gupta and
Peter W. Cook Power-Aware Microarchitecture: Design
and Modeling Challenges for
Next-Generation Microprocessors . . . . 26--44
Chris Herring Microprocessors, Microcontrollers, and
Systems in the New Millennium . . . . . 45--51
Gene Frantz Digital Signal Processor Trends . . . . 52--59
Rakesh Krishnaiyer and
Dattatraya Kulkarni and
Daniel Lavery and
Wei Li and
Chu-cheow Lim and
John Ng and
David Sehr An Advanced Optimizer for the IA-64
Architecture . . . . . . . . . . . . . . 60--68
Eric Dahlen and
Jennifer Gustin and
Susan Meredith and
Doug Moran The 82460GX Server/Workstation Chip Set 69--75
Humayn Khalid Validating Trace-Driven
Microarchitectural Simulations . . . . . 76--82
Tadao Nakamura Cool Chips III . . . . . . . . . . . . . 83--84
Anonymous Annual Index --- Volume 20 Author and
Subject listings . . . . . . . . . . . . 85--95
Anonymous Product Summary . . . . . . . . . . . . 96--96
Ken Sakamura EIC Message: Beginnings and endings . . 4--5
Anonymous Micro News: William Hewlett dies; IBM
introduces MRAM; embedded microprocessor
benchmark . . . . . . . . . . . . . . . 6--7
Richard H. Stern Micro Law: Who invented hyperlinks? . . 8--10
Shane Greenstein Micro Economics: How does the new
economy stack up? . . . . . . . . . . . 11--12
Gary S. Robinson Micro Standards: Working in informal
groups . . . . . . . . . . . . . . . . . 13--13, 92
James Yee and
Manu Thapar Guest Editors' Introduction: Red Hot
Chili Papers . . . . . . . . . . . . . . 14--15
Girish Welling and
Maximilian Ott and
Saurabh Mathur A Cluster-Based Active Router
Architecture . . . . . . . . . . . . . . 16--25
Li-Shiuan Peh and
William J. Dally A Delay Model for Router
Microarchitectures . . . . . . . . . . . 26--34
Devavrat Shah and
Pankaj Gupta Fast Updating Algorithms for TCAMs . . . 36--47
Konstantinos Psounis and
Rong Pan and
Balaji Prabhakar Approximate Fair Dropping for
Variable-Length Packets . . . . . . . . 48--56
Kenneth Y. Yun A Terabit Multiservice Switch . . . . . 58--70
Ejaz Haq and
Jim Slager and
John Pecoraro and
John D. Johnson and
Mark Santoro and
Lee Tavrow and
Scott Wakefield and
David Weisner JAZiO Signal-Switching Technology: a
Low-Cost Digital I/O for High-Speed
Applications . . . . . . . . . . . . . . 72--81
William A. Samaras and
Naveen Cherukuri and
Srinivas Venkataraman The IA-64 Itanium Processor Cartridge 82--89
Richard Mateosian Micro Review: Confronting the context of
technology's advances . . . . . . . . . 90--92
Anonymous Product Summary . . . . . . . . . . . . 94--95
Ken Sakamura EIC Message: a new challenge . . . . . . 2--2
Gary S. Robinson Micro Standards: International
standards: Why do them? . . . . . . . . 4, 96
Shane Greenstein Micro Economics: Pricing Internet access 5--6
Richard H. Stern Micro Law: Amazon's one-click patent
loses its teeth . . . . . . . . . . . . 7--10
Anonymous Micro News: Next-generation lithography;
new research at IBM; clockless
computing; Micro Bits . . . . . . . . . 11, 196
William J. Dally and
Marc Tremblay and
Allen J. Baum Guest Editors' Introduction: Hot Chips
12 . . . . . . . . . . . . . . . . . . . 13--15
Mike O'Connor and
Christopher A. Gomez The iFlow Address Processor . . . . . . 16--23
Matthias Steffen and
Lieven M. K. Vandersypen and
Isaac L. Chuang Toward Quantum Computation: a Five-Qubit
Quantum Processor . . . . . . . . . . . 24--34
Brucek Khailany and
William J. Dally and
Ujval J. Kapasi and
Peter Mattson and
Jinyung Namkoong and
John D. Owens and
Brian Towles and
Andrew Chang and
Scott Rixner Imagine: Media Processing with Streams 35--46
Ion E. Opris and
Seiichiro Watanabe A Fast Analog Front-End Processor for
Digital Imaging Systems . . . . . . . . 48--54
R. Brett Tremaine and
T. Basil Smith and
Mike Wazlowski and
David Har and
Kwok-Ken Mak and
Sujith Arramreddy Pinnacle: IBM MXT in a Memory Controller
Chip . . . . . . . . . . . . . . . . . . 56--68
Manfred Stadler and
Markus Thalmann and
Thomas Röwer and
Hubert Kaeslin and
Norbert Felber and
Wolfgang Fichnter Design and Verification of a Stack
Processor Virtual Component . . . . . . 69--80
Hubert Kirrmann and
Pierre A. Zuber The IEC/IEEE Train Communication Network 81--92
Anonymous Product Summary . . . . . . . . . . . . 93--93
Richard Mateosian Micro Review: Pervasive technologies . . 94--95
Ken Sakamura EIC Message: In search of perfect
computing . . . . . . . . . . . . . . . 2--2
Gary S. Robinson Micro Standards: Centipedes, SDOs, and
consortia . . . . . . . . . . . . . . . 4--5
Shane Greenstein Micro Economics: Shortfalls, downturns,
and recessions . . . . . . . . . . . . . 6, 77
Anonymous Micro News: Optical computer; multilevel
cell technology; increased disk space;
new form of nitrogen; extreme
ultraviolet lithography . . . . . . . . 7--7
Richard H. Stern Micro Law: Preventing abuse of IEEE
standards policy . . . . . . . . . . . . 8--11
Alex (Sandy) Pentland Guest Editor's Introduction: Wearable
Information Devices . . . . . . . . . . 12--15
Paul Lukowicz and
Urs Anliker and
Gerhard Tröster and
Steven J. Schwartz and
Richard W. DeVaul The WearARM Modular, Low-Power Computing
Core . . . . . . . . . . . . . . . . . . 16--28
Nathan S. Shenck and
Joseph A. Paradiso Energy Scavenging With Shoe-Mounted
Piezoelectrics . . . . . . . . . . . . . 30--42
Bernt Schiele and
Tony Jebara and
Nuria Oliver Sensory-Augmented Computing: Wearing the
Museum's Guide . . . . . . . . . . . . . 44--52
L. Fernando Friedrich and
John Stankovic and
Marty Humphrey and
Michael Marley and
John Haskins, Jr. A Survey of Configurable,
Component-Based Operating Systems for
Embedded Applications . . . . . . . . . 54--68
Mansur H. Samadzadeh and
Loai E. Garalnabi Hardware/Software Cost Analysis of
Interrupt Processing Strategies . . . . 69--76
Richard Mateosian Micro Review: Project tools . . . . . . 78--79
Anonymous Product Summary . . . . . . . . . . . . 80--80
Ken Sakamura EIC Message: a Java-enabled evolution 2--3, 5
Hubert Kirrman Letter to the Editor: On ``Preventing
abuse of IEEE standards policy'' . . . . 5--5
Gary S. Robinson Micro Standards: Why standards are here
to stay . . . . . . . . . . . . . . . . 6--7
Shane Greenstein Micro Economics: An earful about Zvi's
e-mail . . . . . . . . . . . . . . . . . 8--10
Anonymous Micro News: Wireless LAN Chip;
Holographic data storage;
System-in-package FCRAM; Strained
silicon increases chip speed; 157-nm
lithography; Material improves computer
memory; HyperTransport Technology
Consortium; Faster transistor; Lead-free
chips; Micro Bits . . . . . . . . . . . 11, 68
Richard H. Stern Micro Law: More standardization
skullduggery . . . . . . . . . . . . . . 12--15, 69
Shouichi Hachiya Java Use in Mobile Information Devices:
Introducing JTRON . . . . . . . . . . . 16--21
Zhao Shang and
Zhichun Zhu and
Xiaodong Zhang Cached DRAM for ILP Processor Memory
Access Latency Reduction . . . . . . . . 22--32
Donglok Kim and
Ravia Managuli and
Yongmin Kim Data Cache and Direct Memory Access in
Programming Mediaprocessors . . . . . . 33--42
Thad Starner The Challenges of Wearable Computing:
Part 1 . . . . . . . . . . . . . . . . . 44--52
Thad Starner The Challenges of Wearable Computing:
Part 2 . . . . . . . . . . . . . . . . . 54--67
Richard Mateosian Micro Review: Making it work . . . . . . 70--71
Anonymous Product Summary . . . . . . . . . . . . 72--72
Ken Sakamura EIC's Message: Surviving the Slump,
Building the Future . . . . . . . . . . 5--5
Shane Greenstein Micro Economics: Explaining Booms,
Busts, and Errors . . . . . . . . . . . 6--7, 10
Richard H. Stern Micro Law: Another Update on
Standardization Skullduggery . . . . . . 8--10
Anonymous Micro News: Heightened security concerns
may drive chip technology; Chip detects
cancer marker; New spectroscopy tool
probes semiconductor etching processes;
RF MEMS projected to improve wireless;
2.0-GHz [Intel Xeon] processor in
production . . . . . . . . . . . . . . . 11--11
Dimiter R. Avresky and
Fabrizio Lombardi and
Karl E. Grosspietsch and
Barry W. Johnson Guest Editors' Introduction:
Fault-Tolerant Embedded Systems . . . . 12--15
Alfredo Benso and
Silvia Chiusano and
Paolo Prinetto A Self-Repairing Execution Unit for
Microprogrammed Processors . . . . . . . 16--22
Matthias Pflanz and
Heinrich Theodor Vierhaus Online Check and Recovery Techniques for
Dependable Embedded Processors . . . . . 24--40
Paul Richardson and
Larry Sieh and
Ali M. Elkateeb Fault-Tolerant Adaptive Scheduling for
Embedded Real-Time Systems . . . . . . . 41--51
Andrea Bondavalli and
Alessandro Fantechi and
Diego Latella and
Luca Simoncini Design Validation of Embedded Dependable
Systems . . . . . . . . . . . . . . . . 52--62
Gregory Provan and
Yi-Liang Chen Model-Based Fault-tolerant Control
Reconfiguration for General Network
Topologies . . . . . . . . . . . . . . . 64--76
Wenyi Feng and
Farzin Karimi and
Fabrizio Lombardi Fault Detection in a Tristate System
Environment . . . . . . . . . . . . . . 77--85
Richard Mateosian Micro Review: Managing Development . . . 86--87
Anonymous Product Summary . . . . . . . . . . . . 88--88
Anonymous Corrections: ``Online Check and Recovery
Techniques for Dependable Embedded
Processors'' and ``Micro Economics:
Explaining Booms, Busts, and Errors'' 2--2
Anonymous Micro News: Micro congratulations to
current and past EICs: Sakamura receives
Takeda Award; Steve Diamond is Computer
Society President-elect . . . . . . . . 3--3
Ken Sakamura Guest Editor's Introduction: Radio
Frequency Identification and Noncontact
Smart Cards . . . . . . . . . . . . . . 4--6
Ken Sakamura and
Noboru Koshizuka The eTRON Wide-Area Distributed-System
Architecture for E-Commerce . . . . . . 7--12
Jean-François Dhem and
Nathalie Feyt Hardware and Software Symbiosis Helps
Smart Card Evolution . . . . . . . . . . 14--25
Elena Trichina and
Marco Bucci and
Domenico De Seta and
Raimondo Luzzi Supplemental Cryptographic Hardware for
Smart Cards . . . . . . . . . . . . . . 26--35
Thomas Gyger and
Olivier Desjeux EasyRide: Active Transponders for a Fare
Collection System . . . . . . . . . . . 36--42
Kazuo Takaragi and
Mitsuo Usami and
Ryo Imura and
Rei Itsuki and
Tsuneo Satoh An Ultra Small Individual Recognition
Security Chip . . . . . . . . . . . . . 43--49
Sanjay Sarma and
David Brock and
Daniel Engels Radio Frequency Identification and the
Electronic Product Code . . . . . . . . 50--54
Ruby B. Lee and
Zhijie Shi and
Xiao Yang Efficient Permutation Instructions for
Fast Software Cryptography . . . . . . . 56--69
Shane Greenstein Micro Economics: E-business
Infrastructure . . . . . . . . . . . . . 70--71
Richard H. Stern Micro Law: Is mousetrapping unfair? . . 72--77
Richard Mateosian Micro Review: Holiday Reading . . . . . 78--79
Anonymous IEEE Micro 2001 Annual Index, Volume 21:
Author and Subject Listings . . . . . . 80--88
Ken Sakamura EIC's Message: The Next Challenge . . . 2--2
Shane Greenstein Micro Economics: The Ride Before the
Fall . . . . . . . . . . . . . . . . . . 4--5, 91
Richard H. Stern Micro Law: Is Gatoring Unfair or
Illegal? . . . . . . . . . . . . . . . . 6--7, 92--93
John Lockwood and
Marwan Krunz Guest Editors' Introduction: Hot
Interconnects . . . . . . . . . . . . . 8--9
Devavrat Shah and
Paolo Giaccone and
Balaji Prabhakar Efficient Randomized Algorithms for
Input-Queued Switch Scheduling . . . . . 10--18
Paolo Giaccone and
Devavrat Shah and
Balaji Prabhakar An Implementable Parallel Scheduler for
Input-Queued Switches . . . . . . . . . 19--25
Shubhendu S. Mukherjee and
Peter Bannon and
Steven Lang and
Aaron Spink and
David Webb The Alpha 21364 Network Architecture . . 26--35
Alan Charlesworth The Sun Fireplane Interconnect . . . . . 36--45
Fabrizio Petrini and
Wu-chun Feng and
Adolfy Hoisie and
Salvador Coll and
Eitan Frachtenberg The Quadrics Network: High-Performance
Clustering Technology . . . . . . . . . 46--57
Huan Liu Routing Table Compaction in Ternary CAM 58--64
Florian Braun and
John Lockwood and
Marcel Waldvogel Protocol Wrappers for Layered Network
Packet Processing in Reconfigurable
Hardware . . . . . . . . . . . . . . . . 66--74
Devavrat Shah and
Sundar Iyer and
Balaji Prabhakar and
Nick McKeown Maintaining Statistics Counters in
Router Line Cards . . . . . . . . . . . 76--81
Pablo Molinero-Fernández and
Nick McKeown TCP Switching: Exposing Circuits to IP 82--89
Anonymous Micro News: Optics speed data transfer;
Microchain MEMS; Micro Bits [IEEE
Standard 802.16 (Air Interface for Fixed
Broadband Wireless Access Systems)] . . 90--90
Richard Mateosian Micro Review: Learning proven lessons 94--95
Anonymous Product Summary . . . . . . . . . . . . 96--96
Ken Sakamura EIC's Message: a New Definition for
High-Performance Computing . . . . . . . 2--2
Shane Greenstein Micro Economics: Competition Policy for
Innovative Industries . . . . . . . . . 4--5, 72
John Kubiatowicz and
Andrew Wolfe Guest Editors' Introduction: Hot Chips
13 . . . . . . . . . . . . . . . . . . . 6--7
David H. Davies DataPlay's Mobile Information
Distribution and Storage Technology . . 8--15
Douglas C. Bossen and
Joel M. Tendler and
Kevin Reick Power4 System Design for High
Reliability . . . . . . . . . . . . . . 16--24
Michael Bedford Taylor and
Jason Kim and
Jason Miller and
David Wentzlaff and
Fae Ghodrat and
Ben Greenwald and
Henry Hoffman and
Paul Johnson and
Jae-Wook Lee and
Walter Lee and
Albert Ma and
Arvind Saraf and
Mark Seneski and
Nathan Shnidman and
Volker Strumpen and
Matt Frank and
Saman Amarasinghe and
Anant Agarwal The Raw Microprocessor: a Computational
Fabric for Software Circuits and
General-Purpose Programs . . . . . . . . 25--35
Fayé Briggs and
Michel Cekleov and
Ken Creta and
Manoj Khare and
Steve Kulick and
Akhilesh Kumar and
Lily Pao Looi and
Chitra Natarajan and
Sivakumar Radhakrishnan and
Linda Rankin Intel 870: a Building Block for
Cost-Effective, Scalable Servers . . . . 36--47
Chris Eddington InfiniBridge: An InfiniBand Channel
Adapter with Integrated Switch . . . . . 48--56
Zhichun Zhu and
Xiaodong Zhang Access-Mode Predictions for Low-Power
Cache Design . . . . . . . . . . . . . . 58--71
Ken Sakamura EIC's Message: The Test of Time . . . . 2--2
Shane Greenstein Micro Economics: Markets for Technology 4--5
Richard H. Stern Micro Law: Challenging search engines
under copyright law: Part 1 . . . . . . 6--7
Karl E. Grosspietsch Guest Editor's Introduction: Unorthodox
Computer Architectures . . . . . . . . . 8--9
Ulrich Rückert ULSI Architectures for Artificial Neural
Networks . . . . . . . . . . . . . . . . 10--19
Giovanni Danese and
Francesco Leporati and
Stefano Ramat A Parallel Neural Processor for
Real-Time Applications . . . . . . . . . 20--31
Jürgen Büddefeld and
Karl E. Grosspietsch Intelligent-Memory Architecture for
Artificial Neural Networks . . . . . . . 32--40
Marek Perkowski and
David Foote and
Qihong Chen and
Anas Al-Rabadi and
Lech Jozwiak Learning Hardware Using Multiple-Valued
Logic, Part 1: Introduction and Approach 41--51
Marek Perkowski and
David Foote and
Qihong Chen and
Anas Al-Rabadi and
Lech Jozwiak Learning Hardware Using Multiple-Valued
Logic, Part 2: Cube Calculus and
Architecture . . . . . . . . . . . . . . 52--61
Frank Eschmann and
Bernd Klauer and
Ronald Moore and
Klaus Waldschmidt SDAARC: An Extended Cache-Only Memory
Architecture . . . . . . . . . . . . . . 62--70
Richard Mateosian Micro Review: Enterprise Computing . . . 71--72
Ken Sakamura EIC's Message: Large Market on the
Horizon . . . . . . . . . . . . . . . . 4--4
Richard H. Stern Micro Law: FTC Piles onto Rambus'
Standardization Skullduggery . . . . . . 6--7, 86--87
Shane Greenstein Micro Economics: The Crash in
Competitive Telephony . . . . . . . . . 8--9, 88
Richard Mateosian Micro Review: Programming Books . . . . 10--11
Anonymous Micro News: Laser design makes less
expensive chip; Protein chains into a
wire; Crystals and computing;
Researchers say quantum design works;
Partners work for 0.9-micron CMOS; Tiny
technology generates heat; Organic
memory device; Micro Bits . . . . . . . 12--13
Philip Koopman Guest Editor's Introduction: Critical
Embedded Automotive Networks . . . . . . 14--18
Michael Ellims and
Stephen Parker and
James Zurlo Design and Analysis of a Robust
Real-Time Engine Control Network . . . . 20--27
Lars-Berno Fredriksson CAN for Critical Embedded Automotive
Networks . . . . . . . . . . . . . . . . 28--35
Reinhard Maier and
Günther Bauer and
Georg Stöger and
Stefan Poledna Time-Triggered Architecture: a
Consistent Computing Platform . . . . . 36--45
Joaquim Ferreira and
Paulo Pedreiras and
Luís Almeida and
José Alberto Fonseca The FTT-CAN Protocol for Flexibility in
Safety-Critical Systems . . . . . . . . 46--55
Roman Nossal and
Roland Lang Model-Based System Development: An
Approach to Building X-by-Wire
Applications . . . . . . . . . . . . . . 56--63
Brinkley Sprunt The Basics of Performance-Monitoring
Hardware . . . . . . . . . . . . . . . . 64--71
Brinkley Sprunt Pentium 4 Performance-Monitoring
Features . . . . . . . . . . . . . . . . 72--82
Anonymous Product Summary . . . . . . . . . . . . 84--85
Ken Sakamura EIC's Message: Future SOC Possibilities 7--7
Anonymous Micro News: IBM's Cell completes design
phase; Silver molecules render
electroluminescent light source;
Next-generation disc storage; IBM
electron microscope; Cornell
cluster-supercomputing expansion;
Silicon makes low-voltage gas sensor;
NIST chemists explore plastics; Micro
Bits . . . . . . . . . . . . . . . . . . 9--11
Shane Greenstein Micro Economics: The Price is Not Right 12--13, 96
Luciano Lavagno Guest Editor's Introduction: Systems on
a Chip---The Next Electronic Frontier 14--15
John Bainbridge and
Steve Furber Chain: a Delay-Insensitive Chip Area
Interconnect . . . . . . . . . . . . . . 16--23
Luca P. Carloni and
Alberto L. Sangiovanni-Vincentelli Coping with Latency in SOC Design . . . 24--35
Faraydon Karim and
Anh Nguyen and
Sujit Dey An Interconnect Architecture for
Networking Systems on Chips . . . . . . 36--45
Martti Forsell A Scalable High-Performance Computing
Solution for Networks on Chips . . . . . 46--55
Christophe Wolinski and
Maya Gokhale and
Kevin McCabe A Polymorphous Computing Fabric . . . . 56--68
Jin-Fu Li and
Hsin-Jung Huang and
Jeng-Bin Chen and
Chih-Pin Su and
Cheng-Wen Wu and
Chuang Cheng and
Shao-I Chen and
Chi-Yi Hwang and
Hsiao-Ping Lin A Hierarchical Test Methodology for
Systems on Chip . . . . . . . . . . . . 69--81
Ozgur Sinanoglu and
Alex Orailoglu Efficient Construction of Aliasing-Free
Compaction Circuitry . . . . . . . . . . 82--92
Richard Mateosian Micro Review: Personal Effectiveness . . 94--96
Ken Sakamura EIC's Message: Farewell message . . . . 2--2
Richard H. Stern Micro Law: Standardization and
Competitive Advantage . . . . . . . . . 4--5, 73
Anonymous Micro News: Intel expands 300-mm wafer
production; IBM claims smallest working
computer circuits; 802.11b chip
suppliers predict growth, market
effects; Samsung extends systems LSI
commitment; Light-emitting silicon
breakthrough; Gas sensors could reduce
power demands, lower cost;
Application-specific nanotubes; Micro
Bits . . . . . . . . . . . . . . . . . . 6--6, 74
Ken Sakamura Guest Editor's Introduction: Making
Computers Invisible . . . . . . . . . . 7--11
Jason L. Hill and
David E. Culler Mica: a Wireless Platform for Deeply
Embedded Networks . . . . . . . . . . . 12--24
Shigeru Shimada and
Masaaki Tanizaki and
Kishiko Maruyama Ubiquitous Spatial-Information Services
Using Cell Phones . . . . . . . . . . . 25--34
Peter Tandler and
Norbert Streitz and
Thorsten Prante Roomware-Moving Toward Ubiquitous
Computers . . . . . . . . . . . . . . . 36--47
Ken Sakamura and
Noboru Koshizuka T-Engine: The Open, Real-Time
Embedded-Systems Platform . . . . . . . 48--57
Fei Xia and
Alex V. Yakovlev and
Ian G. Clark and
Delong Shang Data Communication in Systems with
Heterogeneous Timing . . . . . . . . . . 58--69
Shane Greenstein Micro Economics: Which Industries Use
the Internet? . . . . . . . . . . . . . 70--72
Anonymous IEEE Micro, 2002 Annual Index, Volume 22 78--80
Pradip Bose EIC's Message: Looking Forward to Bright
New Beginnings . . . . . . . . . . . . . 5--7
Anonymous Micro News: IBM ups the ante in silicon
transistor speed; New benchmark suite
based on high-performance computing
applications, MPI and OpenMP [SPEC
HPC2002]; EU OKs Hitachi, Mitsubishi
Electric semiconductor joint venture;
Intel launches Pentium 4 at 3.06 GHz;
TSMC unveils viable 25nm transistors . . 6--6, 87
Anonymous Obituary: Rob Rau: 1951--2002: Pioneer
of VLIW/EPIC architecture dies . . . . . 7--7
John W. Lockwood Guest Editor's Introduction: Hot
Interconnects 10---Thinking beyond the
Internet . . . . . . . . . . . . . . . . 8--9
François Abel and
Cyriel Minkenberg and
Ronald P. Luijten and
Mitchell Gusat and
Ilias Iliadis A Four-Terabit Packet Switch Supporting
Long Round-Trip Times . . . . . . . . . 10--24
Hang-Sheng Wang and
Li-Shiuan Peh and
Sharad Malik A Power Model for Routers: Modeling
Alpha 21364 and InfiniBand Routers . . . 26--35
Rong Pan and
Balaji Prabhakar and
Lee Breslau and
Scott Shenker Approximate Fair Allocation of Link
Bandwidth . . . . . . . . . . . . . . . 36--43
Rina Panigrahy and
Samar Sharma Sorting and Searching using Ternary CAMs 44--53
David V. Schuehler and
John W. Lockwood TCP Splitter: a TCP/IP Flow Monitor in
Reconfigurable Hardware . . . . . . . . 54--59
Hans Eberle A Radio Network for Monitoring and
Diagnosing Computer Systems . . . . . . 60--65
Marc A. Viredaz and
Deborah A. Wallach Power Evaluation of a Handheld Computer 66--74
Richard H. Stern Micro Law: Weird Turn of Events in
Continuing Rambus Saga . . . . . . . . . 76--80
Richard Mateosian Micro Review: Leadership Annoyances . . 82--83
Shane Greenstein Micro Economics: Where Did the Internet
Go? . . . . . . . . . . . . . . . . . . 84--86
Pradip Bose EIC's Message: Issues and Trends in
High-Performance Processor Cores . . . . 5--5
Anonymous Micro News: Intel gears up 90-nm
processor, chip set rollout; IBM PowerPC
runs up to 2.5 GHz; AMD, Fujitsu form
chip venture . . . . . . . . . . . . . . 6--6
Richard Mateosian Micro Review: Nuts and Bolts . . . . . . 7, 77
John Wawrzynek and
Keith Diefendorff Guest Editors' Introduction: Hot Chips
14---Innovation in the Face of Uncertain
Economics . . . . . . . . . . . . . . . 8--11
Alfred K. Wong Microlithography: Trends, Challenges,
Solutions, and Their Impact on Design 12--21
Luiz André Barroso and
Jeffrey Dean and
Urs Hölzle Web Search for a Planet: The Google
Cluster Architecture . . . . . . . . . . 22--28
John Nickolls and
L. J. Madar III and
Scott Johnson and
Viresh Rustagi and
Ken Unger and
Mustafiz Choudhury Calisto: a Low-Power Single-Chip
Multiprocessor Communications Platform 29--43
Cameron McNairy and
Don Soltis Itanium 2 Processor Microarchitecture 44--55
David Koufaty and
Deborah T. Marr Hyperthreading Technology in the
Netburst Microarchitecture . . . . . . . 56--65
Chetana N. Keltcher and
Kevin J. McGrath and
Ardsher Ahmed and
Pat Conway The AMD Opteron Processor for
Multiprocessor Servers . . . . . . . . . 66--76
Shane Greenstein Micro Economics: Too Much Internet
Backbone? . . . . . . . . . . . . . . . 78--80
Pradip Bose Design and Integration: Chip- and
System-Level Challenges . . . . . . . . 5--5
Alberto Sangiovanni-Vincentelli and
Luciano Lavagno Guest Editors' Introduction: Trends and
Directions in Microelectronics . . . . . 6--7
Alberto Sangiovanni-Vincentelli Electronic-System Design in the
Automobile Industry . . . . . . . . . . 8--18
Theo A. C. M. Claasen System on a Chip: Changing IC Design
Today and in the Future . . . . . . . . 20--26
James D. Meindl Interconnect Opportunities for Gigascale
Integration . . . . . . . . . . . . . . 28--35
Bruno Murari Integrating Nonelectronic Components
into Electronic Microsystems . . . . . . 36--44
Nick Richardson and
Lun Bin Huang and
Razak Hossain and
Julian Lewis and
Tommy Zounes and
Naresh Soni The iCore 520-MHz Synthesizable CPU Core 46--57
Amaury N\`eve and
Denis Flandre and
Jean-Jacques Quisquater SOI Technology for Future
High-Performance Smart Cards . . . . . . 58--67
Shane Greenstein Micro Economics: An Era of Error . . . . 68--69
Richard Mateosian Micro Review: Evolution . . . . . . . . 70--72
Pradip Bose Editor-in-Chief's Message: Adapting Old
Paradigms to Meet New Challenges . . . . 5--5
Anonymous News: Intel's earnings double in
quarter; Tiny bubbles key to future
liquid-cooled systems; Chip diet tests
Cisco's resolve; Intel to release
machine learning libraries; Proposal in
to fit eight Alpha cores onto a chip;
Micro Bits . . . . . . . . . . . . . . . 6--7
Shane Greenstein Micro Economics: Moore Meets Malthus in
Multiples . . . . . . . . . . . . . . . 8--10
Richard Mateosian Micro Review: Managing Software Projects 11--13
Cristian Constantinescu Trends and Challenges in VLSI Circuit
Reliability . . . . . . . . . . . . . . 14--19
Stamatis Vassiliadis and
Stephan Wong and
Sorin Cotofana Microcode Processing: Positioning and
Directions . . . . . . . . . . . . . . . 21--30
Wangyang Lai and
Chin-Tau Lea A Programmable State Machine
Architecture for Packet Processing . . . 32--42
Bruce Jacob A Case for Studying DRAM Issues at the
System Level . . . . . . . . . . . . . . 44--56
Kerem Karadayi and
Vishal Markandey and
Jeremiah Golston and
Robert J. Gove and
Yongmin Kim Strategies for Mapping Algorithms to
Mediaprocessors for High Performance . . 58--70
John Hennessy and
Daniel Citron and
David Patterson and
Guri Sohi The Use and Abuse of SPEC: An ISCA Panel 73--77
Alan Clements CSIDC: Competing Students Design
Real-World Systems . . . . . . . . . . . 78--80
Richard H. Stern Micro Law: Unresolved Legal Questions
about Patents and Standard Setting . . . 5, 72--74
Richard Mateosian Micro Review: So Many Books, So Little
Time . . . . . . . . . . . . . . . . . . 6--7, 79--80
Pradip Bose and
David H. Albonesi and
Diana Marculescu Guest Editors' Introduction: Power and
Complexity Aware Design . . . . . . . . 8--11
Michael C. Huang and
Daniel Chaver and
Luis Piñuel and
Manuel Prieto and
Francisco Tirado Customizing the Branch Predictor to
Reduce Complexity and Energy Consumption 12--25
Lieven Eeckhout and
Sebastien Nussbaum and
James E. Smith and
Koen De Bosschere Statistical Simulation: Adding
Efficiency to the Computer Designer's
Toolbox . . . . . . . . . . . . . . . . 26--38
Nathalie Julien and
Johann Laurent and
Eric Senn and
Eric Martin Power Consumption Modeling and
Characterization of the TI C6201 . . . . 40--49
Jaume Abella and
Ramon Canal and
Antonio González Power- and Complexity-Aware Issue Queue
Designs . . . . . . . . . . . . . . . . 50--58
Joshua B. Fryman and
Chad M. Huneycutt and
Hsien-Hsin (Sean) Lee and
Kenneth M. Mackenzie and
David E. Schimmel Energy-Efficient Network Memory for
Ubiquitous Devices . . . . . . . . . . . 60--70
Shane Greenstein Micro Economics: Jumping on Bandwagons 75--77
Anonymous News: AMD launches Athlon 64; Intel
Pentium 4 aimed at gaming market; Sun
Microsystems cofounder [Bill Joy]
resigns; PlayStation 3 chip ready for
production . . . . . . . . . . . . . . . 85
Charles Moore Parting Thoughts: Managing the
Transition from Complexity to Elegance:
Knowing When You Have a Problem . . . . 88, 86--87
Maurice V. Wilkes Letters . . . . . . . . . . . . . . . . 5--5
Richard Mateosian Micro Review: Where we're going . . . . 6--7
Charles Moore and
Kevin W. Rudd and
Ruby B. Lee and
Pradip Bose Guest Editors' Introduction: Micro's Top
Picks from Microarchitecture Conferences 8--10
Haitham Akkary and
Ravi Rajwar and
Srikanth T. Srinivasan Checkpoint Processing and Recovery: An
Efficient, Scalable Alternative to
Reorder Buffers . . . . . . . . . . . . 11--19
Onur Mutlu and
Jared Stark and
Chris Wilkerson and
Yale N. Patt Runahead Execution: An Effective
Alternative to Large Instruction Windows 20--25
Michael K. Chen and
Kunle Olukotun The Jrpm System for Dynamically
Parallelizing Sequential Java Programs 26--35
Christoforos E. Kozyrakis and
David A. Patterson Scalable Vector Processors for Embedded
Systems . . . . . . . . . . . . . . . . 36--45
Karthikeyan Sankaralingam and
Ramadass Nagarajan and
Haiming Liu and
Changkyu Kim and
Jaehyuk Huh and
Doug Burger and
Stephen W. Keckler and
Charles Moore Exploiting ILP, TLP, and DLP with the
Polymorphous TRIPS Architecture . . . . 46--51
Kevin Skadron and
Mircea R. Stan and
Wei Huang and
Sivakumar Velusamy and
Karthik Sankaranarayanan and
David Tarjan Temperature-Aware Computer Systems:
Opportunities and Challenges . . . . . . 52--61
Grigorios Magklis and
Greg Semeraro and
David H. Albonesi and
Steven G. Dropsho and
Sandhya Dwarkadas and
Michael L. Scott Dynamic Frequency and Voltage Scaling
for a Multiple-Clock-Domain
Microprocessor . . . . . . . . . . . . . 62--68
Shubhendu S. Mukherjee and
Christopher T. Weaver and
Joel Emer and
Steven K. Reinhardt and
Todd Austin Measuring Architectural Vulnerability
Factors . . . . . . . . . . . . . . . . 70--75
Mohamed A. Gomaa and
Chad Scarbrough and
T. N. Vijaykumar and
Irith Pomeranz Transient-Fault Recovery for Chip
Multiprocessors . . . . . . . . . . . . 76--83
Timothy Sherwood and
Erez Perelman and
Greg Hamerly and
Suleyman Sair and
Brad Calder Discovering and Exploiting Program
Phases . . . . . . . . . . . . . . . . . 84--93
Alaa R. Alameldeen and
David A. Wood Addressing Workload Variability in
Architectural Simulations . . . . . . . 94--98
Changkyu Kim and
Doug Burger and
Stephen W. Keckler Nonuniform Cache Architectures for
Wire-Delay Dominated On-Chip Caches . . 99--107
Milo M. K. Martin and
Mark D. Hill and
David A. Wood Token Coherence: a New Framework for
Shared-Memory Multiprocessors . . . . . 108--116
Ravi Rajwar and
James Goodman Transactional Execution: Toward
Reliable, High-Performance
Multithreading . . . . . . . . . . . . . 117--125
José F. Martínez and
Josep Torrellas Speculative Synchronization:
Programmability and Performance for
Parallel Codes . . . . . . . . . . . . . 126--134
Anonymous 2003 IEEE Micro Annual Index, Vol. 23 136--139
Pradip Bose New Challenges and Burning Issues . . . 5--5
Anonymous News . . . . . . . . . . . . . . . . . . 6--6
Richard H. Stern Micro Law: Challenging Search Engines
and Pop-Ups Under Copyright Law: Part 2 7, 71--73
J. Bryan Lyles Guest Editor's Introduction: Hot
Interconnects 11- Solving Network
Bottlenecks . . . . . . . . . . . . . . 8--9
Justin (Gus) Hurwitz and
Wu-chun Feng End-to-End Performance of 10-Gigabit
Ethernet on Commodity Systems . . . . . 10--22
Greg Regnier and
Dave Minturn and
Gary McAlpine and
Vikram A. Saletore and
Annie Foong ETA: Experience with an Intel Xeon
Processor as a Packet Processing Engine 24--31
Andrew Lines Asynchronous Interconnect for
Synchronous SoC Design . . . . . . . . . 32--41
Jiuxing Liu and
Balasubramanian Chandrasekaran and
Weikuan Yu and
Jiesheng Wu and
Darius Buntinas and
Sushmitha Kini and
Dhabaleswar K. Panda and
Pete Wyckoff Microbenchmark Performance Comparison of
High-Speed Cluster Interconnects . . . . 42--51
Sarang Dharmapurikar and
Praveen Krishnamurthy and
Todd S. Sproull and
John W. Lockwood Deep Packet Inspection using Parallel
Bloom Filters . . . . . . . . . . . . . 52--61
David V. Schuehler and
James Moscola and
John W. Lockwood Architecture for a Hardware-Based,
TCP/IP Content-Processing System . . . . 62--69
Richard Mateosian Micro Review: Single Sourcing Mount Fuji 74--75
Shane Greenstein Micro Economics: Why Inventors are not
Famous . . . . . . . . . . . . . . . . . 76--78
Charles Moore Managing the Transition from Complexity
to Elegance: Design Convergence . . . . 80, 79
Pradip Bose EIC's Message: Chip-level
microarchitecture trends . . . . . . . . 5--5
Richard H. Stern Micro Law: Challenging search engines
and pop-ups under copyright law: Part 3 6, 70--72
Michael Flynn and
Pradeep Dubey Guest Editors' Introduction: Hot Chips
15---Scaling the Silicon Mountain . . . 7--9
Stefan Rusu and
Harry Muljono and
Brian Cherkauer Itanium 2 Processor 6M: Higher Frequency
and Larger L3 Cache . . . . . . . . . . 10--18
Sanjiv Kapil and
Harlan McGhan and
Jesse Lawrendra A Chip Multithreaded Processor for
Network-Facing Workloads . . . . . . . . 20--30
Deepu Talla and
Ching-Yu Hung and
Raj Talluri and
Frank Brill and
David Smith and
David Brier and
Bruce Xiong and
Derek Huynh Anatomy of a Portable Digital
Mediaprocessor . . . . . . . . . . . . . 32--39
Ron Kalla and
Balaram Sinharoy and
Joel M. Tendler IBM Power5 Chip: a Dual-Core
Multithreaded Processor . . . . . . . . 40--47
Uri Cummings PivotPoint: Clockless Crossbar Switch
for High-Performance Embedded Systems 48--59
Ravikumar V. C. and
Rabi N. Mahapatra TCAM Architecture for IP Lookup Using
Prefix Properties . . . . . . . . . . . 60--69
Shane Greenstein Micro Economics: The paradox of
commodities . . . . . . . . . . . . . . 73--75
Anonymous Micro News . . . . . . . . . . . . . . . 76--77
Chuck Moore Getting it right . . . . . . . . . . . . 80, 79
Pradip Bose EIC's Message: General-purpose versus
application-specific processors . . . . 5--5
Richard H. Stern Micro Law: Collecting patent
infringement damages on unpatented
products . . . . . . . . . . . . . . . . 6--7
Alex Veidenbaum Guest Editor's Introduction:
Application-Specific Processors . . . . 8--9
Michael L. Chu and
Kevin C. Fan and
Rajiv A. Ravindran and
Scott A. Mahlke Cost-Sensitive Partitioning in an
Architecture Synthesis System for
Multicluster Processors . . . . . . . . 10--20
Peter Petrov and
Alex Orailoglu Transforming Binary Code for Low-Power
Embedded Processors . . . . . . . . . . 21--33
Alireza Hodjat and
Ingrid Verbauwhede High-Throughput Programmable
Cryptocoprocessor . . . . . . . . . . . 34--45
Matthias Meyer A Novel Processor Architecture with
Exact Tag-Free Pointers . . . . . . . . 46--55
Faraydon Karim and
Alain Mellan and
Anh Nguyen and
Utku Aydonat and
Tarek Abdelrahman A Multilevel Computing Architecture for
Embedded Multimedia Applications . . . . 56--66
Shane Greenstein Micro Economics: Imitation happens . . . 67--69
Richard Mateosian Micro Review: Back to the future . . . . 70--71
Anonymous Micro News . . . . . . . . . . . . . . . 72--72
Pradip Bose Editor in Chief's Message: Saving
power-Lessons from embedded systems . . 5--6
Richard H. Stern Micro Law: FTC turns back challenge on
patent coverage . . . . . . . . . . . . 7, 85--86
Alessio Bechini and
Thomas M. Conte and
Cosimo Antonio Prete Guest Editors' Introduction:
Opportunities and Challenges in Embedded
Systems . . . . . . . . . . . . . . . . 8--9
Alexander G. Dean Efficient Real-Time Fine-Grained
Concurrency on Low-Cost Microcontrollers 10--22
Francisco J. Cazorla and
Alex Ramirez and
Mateo Valero and
Peter M. W. Knijnenburg and
Rizos Sakellariou and
Enrique Fernández QoS for High-Performance SMT Processors
in Embedded Systems . . . . . . . . . . 24--31
Taeweon Suh and
Hsien-Hsin S. Lee and
Douglas M. Blough Integrating Cache Coherence Protocols
for Heterogeneous Multiprocessor
Systems, Part 1 . . . . . . . . . . . . 33--41
David Andrews and
Douglas Niehaus and
Razali Jidin and
Michael Finley and
Wesley Peck and
Michael Frisbie and
Jorge Ortiz and
Ed Komp and
Peter Ashenden Programming Models for Hybrid FPGA--CPU
Computational Components: a Missing Link 42--53
Sridhar Rajagopal and
Joseph R. Cavallaro and
Scott Rixner Design Space Exploration for Real-Time
Embedded Stream Processors . . . . . . . 54--66
Andreas Krall and
Ivan Pryanishnikov and
Ulrich Hirnschrott and
Christian Panis xDSPcore: a Compiler-Based Configurable
Digital Signal Processor . . . . . . . . 67--78
Shane Greenstein Micro Economics: The diamond-wafer
paradox: a modern mystery . . . . . . . 79--81
Anonymous Micro News . . . . . . . . . . . . . . . 82--82
Richard Mateosian Micro Review: Attacking complexity . . . 88, 87
Pradip Bose Communication versus Computation . . . . 5--5
Richard H. Stern Micro Law: Vicarious liability for
infringement . . . . . . . . . . . . . . 6, 79--82
Ioannis Papaefstathiou and
Nikos A. Nikolaou and
Bharat Doshi and
Eric Grosse Guest Editors' Introduction: Network
Processors for Future High-End Systems
and Applications . . . . . . . . . . . . 7--9
Jakob Carlström and
Thomas Bodén Synchronous Dataflow Architecture for
Network Processors . . . . . . . . . . . 10--18
Ioannis Papaefstathiou and
Stylianos Perissakis and
Theofanis G. Orphanoudakis and
Nikos A. Nikolaou and
George Kornaros and
Nicholas A. Zervos and
George Konstantoulakis and
Dionisios N. Pnevmatikatos and
Kyriakos Vlachos PRO3: a Hybrid NPU Architecture . . . . 20--33
Yan Luo and
Jun Yang and
Laxmi N. Bhuyan and
Li Zhao NePSim: a Network Processor Simulator
with a Power Evaluation Framework . . . 34--44
Niraj Shah and
William Plishker and
Kaushik Ravindran and
Kurt Keutzer NP-Click: a Productive Software
Development Approach for Network
Processors . . . . . . . . . . . . . . . 45--54
Zhangxi Tan and
Chuang Lin and
Hao Yin and
Bo Li Optimization and Benchmark of
Cryptographic Algorithms on Network
Processors . . . . . . . . . . . . . . . 55--69
Taeweon Suh and
Hsien-Hsin S. Lee and
Douglas M. Blough Integrating Cache Coherence Protocols
for Heterogeneous Multiprocessor
Systems, Part 2 . . . . . . . . . . . . 70--78
Shane Greenstein Micro Economics: Creative Destruction
and Deconstruction . . . . . . . . . . . 83--85
Richard Mateosian Micro Review: Seek and Show . . . . . . 88, 86--87
Pradip Bose EIC's Message: Computer architecture
research: Shifting priorities and newer
challenges . . . . . . . . . . . . . . . 5--5
Shane Greenstein Micro Economics: Canaries, whips, and
sails . . . . . . . . . . . . . . . . . 6--7, 129
David H. Albonesi Guest Editor's Introduction: Micro's Top
Picks from Microarchitecture Conferences 8--9
Dan Ernst and
Shidhartha Das and
Seokwoo Lee and
David Blaauw and
Todd Austin and
Trevor Mudge and
Nam Sung Kim and
Krisztián Flautner Razor: Circuit-Level Correction of
Timing Errors for Low-Power Operation 10--20
Jared C. Smolens and
Brian T. Gold and
Jangwoo Kim and
Babak Falsafi and
James C. Hoe and
Andreas G. Nowatzyk Fingerprinting: Bounding
Soft-Error-Detection Latency and
Bandwidth . . . . . . . . . . . . . . . 22--29
Christopher T. Weaver and
Joel Emer and
Shubhendu S. Mukherjee and
Steven K. Reinhardt Reducing the Soft-Error Rate of a
High-Performance Microprocessor . . . . 30--37
Xiaodong Li and
Zhenmin Li and
Pin Zhou and
Yuanyuan Zhou and
Sarita V. Adve and
Sanjeev Kumar Performance-Directed Energy Management
for Storage Systems . . . . . . . . . . 38--49
Pin Zhou and
Feng Qin and
Wei Liu and
Yuanyuan Zhou and
Josep Torrellas iWatcher: Simple, General Architectural
Support for Software Debugging . . . . . 50--56
Brian A. Fields and
Rastislav Bodík and
Mark D. Hill and
Chris J. Newburn Interaction Cost: For When Event Counts
Just Don't Add Up . . . . . . . . . . . 57--61
Srikanth T. Srinivasan and
Ravi Rajwar and
Haitham Akkary and
Amit Gandhi and
Michael Upton Continual Flow Pipelines: Achieving
Resource-Efficient Latency Tolerance . . 62--73
Perry H. Wang and
Jamison D. Collins and
Hong Wang and
Dongkeun Kim and
Bill Greene and
Kai-Ming Chan and
Aamir B. Yunus and
Terry Sych and
Stephen F. Moore and
John P. Shen Helper Threads via Virtual
Multithreading . . . . . . . . . . . . . 74--82
Ronny Krashinsky and
Christopher Batten and
Mark Hampton and
Steve Gerding and
Brian Pharris and
Jared Casper and
Krste Asanovic The Vector-Thread Architecture . . . . . 84--90
Lance Hammond and
Brian D. Carlstrom and
Vicky Wong and
Michael Chen and
Christos Kozyrakis and
Kunle Olukotun Transactional Coherence and Consistency:
Simplifying Parallel Hardware and
Software . . . . . . . . . . . . . . . . 92--103
Jaehyuk Huh and
Doug Burger and
Jichuan Chang and
Gurindar S. Sohi Speculative Incoherent Cache Protocols 104--109
Harold W. Cain and
Mikko H. Lipasti Memory Ordering: a Value-Based Approach 110--117
Simha Sethumadhavan and
Rajagopalan Desikan and
Doug Burger and
Charles R. Moore and
Stephen W. Keckler Scalable Hardware Memory Disambiguation
for High-ILP Processors . . . . . . . . 118--127
Anonymous Micro News . . . . . . . . . . . . . . . 129--129
Richard Mateosian Micro Review: More on old themes . . . . 133--134
Anonymous 2004 Annual Index . . . . . . . . . . . 135--144
Pradip Bose EIC's Message: The ``power'' of
communication . . . . . . . . . . . . . 5--5
Richard H. Stern Micro Law: FTC cracks down on spyware
and PC hijacking, but not true lies . . 6--7, 100--101
James P. G. Sterbenz and
Dimitrios Stiliadis Guest Editors' Introduction: Hot
Interconnects 12 . . . . . . . . . . . . 8--9
Venkata Krishnan and
David Mayhew Localized Congestion Control in Advanced
Switching Interconnects . . . . . . . . 10--18
Jiuxing Liu and
Amith Mamidala and
Abhinav Vishnu and
Dhabaleswar K. Panda Evaluating InfiniBand Performance with
PCI Express . . . . . . . . . . . . . . 20--29
Thomas H. Dunigan, Jr. and
Jeffrey S. Vetter and
James B. White III and
Patrick H. Worley Performance Evaluation of the Cray X1
Distributed Shared-Memory Architecture 30--40
Avinash Karanth Kodi and
Ahmed Louri Design of a High-Speed Optical
Interconnect for Scalable Shared-Memory
Multiprocessors . . . . . . . . . . . . 41--49
Fang Yu and
Randy H. Katz and
T. V. Lakshman Efficient Multimatch Packet
Classification and Lookup with TCAM . . 50--59
Bharath Madhusudan and
John W. Lockwood A Hardware-Accelerated System for
Real-Time Worm Detection . . . . . . . . 60--69
Srikanth Arekapudi and
Shang-Tse Chuang and
Isaac Keslassy and
Nick McKeown Using Hardware to Configure a
Load-Balanced Switch . . . . . . . . . . 70--78
Ayose Falcón and
Jared Stark and
Alex Ramirez and
Konrad Lai and
Mateo Valero Better Branch Prediction Through
Prophet/Critic Hybrids . . . . . . . . . 80--89
Kyle J. Nesbit and
James E. Smith Data Cache Prefetching Using a Global
History Buffer . . . . . . . . . . . . . 90--97
Richard Mateosian Micro Review: Too much information . . . 98--99
Shane Greenstein Micro Economics: Not a mellifluous march
to maturity . . . . . . . . . . . . . . 104, 102--103
Pradip Bose EIC's Message: Variation-tolerant design 5--5
Richard Mateosian Micro Review: Thinking about history and
design . . . . . . . . . . . . . . . . . 6--7
Bill Dally and
Keith Diefendorff Hot Chips 16: Power, Parallelism, and
Memory Performance . . . . . . . . . . . 8--9
Cameron McNairy and
Rohit Bhatia Montecito: a Dual-Core, Dual-Thread
Itanium Processor . . . . . . . . . . . 10--20
Poonacha Kongetira and
Kathirgamar Aingaran and
Kunle Olukotun Niagara: a 32-Way Multithreaded Sparc
Processor . . . . . . . . . . . . . . . 21--29
Rajesh Kota and
Rich Oehler Horus: Large-Scale Symmetric
Multiprocessing for Opteron Systems . . 30--40
John Montrym and
Henry Moreton The GeForce 6800 . . . . . . . . . . . . 41--51
Hans Eberle and
Sheueling Shantz and
Vipul Gupta and
Nils Gura and
Leonard Rarick and
Lawrence Spracklen Accelerating Next-Generation Public-Key
Cryptosystems on General-Purpose CPUs 52--59
Jörg Keller and
Andreas Grävinghoff Thread-Based Virtual Duplex Systems in
Embedded Environments . . . . . . . . . 60--69
Shane Greenstein Micro Economics: Communications
consolidation after an era of no
restraints . . . . . . . . . . . . . . . 72, 70--71
Pradip Bose EIC's Message: Integrated
microarchitectures . . . . . . . . . . . 5--6
Richard H. Stern Micro Law: The antitrust ghost in the
standard-setting machine . . . . . . . . 7--9
Shane Greenstein Micro Economics: The anatomy of
foresight traps . . . . . . . . . . . . 10--12
Richard Mateosian Micro Review: Dealing with globalization 13--15
Michael J. Flynn and
Patrick Hung Microprocessor Design Issues: Thoughts
on the Road Ahead . . . . . . . . . . . 16--31
Shailender Chaudhry and
Paul Caprioli and
Sherman Yip and
Marc Tremblay High-Performance Throughput Computing 32--45
Adrian Cristal and
Oliverio J. Santana and
Francisco Cazorla and
Marco Galluzzi and
Tanausu Ramirez and
Miquel Pericas and
Mateo Valero Kilo-Instruction Processors: Overcoming
the Memory Wall . . . . . . . . . . . . 48--57
Tilak Agerwala and
Siddhartha Chatterjee Computer Architecture: Challenges and
Opportunities for the Next Decade . . . 58--69
Jayanth Srinivasan and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers Lifetime Reliability: Toward an
Architectural Solution . . . . . . . . . 70--80
Mancia Anguita and
J. Manuel Martinez-Lechado MP3 Optimization Exploiting Processor
Architecture and using Better Algorithms 81--92
Philip G. Emma Micro Innovations: Inventions and the
creative process . . . . . . . . . . . . 96, 93--95
Pradip Bose EIC's Message: Presilicon modeling:
challenges in the late CMOS era . . . . 5--6
Phillip G. Emma Micro Innovations: What is patentable? 7--9
Zhichun Zhu and
Xiaodong Zhang Look-Ahead Architecture Adaptation to
Reduce Processor Power Consumption . . . 10--19
Yen-Jen Chang and
Feipei Lai Dynamic Zero-Sensitivity Scheme for
Low-Power Cache Memories . . . . . . . . 20--32
Jon Beecroft and
David Addison and
David Hewson and
Moray McLaren and
Duncan Roweth and
Fabrizio Petrini and
Jarek Nieplocha QsNet$^{\rm II}$: Defining
High-Performance Network Design . . . . 34--47
Mohammad J. Akhbarizadeh and
Mehrdad Nourani and
Cyrus D. Cantrell Prefix Segregation Scheme for a
TCAM-Based IP Forwarding Engine . . . . 48--63
Weidong Wu and
Jian Shi and
Ling Zuo and
Bingxin Shi Power-Efficient TCAMS for Bursty Access
Patterns . . . . . . . . . . . . . . . . 64--72
Richard H. Stern Micro Law: Standardization skullduggery
update: UMTS standard . . . . . . . . . 73--76
Shane Greenstein Micro Economics: Explorers and
expanders, both early and late . . . . . 77--79
Richard Mateosian Micro Review: Going through the database 80, 79
Pradip Bose EIC's Message: High performance at
affordable power . . . . . . . . . . . . 5--5
Kunio Uchiyama and
Pradip Bose Guest Editors' Introduction:
Energy-Efficient Design . . . . . . . . 6--9
Osamu Takahashi and
Scott Cottier and
Sang H. Dhong and
Brian Flachs and
Joel Silberman Power-Conscious Design of the CELL
Processor's Synergistic Processor
Element . . . . . . . . . . . . . . . . 10--18
Seiji Maeda and
Shigehiro Asano and
Tomofumi Shimada and
Koichi Awazu and
Haruyuki Tago A Real-Time Software Platform for the
Cell Processor . . . . . . . . . . . . . 20--29
Toru Asano and
Joel Silberman and
Sang H. Dhong and
Osamu Takahashi and
Michael White and
Scott Cottier and
Takaaki Nakazato and
Atsushi Kawasumi and
Hiroshi Yoshihara Low-Power Design Approach of 11FO4
256-Kbyte Embedded SRAM for the
Synergistic Processor Element of a Cell
Processor . . . . . . . . . . . . . . . 30--38
Canturk Isci and
Alper Buyuktosunoglu and
Margaret Martonosi Long-Term Workload Phases: Duration
Predictions and Applications to DVFS . . 39--51
Qiang Wu and
Philo Juang and
Margaret Martonosi and
Li-Shiuan Peh and
Douglas W. Clark Formal Control Techniques for
Power-Performance Management . . . . . . 52--62
Diana Marculescu and
Emil Talpes Energy Awareness and Uncertainty in
Microarchitecture-Level Design . . . . . 64--76
Jeffery B. Fromm and
Robert A. Skitol Micro Law: Update on the antitrust ghost
in the standard-setting machine . . . . 77--79
Phil Emma Patents: To file or not to file? . . . . 79--81
Shane Greenstein Micro Economics: Outsourcing and
climbing a value chain . . . . . . . . . 84, 83
Pradip Bose EIC's Message: Designing microprocessors
with robust functionality and
performance . . . . . . . . . . . . . . 5--5
Shane Greenstein Micro Economics: Wireless access and
electrical markets: Becoming similar? 6--7
Sarita V. Adve and
Pia Sanda Guest Editors' Introduction:
Reliability-Aware Microarchitecture . . 8--9
Shekhar Borkar Designing Reliable Systems from
Unreliable Components: The Challenges of
Transistor Variability and Degradation 10--16
Ravishankar K. Iyer and
Nithin M. Nakka and
Zbigniew T. Kalbarczyk and
Subhasish Mitra Recent Advances and New Avenues in
Hardware-Level Reliability Support . . . 18--29
Giacinto P. Saggese and
Nicholas J. Wang and
Zbigniew T. Kalbarczyk and
Sanjay J. Patel and
Ravishankar K. Iyer An Experimental Study of Soft Errors in
Microprocessors . . . . . . . . . . . . 30--39
Zhijian Lu and
John Lach and
Mircea R. Stan and
Kevin Skadron Improved Thermal Management with
Reliability Banking . . . . . . . . . . 40--49
Brian T. Gold and
Jangwoo Kim and
Jared C. Smolens and
Eric S. Chung and
Vasileios Liaskovitis and
Eriko Nurvitadhi and
Babak Falsafi and
James C. Hoe and
Andreas G. Nowatzyk TRUSS: a Reliable, Scalable Server
Architecture . . . . . . . . . . . . . . 51--59
M. Wasiur Rashid and
Edwin J. Tan and
Michael C. Huang and
David H. Albonesi Power-Efficient Error Tolerance in Chip
Multiprocessors . . . . . . . . . . . . 60--70
Daniel Stasiak and
Rajat Chaudhry and
Dennis Cox and
Stephen Posluszny and
Jim Warnock and
Steve Weitzel and
Dieter Wendel and
Michael Wang Cell Processor Low-Power Design
Methodology . . . . . . . . . . . . . . 71--78
Phil Emma Micro Innovations: Writing the claims
for a patent . . . . . . . . . . . . . . 79--81
Richard Mateosian Micro Review: Year-end cleanup . . . . . 82--84
Richard Stern Micro Law: Transnational electronic
systems and patent infringement . . . . 85--88
Anonymous IEEE Micro 2005 Annual Index, Vol. 25 92--103
Pradip Bose EIC's Message: Measuring the impact of
microarchitectural ideas . . . . . . . . 5--6
Shane Greenstein Micro Economics: Format wars all over
again . . . . . . . . . . . . . . . . . 7, 140
Josep Torrellas Guest Editor's Introduction: Micro's Top
Picks from Microarchitecture Conferences 8--9
Onur Mutlu and
Hyesoon Kim and
Yale N. Patt Efficient Runahead Execution:
Power-Efficient Memory Latency Tolerance 10--20
Ibrahim Hur and
Calvin Lin Adaptive History-Based Memory Schedulers
for Modern Processors . . . . . . . . . 22--29
Amit Gandhi and
Haitham Akkary and
Ravi Rajwar and
Srikanth T. Srinivasan and
Konrad Lai Scalable Load and Store Processing in
Latency-Tolerant Processors . . . . . . 30--39
Ronald D. Barnes and
Shane Ryoo and
Wen-mei W. Hwu Tolerating Cache-Miss Latency with
Multipass Pipelines . . . . . . . . . . 40--47
Hyesoon Kim and
Onur Mutlu and
Yale N. Patt and
Jared Stark Wish Branches: Enabling Adaptive and
Aggressive Predicated Execution . . . . 48--58
C. Scott Ananian and
Krste Asanovic and
Bradley C. Kuszmaul and
Charles E. Leiserson and
Sean Lie Unbounded Transactional Memory . . . . . 59--69
Jason F. Cantin and
James E. Smith and
Mikko H. Lipasti and
Andreas Moshovos and
Babak Falsafi Coarse-Grain Coherence Tracking:
RegionScout and Region Coherence Arrays 70--79
Jose Renau and
Karin Strauss and
Luis Ceze and
Wei Liu and
Smruti R. Sarangi and
James Tuck and
Josep Torrellas Energy-Efficient Thread-Level
Speculation . . . . . . . . . . . . . . 80--91
Mohamed A. Gomaa and
T. N. Vijaykumar Opportunistic Transient-Fault Detection 92--99
Satish Narayanasamy and
Gilles Pokam and
Brad Calder BugNet: Recording Application-Level
Execution for Deterministic Replay
Debugging . . . . . . . . . . . . . . . 100--109
Lin Tan and
Timothy Sherwood Architectures for Bit-Split String
Scanning in Intrusion Detection . . . . 110--117
Qiang Wu and
Margaret Martonosi and
Douglas W. Clark and
Vijay Janapa Reddi and
Dan Connors and
Youfeng Wu and
Jin Lee and
David Brooks Dynamic-Compiler-Driven Control for
Microprocessor Energy and Performance 119--129
Li Shang and
Li-Shiuan Peh and
Amit Kumar and
Niraj K. Jha Temperature-Aware On-Chip Networks . . . 130--139
Richard Mateosian Micro Review: The future will soon be
here . . . . . . . . . . . . . . . . . . 141--142
Phil Emma Micro Innovations: How to write a patent 144, 143
Pradip Bose Editor-in-Chief's Message: Workload
characterization: a key aspect of
microarchitecture design . . . . . . . . 5--6
Shane Greenstein Micro Economics: Andy's acceleration and
Moore's momentum . . . . . . . . . . . . 7, 81--82
John Sell and
Alan Jay Smith Guest Editors' Introduction: Hot Chips
17 . . . . . . . . . . . . . . . . . . . 8--9
Michael Gschwind and
H. Peter Hofstee and
Brian Flachs and
Martin Hopkins and
Yukio Watanabe and
Takeshi Yamazaki Synergistic Processing in Cell's
Multicore Architecture . . . . . . . . . 10--24
Jeff Andrews and
Nick Baker Xbox 360 System Architecture . . . . . . 25--37
Boris Murmann Digitally Assisted Analog Circuits . . . 38--47
Volker Lindenstruth An Extreme Processor for an Extreme
Experiment . . . . . . . . . . . . . . . 48--57
Cary Gunn CMOS Photonics for High-Speed
Interconnects . . . . . . . . . . . . . 58--66
Amit Agarwal and
Saibal Mukhopadhyay and
Arijit Raychowdhury and
Kaushik Roy and
Chris H. Kim Leakage Power Analysis and Reduction for
Nanoscale Circuits . . . . . . . . . . . 68--80
Philip G. Emma Micro Innovations: The best patents of
all . . . . . . . . . . . . . . . . . . 84, 83
Pradip Bose Editor-in-Chief's Message: Robust
On-Chip Communication . . . . . . . . . 5--5
Shane Greenstein Micro Economics: Room for a Thousand
Flowers to Bloom . . . . . . . . . . . . 6, 93
Fabrizio Petrini and
Olav Lysne and
Ron Brightwell Guest Editors' Introduction:
High-Performance Interconnects . . . . . 7--9
Michael Kistler and
Michael Perrone and
Fabrizio Petrini Cell Multiprocessor Communication
Network: Built for Speed . . . . . . . . 10--23
Pavan Balaji and
Wu-chun Feng and
Dhabaleswar K. Panda Bridging the Ethernet--Ethernot
Performance Gap . . . . . . . . . . . . 24--40
Ron Brightwell and
Kevin T. Pedretti and
Keith D. Underwood and
Trammell Hudson SeaStar Interconnect: Balanced Bandwidth
for Scalable Performance . . . . . . . . 41--57
Cyriel Minkenberg and
François Abel and
Peter Müller and
Raj Krishnamurthy and
Mitchell Gusat and
Peter Dill and
Ilias Iliadis and
Ronald Luijten and
B. Roe Hemenway and
Richard Grzybowski and
Enrico Schiattarella Designing a Crossbar Scheduler for HPC
Applications . . . . . . . . . . . . . . 58--71
Li Zhao and
Yan Luo and
Laxmi N. Bhuyan and
Ravi Iyer A Network Processor-Based, Content-Aware
Switch . . . . . . . . . . . . . . . . . 72--84
Richard Mateosian Micro Review: More on Old Topics . . . . 86--87
Richard Stern Micro Law: Court Dismisses ``Copyright
Champion's'' Source Code Copyright Suit 88--90
Philip G. Emma Micro Innovations: Patent Claims
Revisited: Examiners and Trolls . . . . 96, 94--95
Pradip Bose Editor-in-Chief's Message: Pre-Silicon
Modeling and Analysis: Impact On Real
Design . . . . . . . . . . . . . . . . . 3--3
Shane Greenstein Micro Economics: Legislating
Entrepreneurship: An Oxymoron? . . . . . 4, 86
Timothy Sherwood and
Joshua J. Yi Guest Editors' Introduction: Computer
Architecture Simulation and Modeling . . 5--7
Alaa R. Alameldeen and
David A. Wood IPC Considered Harmful for
Multiprocessor Workloads . . . . . . . . 8--17
Thomas F. Wenisch and
Roland E. Wunderlich and
Michael Ferdman and
Anastassia Ailamaki and
Babak Falsafi and
James C. Hoe SimFlex: Statistical Sampling of
Computer System Simulation . . . . . . . 18--31
Michael Van Biesbrouck and
Brad Calder and
Lieven Eeckhout Efficient Sampling Startup for SimPoint 32--42
Sudhanva Gurumurthi and
Youngjae Kim and
Anand Sivasubramaniam Using STEAM for Thermal Simulation of
Storage Systems . . . . . . . . . . . . 43--51
Nathan L. Binkert and
Ronald G. Dreslinski and
Lisa R. Hsu and
Kevin T. Lim and
Ali G. Saidi and
Steven K. Reinhardt The M5 Simulator: Modeling Networked
Systems . . . . . . . . . . . . . . . . 52--60
Yong-Joon Park and
Zhao Zhang and
Gyungho Lee Microarchitectural Protection Against
Stack-Based Buffer Overflow Attacks . . 62--71
Jesus Alastruey and
Jose Luis Briz and
Pablo Ibáñez and
Victor Viñals Software Demand, Hardware Supply . . . . 72--82
Richard Mateosian Micro Review: Old and New . . . . . . . 83--85
Philip G. Emma Micro Innovations: The Mechanics of
Filing a Patent . . . . . . . . . . . . 88, 87
Pradip Bose Editor-in-Chief's Message: Designing
reliable systems with unreliable
components . . . . . . . . . . . . . . . 5--6
Shane Greenstein Micro Economics: Ubiquitous clicks and
complements . . . . . . . . . . . . . . 7--8
Richard Stern Micro Law: New Jersey federal court
holds Qualcomm's unFRANDly acts no
antitrust violation . . . . . . . . . . 9, 84--85
Egas Henes Neto and
Ivandro Ribeiro and
Michele Vieira and
Gilson Wirth and
Fernanda Lima Kastensmidt Using Bulk Built-in Current Sensors to
Detect Soft Errors . . . . . . . . . . . 10--18
Kundan Nepal and
R. Iris Bahar and
Joseph Mundy and
William R. Patterson and
Alexander Zaslavsky MRF Reinforcer: a Probabilistic Element
for Space Redundancy in Nanoscale
Circuits . . . . . . . . . . . . . . . . 19--27
Radu Teodorescu and
Jun Nakano and
Josep Torrellas SWICH: a Prototype for Efficient
Cache-Level Checkpointing and Rollback 28--40
Ricardo E. Gonzalez A Software-Configurable Processor
Architecture . . . . . . . . . . . . . . 42--51
Pedro J. García and
Francisco J. Quiles and
José Flich and
José Duato and
Ian Johnson and
Finbar Naven Efficient, Scalable Congestion
Management for Interconnection Networks 52--66
Valentina Salapura and
Robert Walkup and
Alan Gara Exploiting Workload Parallelism for
Performance and Power Optimization in
Blue Gene . . . . . . . . . . . . . . . 67--81
Richard Mateosian Micro Review: So many books . . . . . . 82--83
Philip G. Emma Micro Innovations: Prosecuting your
patent . . . . . . . . . . . . . . . . . 88, 87
Pradip Bose Editor-in-Chief's Message: Looking
briefly back, and then forward \ldots 8--9
Shane Greenstein Micro Economics: Four nightmares for net
neutrality . . . . . . . . . . . . . . . 12--13
Daniel Gracia Pérez and
Hugues Berry and
Olivier Temam A Sampling Method Focusing on
Practicality . . . . . . . . . . . . . . 14--28
Osman S. Unsal and
James W. Tschanz and
Keith Bowman and
Vivek De and
Xavier Vera and
Antonio González and
Oguz Ergin Impact of Parameter Variations on
Circuits and Microarchitecture . . . . . 30--39
Rajeev Balasubramonian and
Naveen Muralimanohar and
Karthik Ramani and
Liqun Cheng and
John B. Carter Leveraging Wire Properties at the
Microarchitecture Level . . . . . . . . 40--52
Anonymous IEEE Micro 2006 Annual Index, Volume 26 56--67
Philip G. Emma Micro Innovations: Five strategies for
overcoming obviousness . . . . . . . . . 72, 70--71
David H. Albonesi Editor-in-Chief's Message: Standing on
Solid Ground . . . . . . . . . . . . . . 5--6
Shane Greenstein Micro Economics: The High Cost of a
Cheap Lesson . . . . . . . . . . . . . . 7, 132--133
Ronny Ronen and
Antonio González Guest Editors' Introduction: Micro's Top
Picks from the Microarchitecture
Conferences . . . . . . . . . . . . . . 8--11
Smruti Sarangi and
Satish Narayanasamy and
Bruce Carneal and
Abhishek Tiwari and
Brad Calder and
Josep Torrellas Patching Processor Design Errors with
Programmable Hardware . . . . . . . . . 12--25
Shan Lu and
Joseph Tucek and
Feng Qin and
Yuanyuan Zhou AVIO: Detecting Atomicity Violations via
Access-Interleaving Invariants . . . . . 26--35
George A. Reis and
Jonathan Chang and
David I. August Automatic Instruction-Level
Software-Only Recovery . . . . . . . . . 36--47
Min Xu and
Rastislav Bodík and
Mark D. Hill A Hardware Memory Race Recorder for
Deterministic Replay . . . . . . . . . . 48--55
Nevin Kìrman and
Meyrem Kìrman and
Rajeev K. Dokania and
José F. Martínez and
Alyssa B. Apsel and
Matthew A. Watkins and
David H. Albonesi On-Chip Optical Technology in Future
Bus-Based Multicore Designs . . . . . . 56--66
Austen McDonald and
Brian D. Carlstrom and
JaeWoong Chung and
Chi Cao Minh and
Hassan Chafi and
Christos Kozyrakis and
Kunle Olukotun Transactional Memory: The
Hardware-Software Interface . . . . . . 67--76
Shashidhar Mysore and
Banit Agrawal and
Navin Srivastava and
Sheng-Chih Lin and
Kaustav Banerjee and
Timothy Sherwood $3$D Integration for Introspection . . . 77--83
Stijn Eyerman and
Lieven Eeckhout and
Tejas Karkhanis and
James E. Smith A Top-Down Approach to Architecting CPI
Component Performance Counters . . . . . 84--93
Hyesoon Kim and
José A. Joao and
Onur Mutlu and
Yale N. Patt Diverge-Merge Processor: Generalized and
Energy-Efficient Dynamic Predication . . 94--104
Tingting Sha and
Milo M. K. Martin and
Amir Roth NoSQ: Store-Load Communication without a
Store Queue . . . . . . . . . . . . . . 106--113
Yuan Lin and
Hyunseok Lee and
Mark Woh and
Yoav Harel and
Scott Mahlke and
Trevor Mudge and
Chaitali Chakrabarti and
Krisztián Flautner SODA: a High-Performance DSP
Architecture for Software-Defined Radio 114--123
Richard Stern Micro Law: West Coast Federal Appeals
Court Upholds Chip Protection Act
Violation Finding . . . . . . . . . . . 124--126
Richard Mateosian Micro Review: Economics . . . . . . . . 128--130
Philip Emma Micro Innovations: Reinventing
Entrepreneurial Inventing for the 21st
Century . . . . . . . . . . . . . . . . 136, 134--135
David H. Albonesi Editor in Chief's Message: Truly ``hot''
chips---Do we still care? . . . . . . . 4--5
Shane Greenstein Micro Economics: Wagging Wikipedia's
long tail . . . . . . . . . . . . . . . 6, 79
John Kubiatowicz and
Howard Sachs Guest Editors' Introduction: Hot Chips
18 . . . . . . . . . . . . . . . . . . . 7--9
Pat Conway and
Bill Hughes The AMD Opteron Northbridge Architecture 10--21
Sivakumar Radhakrishnan and
Sundaram Chinthamani and
Kai Cheng The Blackford Northbridge Chipset for
the Intel 5000 . . . . . . . . . . . . . 22--33
Bevan Baas and
Zhiyi Yu and
Michael Meeuwsen and
Omar Sattari and
Ryan Apperson and
Eric Work and
Jeremy Webb and
Michael Lai and
Tinoosh Mohsenin and
Dean Truong and
Jason Cheung AsAP: a Fine-Grained Many-Core Platform
for DSP Applications . . . . . . . . . . 34--45
John Wawrzynek and
David Patterson and
Mark Oskin and
Shih-Lien Lu and
Christoforos Kozyrakis and
James C. Hoe and
Derek Chiou and
Krste Asanovi\'c RAMP: Research Accelerator for Multiple
Processors . . . . . . . . . . . . . . . 46--57
Arjan Bink and
Richard York ARM996HS: The First Licensable,
Clockless 32-Bit Processor Core . . . . 58--68
Tse-Yu Yeh Low-Power, High-Performance Architecture
of the PWRficient Processor Family . . . 69--78
Richard Stern Micro Law: Coming down the home stretch
in the Rambus standardization
skullduggery saga: To levy or not to
levy royalties . . . . . . . . . . . . . 80--82
Richard Mateosian Micro Review: Looking Back . . . . . . . 83--85
Philip Emma Micro Innovations: Supercharging Your
Creative Skills . . . . . . . . . . . . 88, 86--87
David H. Albonesi Editor-in-Chief's Message: More Hot
Stuff . . . . . . . . . . . . . . . . . 4--5
Shane Greenstein Micro Economics: Did the Price of the
Internet Drop? . . . . . . . . . . . . . 6--7
Tim Harris and
Adrián Cristal and
Osman S. Unsal and
Eduard Ayguade and
Fabrizio Gagliardi and
Burton Smith and
Mateo Valero Transactional Memory: An Overview . . . 8--29
Gabriel H. Loh and
Yuan Xie and
Bryan Black Processor Design in $3$D Die-Stacking
Technologies . . . . . . . . . . . . . . 31--48
David Brooks and
Robert P. Dick and
Russ Joseph and
Li Shang Power, Thermal, and Reliability Modeling
in Nanometer-Scale Microprocessors . . . 49--62
Kenneth Hoste and
Lieven Eeckhout Microarchitecture-Independent Workload
Characterization . . . . . . . . . . . . 63--72
Benjamin C. Lee and
David M. Brooks Spatial Sampling and Regression
Strategies . . . . . . . . . . . . . . . 74--93
Serag GadelRab 10-Gigabit Ethernet Connectivity for
Computer Servers . . . . . . . . . . . . 94--105
Richard Stern Micro Law: Antitrust Division Gives IEEE
Standard Setters the Okay to Ask
Patentees How RAND They Are . . . . . . 106--109
Philip Emma Micro Innovations: Arcane Facts and New
Words: Expanding Your Creative Talent 112, 110--111
David H. Albonesi Editor-in-Chief's Message: Mixing It Up 3--4
Shane Greenstein Micro Economics: The 15-Billion-Dollar
Broadband Bonus . . . . . . . . . . . . 5, 58
Assaf Shacham and
Keren Bergman Building Ultralow-Latency
Interconnection Networks Using Photonic
Integration . . . . . . . . . . . . . . 6--20
Li Zhao and
Ravi Iyer and
Jaideep Moses and
Ramesh Illikkal and
Srihari Makineni and
Don Newell Exploring Large-Scale CMP Architectures
Using ManySim . . . . . . . . . . . . . 21--33
Jianwei Chen and
Michel Dubois and
Per Stenström SimWattch: Integrating Complete-System
and User-Level Performance and Power
Simulators . . . . . . . . . . . . . . . 34--48
Ivan Gonzalez and
Estanislao Aguayo and
Sergio Lopez-Buedo Self-Reconfigurable Embedded Systems on
Low-Cost FPGAs . . . . . . . . . . . . . 49--57
Richard Mateosian Micro Review: Thinking about Technology 59--61
Philip Emma Micro Innovations: Innovation or
Notoriety? . . . . . . . . . . . . . . . 64, 62--63
Partha Kundu and
Li-Shiuan Peh Guest Editors' Introduction: On-Chip
Interconnects for Multicores . . . . . . 3--5
Thomas William Ainsworth and
Timothy Mark Pinkston Characterizing the Cell EIB On-Chip
Network . . . . . . . . . . . . . . . . 6--14
David Wentzlaff and
Patrick Griffin and
Henry Hoffmann and
Liewei Bao and
Bruce Edwards and
Carl Ramey and
Matthew Mattina and
Chyi-Chang Miao and
John F. Brown III and
Anant Agarwal On-Chip Interconnection Architecture of
the Tile Processor . . . . . . . . . . . 15--31
Mike Butts Synchronization through Communication in
a Massively Parallel Processor Array . . 32--40
Paul Gratz and
Changkyu Kim and
Karthikeyan Sankaralingam and
Heather Hanson and
Premkishore Shivakumar and
Stephen W. Keckler and
Doug Burger On-Chip Interconnection Networks of the
TRIPS Chip . . . . . . . . . . . . . . . 41--50
Yatin Hoskote and
Sriram Vangal and
Arvind Singh and
Nitin Borkar and
Shekhar Borkar A 5-GHz Mesh Interconnect for a
Teraflops Processor . . . . . . . . . . 51--61
David Arditti Ilitzky and
Jeffrey D. Hoffman and
Anthony Chun and
Brando Perez Esparza Architecture of the Scalable
Communications Core's Network on Chip 62--74
Antonio Pullini and
Federico Angiolini and
Srinivasan Murali and
David Atienza and
Giovanni De Micheli and
Luca Benini Bringing NoCs to 65 nm . . . . . . . . . 75--85
Umit Y. Ogras and
Radu Marculescu and
Hyung Gyu Lee and
Puru Choudhary and
Diana Marculescu and
Michael Kaufman and
Peter Nelson Challenges and Promising Results in NoC
Prototyping Using FPGAs . . . . . . . . 86--95
John D. Owens and
William J. Dally and
Ron Ho and
D. N. (Jay) Jayasimha and
Stephen W. Keckler and
Li-Shiuan Peh Research Challenges for On-Chip
Interconnection Networks . . . . . . . . 96--108
Richard Stern Micro Law: Federal Appeals Court Sees
Potential Antitrust Violation in
Standardization Skullduggery . . . . . . 109--110
Shane Greenstein Micro Economics: Dog Days for Broadband 112, 111
David H. Albonesi Editor-in-Chief's Message: Productive
and Healthy Debate . . . . . . . . . . . 6--6
Shane Greenstein Micro Economics: Innovation at the Edges 8--10
Richard Stern Micro Law: Supreme Court to Hear
Semiconductor Chip Patent ``Exhaustion''
Case . . . . . . . . . . . . . . . . . . 11--13
Joel Emer and
Mark D. Hill and
Yale N. Patt and
Joshua J. Yi and
Derek Chiou and
Resit Sendag Single-Threaded vs. Multithreaded: Where
Should We Focus? . . . . . . . . . . . . 14--24
Shay Gueron and
Jean-Pierre Seifert and
Geoffrey Strongin and
Derek Chiou and
Resit Sendag and
Joshua J. Yi Where Does Security Stand? New
Vulnerabilities vs. Trusted Computing 25--35
Antonio González and
Scott Mahlke and
Shubu Mukherjee and
Resit Sendag and
Derek Chiou and
Joshua J. Yi Reliability: Fallacy or Reality? . . . . 36--45
Kevin Skadron and
Pradip Bose and
Kanad Ghose and
Resit Sendag and
Joshua J. Yi and
Derek Chiou Low-Power Design and Temperature
Management . . . . . . . . . . . . . . . 46--57
Richard Mateosian Micro Review: Advice for Investigators 60--61
Philip Emma Micro Innovations: You're Invited to a
Party! (How To Hold a Collaborative
IP-Development Session) . . . . . . . . 64, 62--63
Anonymous IEEE Micro 2007 Annual Index, Volume 27 i1--i12
Shane Greenstein Micro Economics: The Long Arc Behind
Bill Gates' Wealth . . . . . . . . . . . 4--7
Sarita Adve and
David Brooks and
Craig Zilles Guest Editors' Introduction: Top Picks
from the Computer Architecture
Conferences of 2007 . . . . . . . . . . 8--11
Matthew J. Bridges and
Neil Vachharajani and
Yun Zhang and
Thomas Jablin and
David I. August Revisiting the Sequential Programming
Model for the Multicore Era . . . . . . 12--20
Naveen Neelakantam and
Ravi Rajwar and
Suresh Srinivas and
Uma Srinivasan and
Craig Zilles Hardware Atomicity: An Effective
Abstraction for Reliable Software
Speculation . . . . . . . . . . . . . . 21--31
Jayaram Bobba and
Kevin E. Moore and
Haris Volos and
Luke Yen and
Mark D. Hill and
Michael M. Swift and
David A. Wood Performance Pathologies in Hardware
Transactional Memory . . . . . . . . . . 32--41
Hany E. Ramadan and
Christopher J. Rossbach and
Donald E. Porter and
Owen S. Hofmann and
Aditya Bhandari and
Emmett Witchel MetaTM/TxLinux: Transactional Memory for
an Operating System . . . . . . . . . . 42--51
Albert Meixner and
Michael E. Bauer and
Daniel J. Sorin Argus: Low-Cost, Comprehensive Error
Detection in Simple Cores . . . . . . . 52--59
Xiaoyao Liang and
Ramon Canal and
Gu-Yeon Wei and
David Brooks Replacing 6T SRAMs with 3T1D DRAMs in
the L1 Data Cache to Combat Process
Variability . . . . . . . . . . . . . . 60--68
Naveen Muralimanohar and
Rajeev Balasubramonian and
Norman P. Jouppi Architecting Efficient Interconnects for
Large Caches with CACTI 6.0 . . . . . . 69--79
Amit Kumar and
Li-Shiuan Peh and
Partha Kundu and
Niraj K. Jha Toward Ideal On-Chip Communication Using
Express Virtual Channels . . . . . . . . 80--90
Moinuddin K. Qureshi and
Aamer Jaleel and
Yale N. Patt and
Simon C. Steely, Jr. and
Joel Emer Set-Dueling-Controlled Adaptive
Insertion for High-Performance Caching 91--98
Michael R. Marty and
Mark D. Hill Virtual Hierarchies . . . . . . . . . . 99--109
Philip Emma Micro Innovations: a Collaborative
IP-Development Session . . . . . . . . . 112, 110--111
Shane Greenstein Micro Economics: The Long Arc Behind
Bill Gates' Wealth, Part 2 . . . . . . . 2--5
Raj Amirtharajah and
John Mashey Guest Editors' Introduction: Hot Chips
19 . . . . . . . . . . . . . . . . . . . 7--9
Jonathan Owen and
Maurice Steinman Northbridge Architecture of AMD's
Griffin Microprocessor Family . . . . . 10--18
Charles F. Webb IBM z10: The Next-Generation Mainframe
Microprocessor . . . . . . . . . . . . . 19--29
Kevin Reick and
Pia N. Sanda and
Scott Swaney and
Jeffrey W. Kellington and
Michael Mack and
Michael Floyd and
Daniel Henderson Fault-Tolerant Design of the IBM Power6
Microprocessor . . . . . . . . . . . . . 30--38
Erik Lindholm and
John Nickolls and
Stuart Oberman and
John Montrym NVIDIA Tesla: a Unified Graphics and
Computing Architecture . . . . . . . . . 39--55
Jeffrey M. Gilbert and
Chinh H. Doan and
Sohrab Emami and
C. Bernard Shung A 4-Gbps Uncompressed Wireless HD A/V
Transceiver Chipset . . . . . . . . . . 56--64
Richard Stern Micro Law: FTC Sues N-Data for Violating
Standards Commitment to IEEE . . . . . . 66--69
Richard Mateosian Micro Review: The Paradigms, They Are
A-Changin' . . . . . . . . . . . . . . . 72, 70--71
Sangyeun Cho and
Tao Li and
Onur Mutlu Guest Editors' Introduction: Interaction
of Many-Core Computer Architecture and
Operating Systems . . . . . . . . . . . 2--5
Kyle J. Nesbit and
Miquel Moreto and
Francisco J. Cazorla and
Alex Ramirez and
Mateo Valero and
James E. Smith Multicore Resource Management . . . . . 6--16
Fred A. Bower and
Daniel J. Sorin and
Landon P. Cox The Impact of Dynamically Heterogeneous
Multicore Processors on Thread
Scheduling . . . . . . . . . . . . . . . 17--25
Jeffrey C. Mogul and
Jayaram Mudigonda and
Nathan Binkert and
Parthasarathy Ranganathan and
Vanish Talwar Using Asymmetric Single-ISA CMPs to Save
Energy on Operating Systems . . . . . . 26--41
Stijn Eyerman and
Lieven Eeckhout System-Level Performance Metrics for
Multiprogram Workloads . . . . . . . . . 42--53
Rob Knauerhase and
Paul Brett and
Barbara Hohlt and
Tong Li and
Scott Hahn Using OS Observations to Improve
Performance in Multicore Systems . . . . 54--66
Richard Stern Micro Law: AAI Asks FTC to Investigate
RAND Issues Concerning Digital TV
Standard . . . . . . . . . . . . . . . . 72, 70--71
Shane Greenstein Micro Economics: Voting and Economic
Asymmetry . . . . . . . . . . . . . . . 2--3
Sanjay Patel and
Wen-mei W. Hwu Accelerator Architectures . . . . . . . 4--12
Michael Garland and
Scott Le Grand and
John Nickolls and
Joshua Anderson and
Jim Hardwick and
Scott Morton and
Everett Phillips and
Yao Zhang and
Vasily Volkov Parallel Computing Experiences with CUDA 13--27
Dong Hyuk Woo and
Hsien-Hsin S. Lee and
Joshua B. Fryman and
Allan D. Knies and
Marsha Eng POD: a $3$D-Integrated Broad-Purpose
Acceleration Layer . . . . . . . . . . . 28--40
Bruno Bougard and
Bjorn De Sutter and
Diederik Verkest and
Liesbet Van der Perre and
Rudy Lauwereins A Coarse-Grained Array Accelerator for
Software-Defined Radio Baseband
Processing . . . . . . . . . . . . . . . 41--50
Mei Wen and
Nan Wu and
Chunyuan Zhang and
Qianming Yang and
Jun Ren and
Yi He and
Wei Wu and
Jun Chai and
Maolin Guan and
Changqing Xun On-Chip Memory System Optimization
Design for the FT64 Scientific Stream
Accelerator . . . . . . . . . . . . . . 51--70
Zhanpeng Jin and
Allen C. Cheng ImplantBench: Characterizing and
Projecting Representative Benchmarks for
Emerging Bioimplantable Computing . . . 71--91
Richard Stern Micro Law: What Kinds of
Computer-Software-Related Advances (if
Any) Are Eligible for Patents? Part I 96, 91--95
David H. Albonesi From the Editor in Chief: Changes Ahead 4--4
Shane Greenstein Micro Economics: Slouching Toward a
Dystopian Internet . . . . . . . . . . . 6--7
Eric Li and
Wenlong Li and
Xiaofeng Tong and
Jianguo Li and
Yurong Chen and
Tao Wang and
Patricia P. Wang and
Wei Hu and
Yangzhou Du and
Yimin Zhang and
Yen-Kuang Chen Accelerating Video-Mining Applications
Using Many Small, General-Purpose Cores 8--21
Avinash Karanth Kodi and
Ahmed Louri Optisim: a System Simulation Methodology
for Optically Interconnected HPC Systems 22--36
Shubhajit Roy Chowdhury and
Hiranmay Saha A High-Performance FPGA-Based Fuzzy
Processor Architecture for Medical
Diagnosis . . . . . . . . . . . . . . . 38--52
Junji Sakai and
Inoue Hiroaki and
Sunao Torii and
Masato Edahiro Multitasking Parallel Method for
High-End Embedded Appliances . . . . . . 54--62
Richard Stern Micro Law: What Kinds of
Computer-Software-Related Advances (if
Any) Are Eligible for Patents? Part II:
The ``Useful Arts'' Requirement . . . . 64--70
Richard Mateosian Micro Review: Software Development
Patterns . . . . . . . . . . . . . . . . 72, 71
Shane Greenstein Micro Economics: Chicken Little
Predictions . . . . . . . . . . . . . . 2--3
Philip G. Emma Guest Editor's Introduction: Existential
Architectures: The Metaphysics of
Computer Design . . . . . . . . . . . . 4--6
Constantin Pistol and
Chris Dwyer and
Alvin R. Lebeck Nanoscale Optical Computing Using
Resonance Energy Transfer Logic . . . . 7--18
Zhanpeng Jin and
Allen C. Cheng Evolutionary Benchmark Subsetting . . . 20--36
Jaume Abella and
Xavier Vera and
Osman S. Unsal and
Oguz Ergin and
Antonio González and
James W. Tschanz Refueling: Preventing Wire Degradation
due to Electromigration . . . . . . . . 37--46
Philip G. Emma and
William R. Reohr and
Mesut Meterelliyoz Rethinking Refresh: Increasing
Availability and Reducing Power in DRAM
for Cache Applications . . . . . . . . . 47--56
Richard Stern Micro Law: An Update on
``Exhaustion''---Supreme Court Decides
Quanta Case . . . . . . . . . . . . . . 57--54
Richard Stern Micro News . . . . . . . . . . . . . . . 64--64
Anonymous Annual Index . . . . . . . . . . . . . . 0--0
Shane Greenstein Micro Economics: Symptoms of Healthy
Innovativeness . . . . . . . . . . . . . 3--5
Joel Emer and
Dean Tullsen Top Picks from the 2008 Computer
Architecture Conferences . . . . . . . . 6--9
Larry Seiler and
Doug Carmean and
Eric Sprangle and
Tom Forsyth and
Pradeep Dubey and
Stephen Junkins and
Adam Lake and
Robert Cavin and
Roger Espasa and
Ed Grochowski and
Toni Juan and
Michael Abrash and
Jeremy Sugerman and
Pat Hanrahan Larrabee: a Many-Core x86 Architecture
for Visual Computing . . . . . . . . . . 10--21
Onur Mutlu and
Thomas Moscibroda Parallelism-Aware Batch Scheduling:
Enabling High-Performance and Fair
Shared Memory Controllers . . . . . . . 22--32
John Kim and
William Dally and
Steve Scott and
Dennis Abts Cost-Efficient Dragonfly Topology for
Large-Scale Systems . . . . . . . . . . 33--40
Kevin Lim and
Parthasarathy Ranganathan and
Jichuan Chang and
Chandrakant Patel and
Trevor Mudge and
Steven K. Reinhardt Server Designs for Warehouse-Computing
Environments . . . . . . . . . . . . . . 41--49
Sudhanva Gurumurthi and
Sriram Sankar and
Mircea R. Stan Using Intradisk Parallelism to Build
Energy-Efficient Storage Systems . . . . 50--61
Shimin Chen and
Michael Kozuch and
Phillip B. Gibbons and
Michael Ryan and
Theodoros Strigkos and
Todd C. Mowry and
Olatunji Ruwase and
Evangelos Vlachos and
Babak Falsafi and
Vijaya Ramachandran Flexible Hardware Acceleration for
Instruction-Grain Lifeguards . . . . . . 62--72
Brandon Lucia and
Joseph Devietti and
Luis Ceze and
Karin Strauss Atom-Aid: Detecting and Surviving
Atomicity Violations . . . . . . . . . . 73--83
James Tuck and
Wonsun Ahn and
Josep Torrellas and
Luis Ceze SoftSig: Software-Exposed Hardware
Signatures for Code Analysis and
Optimization . . . . . . . . . . . . . . 84--95
Chris Wilkerson and
Hongliang Gao and
Alaa R. Alameldeen and
Zeshan Chishti and
Muhammad Khellah and
Shih-Lien Lu Trading Off Cache Capacity for
Low-Voltage Operation . . . . . . . . . 96--103
Renée St. Amant and
Daniel A. Jiménez and
Doug Burger Mixed-Signal Approximate Computation: a
Neural Predictor Case Study . . . . . . 104--115
Eren Kursun and
Chen-Yong Cher Temperature Variation Characterization
and Thermal Management of Multicore
Architectures . . . . . . . . . . . . . 116--126
Xiaoyao Liang and
Gu-Yeon Wei and
David Brooks Revival: a Variation-Tolerant
Architecture Using Voltage Interpolation
and Variable Latency . . . . . . . . . . 127--138
Richard H. Stern Micro Law: One of the Last Updates on
Rambus Standardization Skullduggery . . 139--143
Richard Mateosian Micro Review: System Green . . . . . . . 144--147
Shane Greenstein Micro Economics: Building Broadband as
Economic Stimulus . . . . . . . . . . . 2--3
Christos Kozyrakis and
Jan-Willem van de Waerdt Hot Chips Turns 20 . . . . . . . . . . . 4--5
Shailender Chaudhry and
Robert Cypher and
Magnus Ekman and
Martin Karlsson and
Anders Landin and
Sherman Yip and
Håkan Zeffer and
Marc Tremblay Rock: a High-Performance SPARC CMT
Processor . . . . . . . . . . . . . . . 6--16
Weiwu Hu and
Jian Wang and
Xiang Gao and
Yunji Chen and
Qi Liu and
Guojie Li Godson-3: a Scalable Multicore RISC
Processor with x86 Emulation . . . . . . 17--29
Richard Selvaggi and
Larry Pearlstein Broadcom mediaDSP: a Platform for
Building Programmable Multicore Video
Processors . . . . . . . . . . . . . . . 30--45
Dan Mansur A New 40-nm FPGA and ASIC Common
Platform . . . . . . . . . . . . . . . . 46--53
Lloyd Watts and
Dana Massie and
Allen Sansano and
Jim Huey Voice Processors Based on the Human
Hearing System . . . . . . . . . . . . . 54--63
Richard Stern Micro Law: IEEE-USA Tells Congress that
Patent Reform Is Essential to Economic
Recovery . . . . . . . . . . . . . . . . 64--65
Richard Mateosian Micro Review: No More Wishful Thinking 68--71
Anonymous Advert . . . . . . . . . . . . . . . . . 1--1
Shane Greenstein Micro Economics: The Revolution in
Spectrum Allocation . . . . . . . . . . 4--6
Markus Levy and
Thomas M. Conte Embedded Multicore Processors and
Systems . . . . . . . . . . . . . . . . 7--9
Thomas B. Berg Maintaining I/O Data Coherence in
Embedded Multicore Systems . . . . . . . 10--19
Jiang Xu and
Wayne Wolf and
Wei Zhang Double-Data-Rate, Wave-Pipelined
Interconnect for Asynchronous NoCs . . . 20--30
Jean-Yves Mignolet and
Rogier Baert and
Thomas J. Ashby and
Prabhat Avasare and
Hye-On Jang and
Jae Cheol Son MPA: Parallelizing an Application onto a
Multicore Platform Made Easy . . . . . . 31--39
Jim Holt and
Anant Agarwal and
Sven Brehmer and
Max Domeika and
Patrick Griffin and
Frank Schirrmeister Software Standards for the Multicore Era 40--51
Feng Wang and
Mounir Hamdi Memory Subsystems in High-End Routers 52--63
Richard Mateosian Micro Review: Software Architects . . . 62--64
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Shane Greenstein Micro Economics: Soccer Mom Messaging Is
the Poetry of Our Age . . . . . . . . . 2--3
Anonymous Call for Papers . . . . . . . . . . . . 4--4
Keren Bergman and
Ron Brightwell and
Fabrizio Petrini Guest Editors' Introduction: Hot
Interconnects . . . . . . . . . . . . . 5--7
Christopher Batten and
Ajay Joshi and
Jason Orcutt and
Anatol Khilo and
Benjamin Moss and
Charles W. Holzwarth and
Milo\vs A. Popovi\'c and
Hanqing Li and
Henry I. Smith and
Judy L. Hoyt and
Franz X. Kärtner and
Rajeev J. Ram and
Vladimir Stojanovi\'c and
Krste Asanovi\'c Building Many-Core Processor-to-DRAM
Networks with Monolithic CMOS Silicon
Photonics . . . . . . . . . . . . . . . 8--21
Nikos Chrysos and
Giorgos Dimitrakopoulos Practical High-Throughput Crossbar
Scheduling . . . . . . . . . . . . . . . 22--35
John Feehrer and
Paul Rotker and
Milton Shih and
Paul Gingras and
Peter Yakutis and
Stephen Phillips and
John Heath Coherency Hub Design for Multisocket Sun
Servers with CoolThreads Technology . . 36--47
Tushar Krishna and
Amit Kumar and
Li-Shiuan Peh and
Jacob Postman and
Patrick Chiang and
Mattan Erez Express Virtual Channels with
Capacitively Driven Global Links . . . . 48--61
Michael R. T. Tan and
Paul Rosenberg and
Jong-Souk Yeo and
Moray McLaren and
Sagi Mathai and
Terry Morris and
Huei Pei Kuo and
Joseph Straznicky and
Norman P. Jouppi and
Shih-Yuan Wang A High-Speed Optical Multidrop Bus for
Computer Interconnections . . . . . . . 62--73
Michele Petracca and
Benjamin G. Lee and
Keren Bergman and
Luca P. Carloni Photonic NoCs: System-Level Design
Exploration . . . . . . . . . . . . . . 74--85
Richard H. Stern Micro Law: An End to the Rambus
Skullduggery Saga . . . . . . . . . . . 86--86
Richard Mateosian Micro Review: Twitter . . . . . . . . . 87--88
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
David H. Albonesi From the Editor in Chief: Welcome
A-Board . . . . . . . . . . . . . . . . 2--5
Shane Greenstein Micro Economics: Does Google Have Too
Much Money? . . . . . . . . . . . . . . 6--7
José F. Martínez and
Engin \.Ipek Dynamic Multicore Resource Management: a
Machine Learning Approach . . . . . . . 8--17
Jason A. Poovey and
Thomas M. Conte and
Markus Levy and
Shay Gal-On A Benchmark Characterization of the
EEMBC Benchmark Suite . . . . . . . . . 18--29
Tran Nguyen Bao Anh and
Su-Lim Tan Real-Time Operating Systems for Small
Microcontrollers . . . . . . . . . . . . 30--45
Hsiang-Ning Liu and
Yu-Jen Huang and
Jin-Fu Li Memory Built-in Self Test in Multicore
Chips with Mesh-Based Networks . . . . . 46--55
Ying-Dar Lin and
Po-Ching Lin and
Yuan-Cheng Lai and
Tai-Ying Liu Hardware-Software Codesign for
High-Speed Signature-based Virus
Scanning . . . . . . . . . . . . . . . . 56--65
Richard Mateosian Micro Review: Life and Work . . . . . . 66--68
Shane Greenstein Micro Economics: a Network of Platforms 2--3
Anonymous Erratum . . . . . . . . . . . . . . . . 4--4
Makoto Ikeda and
Fumio Arakawa Guest Editors' Introduction: Cool Chips 5--6
Tohru Nojiri and
Yuki Kondo and
Naohiko Irie and
Masayuki Ito and
Hajime Sasaki and
Hideo Maejima Domain Partitioning Technology for
Embedded Multicore Processors . . . . . 7--17
Motoki Kimura and
Kenichi Iwata and
Seiji Mochizuki and
Hiroshi Ueda and
Masakazu Ehama and
Hiromi Watanabe A Full HD Multistandard Video Codec for
Mobile Applications . . . . . . . . . . 18--27
Joo-Young Kim and
Minsu Kim and
Seungjin Lee and
Jinwook Oh and
Sejong Oh and
Hoi-Jun Yoo Real-Time Object Recognition with
Neuro-Fuzzy Controlled Workload-Aware
Task Pipelining . . . . . . . . . . . . 28--43
Yuichi Hori and
Yuya Hanai and
Jun Nishimura and
Tadahiro Kuroda Architecture Design of Versatile
Recognition Processor for Sensornet
Applications . . . . . . . . . . . . . . 44--57
Takashi Komuro and
Atsushi Iwashita and
Masatoshi Ishikawa A QVGA-Size Pixel-Parallel Image
Processor for 1,000-fps Vision . . . . . 58--67
Sudhanva Gurumurthi Prolegomena: Architecting Storage for
the Cloud Computing Era . . . . . . . . 68--71
Richard Stern Micro Law: All Bilski Briefs Filed and
Case Set for Oral Argument . . . . . . . 72--72
Anonymous Annual Index . . . . . . . . . . . . . . 1--1
Anonymous Call for Applications for Editor in
Chief . . . . . . . . . . . . . . . . . 3--3
Shane Greenstein Micro Economics: The Next Chapter at
Google . . . . . . . . . . . . . . . . . 4--7
Trevor Mudge Guest Editor's Introduction: Top Picks
from the Computer Architecture
Conferences of 2009 . . . . . . . . . . 8--11
Andrew Hilton and
Santosh Nagarakatte and
Amir Roth iCFP: Tolerating All-Level Cache Misses
in In-Order Processors . . . . . . . . . 12--19
Nikos Hardavellas and
Michael Ferdman and
Babak Falsafi and
Anastasia Ailamaki Near-Optimal Cache Block Placement with
Reactive Nonuniform Cache Architectures 29--29
John H. Kelm and
Daniel R. Johnson and
Steven S. Lumetta and
Sanjay J. Patel and
Matthew I. Frank A Task-Centric Memory Model for Scalable
Accelerator Architectures . . . . . . . 29--39
Joseph Devietti and
Brandon Lucia and
Luis Ceze and
Mark Oskin DMP: Deterministic Shared-Memory
Multiprocessing . . . . . . . . . . . . 40--49
Thomas F. Wenisch and
Michael Ferdman and
Anastasia Ailamaki and
Babak Falsafi and
Andreas Moshovos Making Address-Correlated Prefetching
Practical . . . . . . . . . . . . . . . 50--59
M. Aater Suleman and
Onur Mutlu and
Moinuddin K. Qureshi and
Yale N. Patt Accelerating Critical Section Execution
with Asymmetric Multicore Architectures 60--70
Stijn Eyerman and
Lieven Eeckhout Per-Thread Cycle Accounting . . . . . . 71--80
Mark Woh and
Sangwon Seo and
Scott Mahlke and
Trevor Mudge and
Chaitali Chakrabarti and
Krisztián Flautner AnySP: Anytime Anywhere Anyway Signal
Processing . . . . . . . . . . . . . . . 81--91
Mohit Tiwari and
Xun Li and
Hassan M. G. Wassel and
Bita Mazloom and
Shashidhar Mysore and
Frederic T. Chong and
Timothy Sherwood Gate-Level Information-Flow Tracking for
Secure Architectures . . . . . . . . . . 92--100
Vijay Janapa Reddi and
Meeta Gupta and
Glenn Holloway and
Michael D. Smith and
Gu-Yeon Wei and
David Brooks Predicting Voltage Droops Using
Recurring Program and Microarchitectural
Event Activity . . . . . . . . . . . . . 110--110
Constantin Pistol and
Wutichai Chongchitmate and
Christopher Dwyer and
Alvin R. Lebeck Architectural Implications of
Nanoscale-Integrated Sensing and
Computing . . . . . . . . . . . . . . . 110--120
Adrian M. Caulfield and
Laura M. Grupp and
Steven Swanson Gordon: An Improved Architecture for
Data-Intensive Applications . . . . . . 121--130
Benjamin C. Lee and
Ping Zhou and
Jun Yang and
Youtao Zhang and
Bo Zhao and
Engin Ipek and
Onur Mutlu and
Doug Burger Phase-Change Technology and the Future
of Main Memory . . . . . . . . . . . . . 143--143
Richard Mateosian Micro Review: Technical Writing . . . . 144--147
Shane Greenstein Micro Economics: Bleeding-Edge Mass
Market Standards . . . . . . . . . . . . 2--4
Krste Asanovi\'c and
Ralph Wittig Guest Editors' Introduction: Hot Chips
21 . . . . . . . . . . . . . . . . . . . 5--6
Ron Kalla and
Balaram Sinharoy and
William J. Starke and
Michael Floyd Power7: IBM's Next-Generation Server
Processor . . . . . . . . . . . . . . . 7--15
Pat Conway and
Nathan Kalyanasundharam and
Gregg Donley and
Kevin Lepak and
Bill Hughes Cache Hierarchy and Memory Subsystem of
the AMD Opteron Processor . . . . . . . 16--29
Takumi Maruyama and
Toshio Yoshida and
Ryuji Kan and
Iwao Yamazaki and
Shuji Yamamura and
Noriyuki Takahashi and
Mikio Hondou and
Hiroshi Okano Sparc64 VIIIfx: a New-Generation
Octocore Processor for Petascale
Computing . . . . . . . . . . . . . . . 30--40
Bryan Catanzaro and
Armando Fox and
Kurt Keutzer and
David Patterson and
Bor-Yiing Su and
Marc Snir and
Kunle Olukotun and
Pat Hanrahan and
Hassan Chafi Ubiquitous Parallel Computing from
Berkeley, Illinois, and Stanford . . . . 41--55
John Nickolls and
William J. Dally The GPU Computing Era . . . . . . . . . 56--69
Tony M. Brewer Instruction Set Innovations for the
Convey HC-1 Computer . . . . . . . . . . 70--79
Sassan Tabatabaei and
Aaron Partridge Silicon MEMS Oscillators for High-Speed
Digital Systems . . . . . . . . . . . . 80--89
Richard Mateosian Micro Review: Designing for Discovery 90--92
David H. Albonesi From the Editor in Chief: Future
Directions in Computer Architecture
Research . . . . . . . . . . . . . . . . 5--5
Shane Greenstein Micro Economics: Standardization and
Coordination . . . . . . . . . . . . . . 6--7
James C. Hoe and
Doug Burger and
Joel Emer and
Derek Chiou and
Resit Sendag and
Joshua Yi The Future of Architectural Simulation 8--18
Arvind and
David August and
Keshav Pingali and
Derek Chiou and
Resit Sendag and
Joshua J. Yi Programming Multicores: Do Applications
Programmers Need to Write Explicitly
Parallel Programs? . . . . . . . . . . . 19--33
Elliott Cooper-Balis and
Bruce Jacob Fine-Grained Activation for Power
Reduction in DRAM . . . . . . . . . . . 34--47
Hyesook Lim and
So Yeon Kim Tuple Pruning Using Bloom Filters for
Packet Classification . . . . . . . . . 48--59
Gabriel H. Loh and
Yuan Xie Prolegomena: $3$D Stacked
Microprocessor: Are We There Yet? . . . 60--64
Shane Greenstein Digitization and Value Creation . . . . 4--5
Luiz Andre Barroso and
Parthasarathy Ranganathan Guest Editors' Introduction:
Datacenter-Scale Computing . . . . . . . 6--7
Christos Kozyrakis and
Aman Kansal and
Sriram Sankar and
Kushagra Vaid Server Engineering Insights for
Large-Scale Online Services . . . . . . 8--19
Trevor Mudge and
Urs Holzle Challenges and Opportunities for
Extremely Energy-Efficient Processors 20--24
Jose E. Moreira and
John Karidis The Case for Full-Throttle Computing: An
Alternative Datacenter Design Strategy 25--28
Amin Vahdat and
Mohammad Al-Fares and
Nathan Farrington and
Radhika Niranjan Mysore and
George Porter and
Sivasankar Radhakrishnan Scale-Out Networking in the Data Center 29--41
Sven-Arne Reinemo and
Tor Skeie and
Manoj K. Wadekar Ethernet for High-Performance Data
centers: On the New IEEE Datacenter
Bridging Standards . . . . . . . . . . . 42--51
David G. Andersen and
Steven Swanson Rethinking Flash in the Data Center . . 52--54
Peng Wang and
Dan Meng and
Jizhong Han and
Jianfeng Zhan and
Bibo Tu and
Xiaofeng Shi and
Le Wan Transformer: a New Paradigm for Building
Data-Parallel Programming Models . . . . 55--64
Gang Ren and
Eric Tune and
Tipp Moseley and
Yixin Shi and
Silvius Rus and
Robert Hundt Google-Wide Profiling: a Continuous
Profiling Infrastructure for Data
Centers . . . . . . . . . . . . . . . . 65--79
Benton H. Calhoun and
David Brooks Can Subthreshold and Near-Threshold
Circuits Go Mainstream? . . . . . . . . 80--85
Richard Mateosian Micro Review: Miscellany . . . . . . . . 86--88
Anonymous Masthead . . . . . . . . . . . . . . . . 3--4
Mateo Valero and
Nacho Navarro Multicore: The View from Europe . . . . 2--4
Veerle Desmet and
Sylvain Girbal and
Alex Ramirez and
Augusto Vega and
Olivier Temam ArchExplorer for Automatic Design Space
Exploration . . . . . . . . . . . . . . 5--15
Alex Ramirez and
Felipe Cabarcas and
Ben Juurlink and
Mauricio Alvarez Mesa and
Friman Sanchez and
Arnaldo Azevedo and
Cor Meenderinck and
Catalin Ciobanu and
Sebastian Isaza and
Georgi Gaydadjiev The SARC Architecture . . . . . . . . . 16--29
Manolis Katevenis and
Vassilis Papaefstathiou and
Stamatis Kavadias and
Dionisios Pnevmatikatos and
Federico Silla and
Dimitrios Nikolopoulos Explicit Communication and
Synchronization in SARC . . . . . . . . 30--41
SARC European Project Parallel Programming Models for
Heterogeneous Multicore Architectures 42--53
Stefanos Kaxiras and
Georgios Keramidas SARC Coherence: Scaling Directory Cache
Coherence in Performance and Power . . . 54--65
Theo Ungerer and
Francisco Cazorla and
Pascal Sainrat and
Guillem Bernat and
Zlatko Petrov and
Christine Rochange and
Eduardo Quinones and
Mike Gerdes and
Marco Paolieri and
Julian Wolf and
Hugues Casse and
Sascha Uhrig and
Irakli Guliashvili and
Michael Houston and
Floria Kluge and
Stefan Metzlaff and
Jorg Mische Merasa: Multicore Execution of Hard
Real-Time Applications Supporting
Analyzability . . . . . . . . . . . . . 66--75
Yehuda Afek and
Ulrich Drepper and
Pascal Felber and
Christof Fetzer and
Vincent Gramoli and
Michael Hohmuth and
Etienne Riviere and
Per Stenstrom and
Osman Unsal and
Walther Maldonado Moreira and
Derin Harmanci and
Patrick Marlier and
Stephan Diestelhorst and
Martin Pohlack and
Adrian Cristal and
Ibrahim Hur and
Aleksandar Dragojevic and
Rachid Guerraoui and
Michal Kapalka and
Sasa Tomic and
Guy Korland and
Nir Shavit and
Martin Nowack and
Torvald Riegel The Velox Transactional Memory Stack . . 76--87
Koen Bertels and
Vlad-Mihai Sima and
Yana Yankova and
Georgi Kuzmanov and
Wayne Luk and
Gabriel Coutinho and
Fabrizio Ferrandi and
Christian Pilato and
Marco Lattuada and
Donatella Sciuto and
Andrea Michelotti HArtes: Hardware-Software Codesign for
Heterogeneous Multicore Platforms . . . 88--97
Anonymous European Multicore Processing Projects 98--101
Shane Greenstein Gatekeeping Economics . . . . . . . . . 102--104
Anonymous Call for Papers . . . . . . . . . . . . 1--1
Anonymous Masthead . . . . . . . . . . . . . . . . 3--3
David H. Albonesi Moving Forward . . . . . . . . . . . . . 4--5
Shane Greenstein Building Broadband Ahead of Digital
Demand . . . . . . . . . . . . . . . . . 6--8
Ofer Shacham and
Omid Azizi and
Megan Wachs and
Stephen Richardson and
Mark Horowitz Rethinking Digital Design: Why Design
Must Change . . . . . . . . . . . . . . 9--24
Christopher Hughes and
Changkyu Kim and
Yen-Kuang Chen Performance and Energy Implications of
Many-Core Caches for Throughput
Computing . . . . . . . . . . . . . . . 25--35
Amin Ansari and
Shuguang Feng and
Shantanu Gupta and
Scott Mahlke Putting Faulty Cores to Work . . . . . . 36--45
Frederick Ryckbosch and
Stijn Polfliet and
Lieven Eeckhout Fast, Accurate, and Validated
Full-System Software Simulation of x86
Hardware . . . . . . . . . . . . . . . . 46--56
Luk Van Ertvelde and
Lieven Eeckhout Workload Reduction and Generation
Techniques . . . . . . . . . . . . . . . 57--65
Roberto Airoldi and
Omer Anjum and
Fabio Garzia and
Alexander Wyglinski and
Jari Nurmi Energy-Efficient Fast Fourier Transforms
for Cognitive Radio Systems . . . . . . 66--76
Richard Mateosian Being Geek . . . . . . . . . . . . . . . 78--78
Anonymous Masthead . . . . . . . . . . . . . . . . 3--3
Erik R. Altman A Solid Past, a Vital Future . . . . . . 4--5
Yale N. Patt and
Onur Mutlu Top Picks . . . . . . . . . . . . . . . 6--10
Doe Hyun Yoon and
Mattan Erez Virtualized ECC: Flexible Reliability in
Main Memory . . . . . . . . . . . . . . 11--19
Vijay Janapa Reddi and
Svilen Kanev and
Wonyoung Kim and
Simone Campanoni and
Michael D. Smith and
Gu-Yeon Wei and
David Brooks Voltage Noise in Production Processors 20--28
Reetuparna Das and
Onur Mutlu and
Thomas Moscibroda and
Chita R. Das Aérgia: a Network-on-Chip Exploiting
Packet Latency Slack . . . . . . . . . . 29--41
John H. Kelm and
Daniel R. Johnson and
William Tuohy and
Steven S. Lumetta and
Sanjay J. Patel Cohesion: An Adaptive Hybrid Memory
Model for Accelerators . . . . . . . . . 42--55
M. Aater Suleman and
Onur Mutlu and
Jose A. Joao and
Khubaib and
Yale Patt Data Marshaling for Multicore Systems 56--64
Matthew A. Watkins and
David H. Albonesi ReMAP: a Reconfigurable Architecture for
Chip Multiprocessors . . . . . . . . . . 65--77
Yoongu Kim and
Michael Papamichael and
Onur Mutlu and
Mor Harchol-Balter Thread Cluster Memory Scheduling . . . . 78--89
Jeffrey Stuecheli and
Dimitris Kaseridis and
Lizy K. John and
David Daly and
Hillery C. Hunter Coordinating DRAM and Last-Level-Cache
Policies with the Virtual Write Queue 90--98
Xiaowei Jiang and
Niti Madan and
Li Zhao and
Mike Upton and
Ravi Iyer and
Srihari Makineni and
Donald Newell and
Yan Solihin and
Rajeev Balasubramonian CHOP: Integrating DRAM Caches for CMP
Server Platforms . . . . . . . . . . . . 99--108
Bogdan F. Romanescu and
Alvin R. Lebeck and
Daniel J. Sorin Address Translation Aware Memory
Consistency . . . . . . . . . . . . . . 109--118
Nak Hee Seong and
Dong Hyuk Woo and
Hsien-Hsin S. Lee Security Refresh: Protecting
Phase-Change Memory against Malicious
Wear Out . . . . . . . . . . . . . . . . 119--127
Shane Greenstein Digital Dark Matter . . . . . . . . . . 128--128
Erik R. Altman Hot Chips and Remembering a Pioneer . . 3--3
Jose Renau and
Will Eatherton Hot Chips 22 . . . . . . . . . . . . . . 4--5
Michael Butler and
Leslie Barnes and
Debjit Das Sarma and
Bob Gelinas Bulldozer: An Approach to Multithreaded
Compute Performance . . . . . . . . . . 6--15
Brad Burgess and
Brad Cohen and
Marvin Denman and
Jim Dundas and
David Kaplan and
Jeff Rupley Bobcat: AMD's Low-Power x86 Processor 16--25
Brian W. Curran and
Lee E. Eisen and
Eric M. Schwarz and
Pak-kin Mak and
James Warnock and
Patrick J. Meaney and
Michael Fee The zEnterprise 196 System and
Microprocessor . . . . . . . . . . . . . 26--40
Olav Lindtjorn and
Robert Clapp and
Oliver Pell and
Haohuan Fu and
Michael Flynn and
Oskar Mencer Beyond Traditional Microprocessors for
Geoscience High-Performance Computing
Applications . . . . . . . . . . . . . . 41--49
Craig M. Wittenbrink and
Emmett Kilgariff and
Arjun Prabhu Fermi GF100 GPU Architecture . . . . . . 50--59
Michael Floyd and
Malcolm Allen-Ware and
Karthick Rajamani and
Bishop Brock and
Charles Lefurgy and
Alan J. Drake and
Lorena Pesantez and
Tilman Gloekler and
Jose A. Tierno and
Pradip Bose and
Alper Buyuktosunoglu Introducing the Adaptive Energy
Management Features of the Power7 Chip 60--75
Jeffrey D. Brown and
Sandra Woodward and
Brian M. Bass and
Charles L. Johnson IBM Power Edge of Network Processor: a
Wire-Speed System on a Chip . . . . . . 76--85
Nathan Goulding-Hotta and
Jack Sampson and
Ganesh Venkatesh and
Saturnino Garcia and
Joe Auricchio and
Po-Chao Huang and
Manish Arora and
Siddhartha Nath and
Vikram Bhatt and
Jonathan Babb and
Steven Swanson and
Michael Bedford Taylor The GreenDroid Mobile Application
Processor: An Architecture for Silicon's
Dark Future . . . . . . . . . . . . . . 86--95
Richard H. Stern Standardization Skullduggery Revisited 96--99
Richard Mateosian Technology . . . . . . . . . . . . . . . 100--102
Shane Greenstein The Direction of Broadband Spillovers 104, 103
Erik R. Altman Very Large-Scale Systems and Some
History . . . . . . . . . . . . . . . . 2--3
Natalie Enright Jerger and
Mikko Lipasti Systems for Very Large-Scale Computing 4--7
Ron O. Dror and
J. P. Grossman and
Kenneth M. Mackenzie and
Brian Towles and
Edmond Chow and
John K. Salmon and
Cliff Young and
Joseph A. Bank and
Brannon Batson and
Martin M. Deneroff and
Jeffrey S. Kuskin and
Richard H. Larson and
Mark A. Moraes and
David E. Shaw Overcoming Communication Latency
Barriers in Massively Parallel
Scientific Computation . . . . . . . . . 8--19
Ravi Iyer and
Sadagopan Srinivasan and
Omesh Tickoo and
Zhen Fang and
Ramesh Illikkal and
Steven Zhang and
Vineet Chadha and
Paul M. Stillwell, Jr. and
Seung Eun Lee CogniServe: Heterogeneous Server
Architecture for Large-Scale Recognition 20--31
Juan Gonzalez and
Judit Gimenez and
Marc Casas and
Miquel Moreto and
Alex Ramirez and
Jesus Labarta and
Mateo Valero Simulating Whole Supercomputer
Applications . . . . . . . . . . . . . . 32--45
Stijn Polfliet and
Frederick Ryckbosch and
Lieven Eeckhout Automated Full-System Power
Characterization . . . . . . . . . . . . 46--59
Victor Jimenez and
Roberto Gioiosa and
Francisco J. Cazorla and
Mateo Valero and
Eren Kursun and
Canturk Isci and
Alper Buyuktosunoglu and
Pradip Bose Energy-Aware Accounting and Billing in
Large-Scale Computing Facilities . . . . 60--71
Enrico Bini and
Giorgio Buttazzo and
Johan Eker and
Stefan Schorr and
Raphael Guerra and
Gerhard Fohler and
Karl-Erik Arzen and
Vanessa Romero Segovia and
Claudio Scordino Resource Management on Multicore
Systems: The ACTORS Approach . . . . . . 72--81
Wei Huang and
Malcolm Allen-Ware and
John B. Carter and
Mircea R. Stan and
Kevin Skadron and
Edmund Cheng Temperature-Aware Architecture: Lessons
and Opportunities . . . . . . . . . . . 82--86
Shane Greenstein The Open Internet Order . . . . . . . . 88, 87
Erik R. Altman From the Editor-in-Chief: Big Chips and
Beyond . . . . . . . . . . . . . . . . . 2--2
Andrew B. Kahng and
Vijayalakshmi Srinivasan Big Chips . . . . . . . . . . . . . . . 3--5
Nikos Hardavellas and
Michael Ferdman and
Babak Falsafi and
Anastasia Ailamaki Toward Dark Silicon in Servers . . . . . 6--15
Wei Huang and
Karthick Rajamani and
Mircea R. Stan and
Kevin Skadron Scaling with Design Constraints:
Predicting the Future of Big Chips . . . 16--29
Daniel R. Johnson and
Matthew R. Johnson and
John H. Kelm and
William Tuohy and
Steven S. Lumetta and
Sanjay J. Patel Rigel: a 1,024-Core Single-Chip
Accelerator Architecture . . . . . . . . 30--41
Junli Gu and
Yihe Sun and
Steven S. Lumetta and
Rakeshh Kumar MOPED: Accelerating Data Communication
on Future CMPs . . . . . . . . . . . . . 42--50
David Papa and
Natarajan Viswanathan and
Cliff Sze and
Zhuo Li and
Gi-Joon Nam and
Charles Alpert and
Igor L. Markov Physical Synthesis with Clock-Network
Optimization for Large Systems on Chips 51--62
Ayse K. Coskun and
Jie Meng and
David Atienza and
Mohamed M. Sabry Attaining Single-Chip, High-Performance
Computing through $3$D Systems with
Active Cooling . . . . . . . . . . . . . 63--75
Richard Vuduc and
Kent Czechowski Prolegomena: What GPU Computing Means
for High-End Systems . . . . . . . . . . 74--78
Shane Greenstein Micro Economics: An Honest Policy Wonk 80, 79
Erik R. Altman From the Editor-in-Chief: CPUs and GPUs:
Who Owns the Future? . . . . . . . . . . 2--3
David Brooks CPUs, GPUs, and Hybrid Computing . . . . 4--6
Stephen W. Keckler and
William J. Dally and
Brucek Khailany and
Michael Garland and
David Glasco GPUs and the Future of Parallel
Computing . . . . . . . . . . . . . . . 7--17
David Rohr and
Matthias Bach and
Matthias Kretz and
Volker Lindenstruth Multi-GPU DGEMM and High Performance
Linpack on Highly Energy-Efficient
Clusters . . . . . . . . . . . . . . . . 18--27
Siegfried Benkner and
Sabri Pllana and
Jesper Larsson Träff and
Philippas Tsigas and
Uwe Dolinsky and
Cédric Augonnet and
Beverly Bachmayer and
Christoph Kessler and
David Moloney and
Vitaly Osipov PEPPHER: Efficient and Productive Usage
of Hybrid Computing Systems . . . . . . 28--41
HyoukJoong Lee and
Kevin J. Brown and
Arvind K. Sujeeth and
Hassan Chafi and
Kunle Olukotun and
Tirark Rompf and
Martin Odersky Implementing Domain-Specific Languages
for Heterogeneous Parallel Computing . . 42--53
Hayden K.-H. So and
Junying Chen and
Billy Y. S. Yiu and
Alfred C. H. Yu Medical Ultrasound Imaging: To GPU or
Not to GPU? . . . . . . . . . . . . . . 54--65
Jeremy S. Meredith and
Philip C. Roth and
Kyle L. Spafford and
Jeffrey S. Vetter Performance Implications of Nonuniform
Device Topologies in Scalable
Heterogeneous Architectures . . . . . . 66--75
Richard Mateosian Micro Review: Effective Communication 76--78
Shane Greenstein Micro Economics: The Wi-Fi Journey . . . 80, 79
Erik R. Altman New Blood, Cool Chips, and Heterogeneous
Designs . . . . . . . . . . . . . . . . 2--3
Makoto Ikeda and
Fumio Arakawa Cool Chips . . . . . . . . . . . . . . . 4--5
Nobuaki Ozaki and
Yoshihiro Yasuda and
Yoshiki Saito and
Daisuke Ikebuchi and
Masayuki Kimura and
Hideharu Amano and
Hiroshi Nakamura and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo Cool Mega-Arrays: Ultralow-Power
Reconfigurable Accelerator Chips . . . . 6--18
Tomoya Suzuki and
Hideki Yamada and
Toshiyuki Yamagishi and
Daisuke Takeda and
Koji Horisaki and
Toshio Fujisawa and
Yasuo Unekawa and
Tom Vander Aa and
Liesbet Van der Perre High-Throughput, Low-Power
Software-Defined Radio Using
Reconfigurable Processors . . . . . . . 19--28
Craig A. Court and
Paul H. J. Kelly Loop-Directed Mothballing: Power Gating
Execution Units Using Runtime Loop
Analysis . . . . . . . . . . . . . . . . 29--38
Sugako Otani and
Hiroyuki Kondo and
Itaru Nonomura and
Toshihiro Hanawa and
Shin'ichi Miura and
Taisuke Boku Peach: a Multicore Communication System
on Chip with PCI Express . . . . . . . . 39--50
Hiroshi Shimamoto and
Takayuki Yamashita and
Misao Kubota and
Hirotaka Maruyama Advanced Camera Technologies for
Broadcasting . . . . . . . . . . . . . . 51--57
Greg Stitt Are Field-Programmable Gate Arrays Ready
for the Mainstream? . . . . . . . . . . 58--63
Shane Greenstein Steve Jobs and the Economics of One
Entrepreneur . . . . . . . . . . . . . . 64--65
Erik R. Altman Hot Interconnects and Hot Topics . . . . 2--3
Torsten Hoefler and
Patrick Geoffray and
Fabrizio Petrini and
Jesper Larsson Traff Top Picks from Hot Interconnects 2011:
Petascale Network Architectures . . . . 4--7
Min Xie and
Yutong Lu and
Kefei Wang and
Lu Liu and
Hongjia Cao and
Xuejun Yang Tianhe-1A Interconnect and
Message-Passing Services . . . . . . . . 8--20
Yuichiro Ajima and
Tomohiro Inoue and
Shinya Hiramoto and
Toshiyuki Shimizu and
Yuzo Takagi The Tofu Interconnect . . . . . . . . . 21--31
Dong Chen and
Noel A. Eisley and
Philip Heidelberger and
Robert M. Senger and
Yutaka Sugawara and
Sameer Kumar and
Valentina Salapura and
David Satterfield and
Burkhard Steinmacher-Burow and
Jeffrey Parker The IBM Blue Gene/Q Interconnection
Fabric . . . . . . . . . . . . . . . . . 32--43
Ismael Gomez Miguelez and
Vuk Marojevic and
Antoni Gelonch Bosch Resource Management for Software-Defined
Radio Clouds . . . . . . . . . . . . . . 44--53
Fabrice Harrouet Designing a Multicore and Multiprocessor
Individual-Based Simulation Engine . . . 54--65
Parthasarathy Ranganathan and
Jichuan Chang (Re)Designing Data-Centric Data Centers 66--70
Shane Greenstein The Range of Linus' Law . . . . . . . . 72, 71
Erik R. Altman Micro Evolution . . . . . . . . . . . . 2--2
Richard H. Stern Micro Law: Standardization Skullduggery
Never Ends: Apple v. Motorola . . . . . 3--5
Allen Baum and
Bevan Bass Hot Chips 23 . . . . . . . . . . . . . . 6--7
Manish Shah and
Robert Golla and
Gregory Grohoski and
Paul Jordan and
Jama Barreh and
Jeff Brooks and
Mark Greenberg and
Gideon Levinsky and
Mark Luttrell and
Christopher Olson and
Zeid Samoail and
Matt Smittle and
Tom Ziaja Sparc T4: a Dynamically Threaded
Server-on-a-Chip . . . . . . . . . . . . 8--19
Efraim Rotem and
Alon Naveh and
Avinash Ananthakrishnan and
Eliezer Weissmann and
Doron Rajwan Power-Management Architecture of the
Intel Microarchitecture Code-Named Sandy
Bridge . . . . . . . . . . . . . . . . . 20--27
Alexander Branover and
Denis Foley and
Maurice Steinman AMD Fusion APU: Llano . . . . . . . . . 28--37
Dongrui Fan and
Hao Zhang and
Da Wang and
Xiaochun Ye and
Fenglong Song and
Guojie Li and
Ninghui Sun Godson-T: An Efficient Many-Core
Processor Exploring Thread-Level
Parallelism . . . . . . . . . . . . . . 38--47
Ruud A. Haring and
Martin Ohmacht and
Thomas W. Fox and
Michael K. Gschwind and
David L. Satterfield and
Krishnan Sugavanam and
Paul W. Coteus and
Philip Heidelberger and
Matthias A. Blumrich and
Robert W. Wisniewski and
Alan Gara and
George Liang-Tai Chiu and
Peter A. Boyle and
Norman H. Chist and
Changhoan Kim The IBM Blue Gene/Q Compute Chip . . . . 48--60
Richard Mateosian Micro Review: Miscellany . . . . . . . . 61--63
Shane Greenstein Micro Economics: a Big Payoff . . . . . 64, C3
Erik R. Altman Top Picks, Columnists, and Artists . . . 2--2
Paolo Faraboschi and
T. N. Vijaykumar Top Picks from the 2011 Computer
Architecture Conferences . . . . . . . . 3--6
Wilson W. L. Fung and
Inderpreet Singh and
Andrew Brownsword and
Tor M. Aamodt Kilo TM: Hardware Transactional Memory
for GPU Architectures . . . . . . . . . 7--16
Daniel Sanchez and
Christos Kozyrakis Scalable and Efficient Fine-Grained
Cache Partitioning with Vantage . . . . 26--37
Hung-Wei Tseng and
Dean M. Tullsen Eliminating Redundant Computation and
Exposing Parallelism through
Data-Triggered Threads . . . . . . . . . 38--47
Niket K. Choudhary and
Salil V. Wadhavkar and
Tanmay A. Shah and
Hiran Mayukh and
Jayneel Gandhi and
Brandon H. Dwiel and
Sandeep Navada and
Hashem H. Najaf-abadi and
Eric Rotenberg FabScalar: Automating Superscalar Core
Design . . . . . . . . . . . . . . . . . 48--59
Doe Hyun Yoon and
Naveen Muralimanohar and
Jichuan Chang and
Parthasarathy Ranganathan and
Norman P. Jouppi and
Mattan Erez Free-p: a Practical End-to-End
Nonvolatile Memory Protection Mechanism 79--87
Qingyuan Deng and
Luiz Ramos and
Ricardo Bianchini and
David Meisner and
Thomas F. Wenisch Active Low-Power Modes for Main Memory
with MemScale . . . . . . . . . . . . . 60--69
Jason Mars and
Lingjia Tang and
Kevin Skadron and
Mary Lou Soffa and
Robert Hundt Increasing Utilization in Modern
Warehouse-Scale Computers Using
Bubble-Up . . . . . . . . . . . . . . . 88--99
Gabriel H. Loh and
Mark D. Hill Supporting Very Large DRAM Caches with
Compound-Access Scheduling and MissMap 70--78
Hadi Esmaeilzadeh and
Ting Cao and
Xi Yang and
Stephen M. Blackburn and
Kathryn S. McKinley What is Happening to Power, Performance,
and Software? . . . . . . . . . . . . . 110--121
Hadi Esmaeilzadeh and
Emily Blem and
Renee St. Amant and
Karthikeyan Sankaralingam and
Doug Burger Dark Silicon and the End of Multicore
Scaling . . . . . . . . . . . . . . . . 122--134
Michael Doggett Prolegomena: Texture Caches . . . . . . 136--141
Shane Greenstein Micro Economics: The Secret Life of
Wally Madhavani . . . . . . . . . . . . 142--143
Erik R. Altman The Odd Couple: Hardware and Software 2--2
Doug Burger and
Stephen W. Keckler and
Mark Papermaster Charles R. (Chuck) Moore (1961--2012) 3--5
David I. August Parallelizing Sequential Code . . . . . 6--7
Simone Campanoni and
Timothy M. Jones and
Glenn Holloway and
Gu-Yeon Wei and
David Brooks Helix: Making the Extraction of
Thread-Level Parallelism Mainstream . . 8--18
Feng Li and
Antoniu Pop and
Albert Cohen Automatic Extraction of Coarse-Grained
Data-Flow Threads from Imperative
Programs . . . . . . . . . . . . . . . . 19--31
Md Kamruzzaman and
Steven Swanson and
Dean M. Tullsen Underclocked Software Prefetching: More
Cores, Less Energy . . . . . . . . . . . 32--41
Saturnino Garcia and
Donghwan Jeon and
Christopher Louie and
Michael Bedford Taylor The Kremlin Oracle for Sequential Code
Parallelization . . . . . . . . . . . . 42--53
Hengjie Li and
Wenting He and
Yang Chen and
Lieven Eeckhout and
Olivier Temam and
Chengyong Wu SWAP: Parallelization through Algorithm
Substitution . . . . . . . . . . . . . . 54--67
Rich Belgard Yale N. Patt Receives the Inaugural IEEE
B. Ramakrishna Rau Award . . . . . . . . 68--69
Shane Greenstein Micro Economics: Calm Economics . . . . 72--72
Erik R. Altman Power- and Energy-Aware Computing . . . 2--2
Josep Torrellas 2012 International Symposium on Computer
Architecture Influential Paper Award . . 4--5
Thomas F. Wenisch and
Alper Buyuktosunoglu Energy-Aware Computing . . . . . . . . . 6--8
Vibhu Sharma and
Stefan Cosemans and
Maryam Ashouie and
Jos Huisken and
Francky Catthoor and
Wim Dehaene Ultra Low-Energy SRAM Design for Smart
Ubiquitous Sensors . . . . . . . . . . . 10--24
David Burgess and
Edmund Gieske and
James Holt and
Thomas Hoy and
Gary Whisenhunt e6500: Freescale's Low-Power,
High-Performance Multithreaded Embedded
Processor . . . . . . . . . . . . . . . 26--36
Venkatraman Govindaraju and
Chen-Han Ho and
Tony Nowatzki and
Jatin Chhugani and
Nadathur Satish and
Karthikeyan Sankaralingam and
Changkyu Kim DySER: Unifying Functionality and
Parallelism Specialization for
Energy-Efficient Computing . . . . . . . 38--51
Boris Grot and
Damien Hardy and
Pejman Lotfi-Kamran and
Babak Falsafi and
Chrysostomos Nicopoulos and
Yiannakis Sazeides Optimizing Data-Center TCO with
Scale-Out Processors . . . . . . . . . . 52--63
Sherief Reda and
Ryan Cochran and
Ayse K. Coskun Adaptive Power Capping for Servers with
Multithreaded Workloads . . . . . . . . 64--75
Richard Mateosian Micro Review: Forewords by Celebrities 76--77
Shane Greenstein Micro Economics: The Prevailing View . . 80--80
Erik R. Altman Which Way Microarchitecture? . . . . . . 2--2
Manish Arora and
Siddhartha Nath and
Subhra Mazumdar and
Scott B. Baden and
Dean M. Tullsen Redefining the Role of the CPU in the
Era of CPU--GPU Integration . . . . . . 4--16
Javier Verdu and
Alex Pajuelo and
Mateo Valero The Problem of Evaluating CPU--GPU
Systems with $3$D Visualization
Applications . . . . . . . . . . . . . . 17--27
David May The XMOS Architecture and XS1 Chips . . 28--37
Jinwook Oh and
Gyeonghoon Kim and
Injoon Hong and
Junyoung Park and
Seungjin Lee and
Joo-Young Kim and
Jeong-Ho Woo and
Hoi-Jun Yoo Low-Power, Real-Time Object-Recognition
Processors for Mobile Vision Systems . . 38--50
Kazutoshi Suito and
Rikuhei Ueda and
Kei Fujii and
Takuma Kogo and
Hiroki Matsutani and
Nobuyuki Yamasaki The Dependable Responsive Multithreaded
Processor for Distributed Real-Time
Systems . . . . . . . . . . . . . . . . 52--61
Anonymous 2012 Reviewers . . . . . . . . . . . . . 62--62
Shane Greenstein Micro Economics: Managing Complements 64, 63
Erik R. Altman Optical Interconnects and Their
Implications . . . . . . . . . . . . . . 2--2
Jeffrey A. Kash and
Raymond G. Beausoleil Special Issue: Selected Research from
the First Optical Interconnects
Conference . . . . . . . . . . . . . . . 3--5
Kazuhiro Tanaka and
Satoshi Ide and
Yukito Tsunoda and
Takashi Shiraishi and
Takatoshi Yagisawa and
Tadashi Ikeuchi and
Tsuyoshi Yamamoto and
Tomohiro Ishihara High-Bandwidth Optical Interconnect
Technologies for Next-Generation Server
Systems . . . . . . . . . . . . . . . . 6--13
Michael R. T. Tan and
Moray McLaren and
Norman P. Jouppi Optical Interconnects for
High-Performance Computing Systems . . . 14--21
Sudharsanan Srinivasan and
Yongbo Tang and
Graham Read and
Nadir Hossain and
Di Liang and
Stephen J. Sweeney and
John E. Bowers Hybrid Silicon Devices for
Energy-Efficient Optical Transmitters 22--31
Chia-Ming Chang and
Olav Solgaard Monolithic Silicon Waveguides in
Standard Silicon . . . . . . . . . . . . 32--40
Anonymous Certification House Advertisement . . . 41--41
William A. Zortman and
Anthony L. Lentine and
Douglas C. Trotter and
Michael R. Watts Bit-Error-Rate Monitoring for Active
Wavelength Control of Resonant
Modulators . . . . . . . . . . . . . . . 42--52
Noam Ophir and
Christopher Mineo and
David Mountain and
Keren Bergman Silicon Photonic Microring Links for
High-Bandwidth-Density, Low-Power Chip
I/O . . . . . . . . . . . . . . . . . . 54--67
Ron Ho and
Philip Amberg and
Eric Chang and
Pranay Koka and
Jon Lexau and
Guoliang Li and
Frankie Y. Liu and
Herb Schwetman and
Ivan Shubin and
Hiren D. Thacker and
Xuezhe Zheng and
John E. Cunningham and
Ashok V. Krishnamoorthy Silicon Photonic Interconnects for
Large-Scale Computer Systems . . . . . . 68--78
Anonymous Corporate Affiliate Program House
Advertisement . . . . . . . . . . . . . 79--79
Alexander M. Wyglinski and
Xinming Huang and
Taskin Padir and
Lifeng Lai and
Thomas R. Eisenbarth and
Krishna Venkatasubramanian Security of Autonomous Systems Employing
Embedded Computing and Sensors . . . . . 80--86
Shane Greenstein Gaming Structure . . . . . . . . . . . . 88--88
Erik R. Altman Hot Chips and the Incomplete Job of
Exploiting Them . . . . . . . . . . . . 4--5
Christos Kozyrakis and
Rumi Zahir Selected Research from Hot Chips 24 . . 6--7
Ronald G. Dreslinski and
David Fick and
Bharan Giridhar and
Gyouho Kim and
Sangwon Seo and
Matthew Fojtik and
Sudhir Satpathy and
Yoonmyung Lee and
Daeyeon Kim and
Nurrachman Liu and
Michael Wieckowski and
Gregory Chen and
Dennis Sylvester and
David Blaauw and
Trevor Mudge Centip3De: A 64-Core, $3$D Stacked
Near-Threshold System . . . . . . . . . 8--16
Robert Rogenmoser and
Lawrence T. Clark Reducing Transistor Variability for High
Performance Low Power Chips . . . . . . 18--26
Gregory Ruhl and
Saurabh Dighe and
Shailendra Jain and
Surhud Khare and
Sriram R. Vangal IA-32 Processor with a
Wide-Voltage-Operating Range in 32-nm
CMOS . . . . . . . . . . . . . . . . . . 28--36
C. Kevin Shum and
Fadi Busaba and
Christian Jacobi IBM zEC12: The Third-Generation
High-Frequency Mainframe Microprocessor 38--47
John Feehrer and
Sumti Jairath and
Paul Loewenstein and
Ram Sivaramakrishnan and
David Smentek and
Sebastian Turullols and
Ali Vahidsafa The Oracle Sparc T5 16-Core Processor
Scales to Eight Sockets . . . . . . . . 48--57
Richard Mateosian Micro Review: Ethics of Big Data . . . . 60--61
Shane Greenstein Micro Economics: The Online Honesty Box 62--63
Erik R. Altman From the Editor in Chief: Ten Years of
Top Picks . . . . . . . . . . . . . . . 2--2
Babak Falsafi and
Gabriel H. Loh Guest Editors' Introduction: Top Picks
from the 2012 Computer Architecture
Conferences . . . . . . . . . . . . . . 4--7
Arun Raghavan and
Yixin Luo and
Anuj Chandawalla and
Marios Papaefthymiou and
Kevin P. Pipe and
Thomas F. Wenisch and
Milo M. K. Martin Designing for Responsiveness with
Computational Sprinting . . . . . . . . 8--15
Hadi Esmaeilzadeh and
Adrian Sampson and
Luis Ceze and
Doug Burger Neural Acceleration for General-Purpose
Approximate Programs . . . . . . . . . . 16--27
Daniel Wong and
Murali Annavaram Scaling the Energy Proportionality Wall
with KnightShift . . . . . . . . . . . . 28--37
Santosh Nagarakatte and
Milo M. K. Martin and
Steve Zdancewic Hardware-Enforced Comprehensive Memory
Safety . . . . . . . . . . . . . . . . . 38--47
Jonathan Kaveh Valamehr and
Melissa Chase and
Seny Kamara and
Andrew Putnam and
Daniel Shumow and
Vinod Vaikuntanathan and
Timothy Sherwood Inspection-Resistant Memory
Architectures . . . . . . . . . . . . . 48--56
Siva Kumar Sastry Hari and
Sarita V. Adve and
Helia Naeimi and
Pradeep Ramachandran Relyzer: Application Resiliency Analyzer
for Transient Faults . . . . . . . . . . 58--66
John Demme and
Robert Martin and
Adam Waksman and
Simha Sethumadhavan A Quantitative, Experimental Approach to
Measuring Processor Side-Channel
Security . . . . . . . . . . . . . . . . 68--77
Timothy G. Rogers and
Mike O'Connor and
Tor M. Aamodt Cache-Conscious Thread Scheduling for
Massively Multithreaded Processors . . . 78--85
Melanie Kambadur and
Kui Tang and
Martha A. Kim Parallel Block Vectors: Collection,
Analysis, and Uses . . . . . . . . . . . 86--94
Abhayendra Singh and
Satish Narayanasamy and
Daniel Marino and
Todd Millstein and
Madanlal Musuvathi A Safety-First Approach to Memory Models 96--104
Mahdi Nazm Bojnordi and
Engin Ipek Programmable DDRx Controllers . . . . . 106--115
Richard Mateosian Micro Review: Unconscious Meaning
[review of \booktitleA User's Guide to
Thought and Meaning; Jackendoff, R.;
2012] . . . . . . . . . . . . . . . . . 116--118
Shane Greenstein Micro Economics: Differentiated
Platforms . . . . . . . . . . . . . . . 120--120
Erik R. Altman Reliability, Theme Issues, and
Plagiarism . . . . . . . . . . . . . . . 2--2
Vijay Janapa Reddi Reliability-Aware Microarchitecture
Design [Guest editor's introduction] . . 4--5
Ulya R. Karpuzcu and
Nam Sung Kim and
Josep Torrellas Coping with Parametric Variation at
Near-Threshold Voltages . . . . . . . . 6--14
Hao Wang and
Nam Sung Kim Improving Throughput of
Power-Constrained Many-Core Processors
Based on Unreliable Devices . . . . . . 16--24
David J. Palframan and
Nam Sung Kim and
Mikko H. Lipasti Resilient High-Performance Processors
with Spare RIBs . . . . . . . . . . . . 26--34
Charles R. Lefurgy and
Alan J. Drake and
Michael S. Floyd and
Malcolm S. Allen-Ware and
Bishop Brock and
Jose A. Tierno and
John B. Carter and
Robert W. Berry Active Guardband Management in Power7+
to Save Energy and Maintain Reliability 35--45
Veit B. Kleeberger and
Christina Gimmler-Dumont and
Christian Weis and
Andreas Herkersdorf and
Daniel Mueller-Gritschneder and
Sani R. Nassif and
Ulf Schlichtmann and
Norbert Wehn A Cross-Layer Technology-Based Study of
How Memory Errors Impact System
Resilience . . . . . . . . . . . . . . . 46--55
Lukasz G. Szafaryn and
Brett H. Meyer and
Kevin Skadron Evaluating Overheads of Multibit
Soft-Error Protection in the Processor
Core . . . . . . . . . . . . . . . . . . 56--65
Youngtaek Kim and
Lizy Kurian John and
Sanjay Pant and
Srilatha Manne and
Michael Schulte and
W. Lloyd Bircher and
Madhu Saravana Sibi Govindan Automating Stressmark Generation for
Testing Processor Voltage Fluctuations 66--75
Richard H. Stern Microsoft Tells Court That Without
FRAND, Standard-Setting Would Be
``Blatant Antitrust Violation'' . . . . 76--77
Shane Greenstein Platform Conflicts [Micro Economics] . . 78--79
Erik R. Altman Dark Silicon and Dangerous Predictions 4--5
Michael B. Taylor and
Steven Swanson Dark Silicon [Guest Editors'
introduction] . . . . . . . . . . . . . 6--7
Michael B. Taylor A Landscape of the New Dark Silicon
Design Regime . . . . . . . . . . . . . 8--19
Arun Raghavan and
Laurel Emurian and
Lei Shao and
Marios Papaefthymiou and
Kevin P. Pipe and
Thomas F. Wenisch and
Milo M. K. Martin Utilizing Dark Silicon to Save Energy
with Computational Sprinting . . . . . . 20--28
Nathaniel Pinckney and
Ronald G. Dreslinski and
Korey Sewell and
David Fick and
Trevor Mudge and
Dennis Sylvester and
David Blaauw Limits of Parallelism and Boosting in
Dim Silicon . . . . . . . . . . . . . . 30--37
Liang Wang and
Kevin Skadron Implications of the Power Wall: Dim
Cores and Reconfigurable Logic . . . . . 40--48
Karthik Swaminathan and
Emre Kultursay and
Vinay Saripalli and
Vijaykrishnan Narayanan and
Mahmut T. Kandemir and
Suman Datta Steep-Slope Devices: From Dark to Dim
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Rich Belgard Awards: Joseph A. (Josh) Fisher Receives
the 2012 IEEE B. Ramakrishna Rau Award 60--61
Shane Greenstein Micro Economics: Digital Public Goods 62--63
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Noriyuki Miura and
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Naohiro Kiyota and
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Margaret Martonosi 2013 International Symposium on Computer
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John Sell and
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David Kidd Process and Circuit Optimization for
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Mithuna S. Thottethodi and
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Inigo Goiri and
William Katsak and
Kien Le and
Thu D. Nguyen and
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Christina Delimitrou and
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Michael Ferdman and
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Tushar Krishna and
Chia-Hsin Owen Chen and
Woo-Cheol Kwon and
Li-Shiuan Peh Smart: Single-Cycle Multihop Traversals
over a Shared Network on Chip . . . . . 43--56
Hassan M. G. Wassel and
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Jason K. Oberg and
Ted Huffmire and
Ryan Kastner and
Frederic T. Chong and
Timothy Sherwood Networks on Chip with Provable Security
Properties . . . . . . . . . . . . . . . 57--68
Inderpreet Singh and
Arrvindh Shriraman and
Wilson W. L. Fung and
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Tor M. Aamodt Cache Coherence for GPU Architectures 69--79
Jaewoong Sim and
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Vilas Sridharan and
Mike O'Connor A Configurable and Strong RAS Solution
for Die-Stacked DRAM Caches . . . . . . 80--90
Somayeh Sardashti and
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Spatial Locality for Energy Optimization 91--99
Richard Sampson and
Ming Yang and
Siyuan Wei and
Chaitali Chakrabarti and
Thomas F. Wenisch Sonic Millip3De: An Architecture for
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Lisa Wu and
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Martha A. Kim and
Kenneth A. Ross Hardware Partitioning for Big Data
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Angshuman Parashar and
Michael Pellauer and
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Neal Crago and
Daniel Lustig and
Vladimir Pavlov and
Antonia Zhai and
Mohit Gambhir and
Aamer Jaleel and
Randy Allmon and
Rachid Rayess and
Stephen Maresh and
Joel Emer Efficient Spatial Processing Element
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Hyojin Sung and
Rakesh Komuravelli and
Sarita V. Adve DeNovoND: Efficient Hardware for
Disciplined Nondeterminism . . . . . . . 138--148
James Goodman Reflections from the 2013 Eckert-Mauchly
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Shane Greenstein Micro Economics: The Academic and
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Babak Falsafi and
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Raphael Polig and
Kubilay Atasu and
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Van Bui and
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Richard H. Stern Alice v. CLS Bank: Are US
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Xabier Iturbe and
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Gyeonghoon Kim and
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Hikaru Tamura and
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Jun Yao and
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Shuming Chen and
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Dan Wang and
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Stephen W. Keckler and
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Calin Cascaval Special Issue on Mobile Systems . . . . 4--5
Mircea Horea Ionica and
David Gregg The Movidius Myriad Architecture's
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Hyojong Kim and
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Yuhao Zhu and
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YaoZu Dong and
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Chenxiong Qian and
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Richard H. Stern Federal Circuit Speaks Out on
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Anonymous 2014 Reviewers . . . . . . . . . . . . . 62--63
Shane Greenstein Networking standards and Russell's
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Onur Mutlu and
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introduction] . . . . . . . . . . . . . 4--5
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Nikola Markovic and
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Amoghavarsha Suresh and
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Avinash Sodani and
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Ronald G. Dreslinski and
Trevor Mudge and
Vinicius Petrucci and
Lingjia Tang and
Jason Mars Sirius Implications for Future
Warehouse-Scale Computers . . . . . . . 42--53
Svilen Kanev and
Juan Pablo Darago and
Kim Hazelwood and
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Tipp Moseley and
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Yuan Xie and
John Jack Sampson and
Vijaykrishnan Narayanan Nonvolatile Processor Architectures:
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Ajaykumar Kannan and
Natalie Enright Jerger and
Gabriel H. Loh Exploiting Interposer Technologies to
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Anuj Kalia and
Michael Kaminsky and
David G. Andersen and
Seongil O and
Sukhan Lee and
Pradeep Dubey Achieving One Billion Key-Value Requests
per Second on a Single Server . . . . . 94--104
Mark C. Jeffrey and
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Cong Yan and
Joel Emer and
Daniel Sanchez Unlocking Ordered Parallelism with the
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Jayneel Gandhi and
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Per Stenstrom 2015 Maurice Wilkes Award Given to
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Shane Greenstein Economic Growth from Technical Advance 130--131
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Salvatore Di Girolamo and
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Torsten Hoefler Exploiting Offload-Enabled Network
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John W. Lockwood and
Madhu Monga Implementing Ultra-Low-Latency
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Amitabha Banerjee and
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Mark S. Birrittella and
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Keith D. Underwood and
Robert C. Zak Enabling Scalable High-Performance
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Trevor Mudge and
Frederic T. Chong and
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Resit Sendag and
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Anonymous Rock Stars of Pervasive, Predictive
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Shane Greenstein Ten Open Questions for Techno-Optimists 86--87
Anonymous Watch the World's Leading Experts Take
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Mohit Tiwari and
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Fangfei Liu and
Hao Wu and
Kenneth Mai and
Ruby B. Lee Newcache: Secure Cache Architecture
Thwarting Cache Side-Channel Attacks . . 8--16
Guru Venkataramani and
Jie Chen and
Milos Doroslovacki Detecting Hardware Covert Timing
Channels . . . . . . . . . . . . . . . . 17--27
Tianwei Zhang and
Ruby B. Lee Monitoring and Attestation of Virtual
Machine Security Health in Cloud
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Robert N. M. Watson and
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Bongjun Kim and
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Cliff Young and
Nishant Patil and
David Patterson Motivation for and Evaluation of the
First Tensor Processing Unit . . . . . . 10--19
Raghu Prabhakar and
Yaqi Zhang and
David Koeplinger and
Matt Feldman and
Tian Zhao and
Stefan Hadjis and
Ardavan Pedram and
Christos Kozyrakis and
Kunle Olukotun Plasticine: A Reconfigurable Accelerator
for Parallel Patterns . . . . . . . . . 20--31
Hari Cherupalli and
Henry Duwe and
Weidong Ye and
Rakesh Kumar and
John Sartori Bespoke Processors for Applications with
Ultra-Low Area and Power Constraints . . 32--39
X. Fu and
M. A. Rol and
C. C. Bultink and
J. van Someren and
N. Khammassi and
I. Ashraf and
R. F. L. Vermeulen and
J. C. de Sterke and
W. J. Vlothuizen and
R. N. Schouten and
C. G. Almudever and
L. DiCarlo and
K. Bertels A Microarchitecture for a
Superconducting Quantum Processor . . . 40--47
Stefanos Kaxiras and
Trevor E. Carlson and
Mehdi Alipour and
Alberto Ros Non-Speculative Load Reordering in Total
Store Ordering . . . . . . . . . . . . . 48--57
Caroline Trippel and
Yatin A. Manerkar and
Daniel Lustig and
Michael Pellauer and
Margaret Martonosi Full-Stack Memory Model Verification
with TriCheck . . . . . . . . . . . . . 58--68
Abhishek Bhattacharjee Breaking the Address Translation Wall by
Accelerating Memory Replays . . . . . . 69--78
Masoumeh Ebrahimi and
Masoud Daneshtalab A General Methodology on Designing
Acyclic Channel Dependency Graphs in
Interconnection Networks . . . . . . . . 79--85
Christina Delimitrou and
Christos Kozyrakis Uncovering the Security Implications of
Cloud Multi-Tenancy with Bolt . . . . . 86--97
Adrian Tang and
Simha Sethumadhavan and
Salvatore Stolfo Motivating Security-Aware Energy
Management . . . . . . . . . . . . . . . 98--106
Joseph McMahan and
Michael Christensen and
Lawton Nichols and
Jared Roesch and
Sung-Yee Guo and
Ben Hardekopf and
Timothy Sherwood An Architecture for Analysis . . . . . . 107--115
Weilong Cui and
Timothy Sherwood Architectural Risk . . . . . . . . . . . 116--125
Shane Greenstein Adjusting to Autonomous Trucking . . . . 126--128
Anonymous Front Cover . . . . . . . . . . . . . . c1--c1
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Anonymous Membership Ad . . . . . . . . . . . . . c2--c2
Anonymous MyCS Ad . . . . . . . . . . . . . . . . c4--c4
Anonymous Education Award Ad . . . . . . . . . . . 1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Anonymous Masthead . . . . . . . . . . . . . . . . 4
Anonymous IEEE Computer Society Information . . . 5
Lieven Eeckhout Approximate Computing, Intelligent
Computing . . . . . . . . . . . . . . . 6--7
Natalie Enright Jerger and
Joshua San Miguel Approximate Computing . . . . . . . . . 8--10
Kaisheng Ma and
Jinyang Li and
Xueqing Li and
Yongpan Liu and
Yuan Xie and
Mahmut Kandemir and
Jack Sampson and
Vijaykrishnan Narayanan IAA: Incidental Approximate
Architectures for Extremely
Energy-Constrained Energy Harvesting
Scenarios using IoT Nonvolatile
Processors . . . . . . . . . . . . . . . 11--19
Phillip Stanley-Marbell and
Martin Rinard Perceived-Color Approximation Transforms
for Programs that Draw . . . . . . . . . 20--29
Serif Yesil and
Ismail Akturk and
Ulya R. Karpuzcu Toward Dynamic Precision Scaling . . . . 30--39
Vasileios Leon and
Georgios Zervakis and
Sotirios Xydis and
Dimitrios Soudris and
Kiamal Pekmestzi Walking through the Energy-Error Pareto
Frontier of Approximate Multipliers . . 40--49
Zhenhong Liu and
Amir Yazdanbakhsh and
Taejoon Park and
Hadi Esmaeilzadeh and
Nam Sung Kim SiMul: An Algorithm-Driven Approximate
Multiplier Design for Machine Learning 50--59
Georgios Tziantzioulis and
Nikos Hardavellas and
Simone Campanoni Temporal Approximate Function
Memoization . . . . . . . . . . . . . . 60--70
Hank Levy and
Susan Eggers Susan Eggers Receives Eckert--Mauchly
Award for Outstanding Contributions to
Computer Architecture . . . . . . . . . 71--75
Antonio Gonzalez 2018 International Symposium on Computer
Architecture Influential Paper Award . . 76--77
Shane Greenstein The Technology Tel . . . . . . . . . . . 78--80
Anonymous Babbage Award Ad . . . . . . . . . . . . c2--c2
Anonymous Front Cover . . . . . . . . . . . . . . c1--c1
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Anonymous Merwin Award Ad . . . . . . . . . . . . c3--c3
Anonymous Masthead . . . . . . . . . . . . . . . . 1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lieven Eeckhout Memristors and More . . . . . . . . . . 4
Lizy K. John and
Earl E. Swartzlander Memristor-Based Computing . . . . . . . 5--6
Leon Chua Memristor: Remembrance of Things Past 7--12
Ameer Haj-Ali and
Rotem Ben-Hur and
Nimrod Wald and
Ronny Ronen and
Shahar Kvatinsky Not in Name Alone: A Memristive Memory
Processing Unit for Real In-Memory
Processing . . . . . . . . . . . . . . . 13--21
Onur Tunali and
M. Ceylan Morgul and
Mustafa Altun Defect-Tolerant Logic Synthesis for
Memristor Crossbars with Performance
Evaluation . . . . . . . . . . . . . . . 22--31
Leonid Yavits and
Roman Kaplan and
Ran Ginosar Enabling Full Associativity with
Memristive Address Decoder . . . . . . . 32--40
Anirban Nag and
Rajeev Balasubramonian and
Vivek Srikumar and
Ross Walker and
Ali Shafiee and
John Paul Strachan and
Naveen Muralimanohar Newton: Gravitating Towards the Physical
Limits of Crossbar Acceleration . . . . 41--49
Deji Akinwande Memory, Memristors, and Atomristors . . 50--52
Xiebing Wang and
Kai Huang and
Long Chen and
Alois Knoll h$^2$ECU: A High-Performance and
Heterogeneous Electronic Control Unit
for Automated Driving . . . . . . . . . 53--62
Georgios Kornaros and
Othon Tomoutzoglou and
Marcello Coppola Hardware-Assisted Security in Electronic
Control Units: Secure Automotive
Communications by Utilizing
One-Time-Programmable Network on Chip
and Firewalls . . . . . . . . . . . . . 63--74
Takumi Maruyama and
Yasunobu Akizuki and
Takekazu Tabata and
Kenichi Kitamura and
Noriko Takagi and
Hiroyuki Ishii and
Shingo Watanabe and
Fumihiro Tawa SPARC64 XII: Fujitsu's Latest $ 12$-Core
Processor for Mission-Critical Servers 75--84
Dongjoo Shin and
Jinmook Lee and
Jinsu Lee and
Juhyoung Lee and
Hoi-Jun Yoo DNPU: An Energy-Efficient Deep-Learning
Processor with Heterogeneous Multi-Core
Architecture . . . . . . . . . . . . . . 85--93
Shane Greenstein Free Software without a Free Lunch or
Free Beer . . . . . . . . . . . . . . . 94--96
Anonymous Front Cover . . . . . . . . . . . . . . c1--c1
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Anonymous Membership Ad . . . . . . . . . . . . . c4--c4
Anonymous Social Networking Ad . . . . . . . . . . c2--c2
Anonymous IEEE Technology and Engineering
Management Society TEMS Administrative
Committee . . . . . . . . . . . . . . . 1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lieven Eeckhout Hardware Acceleration and a Grateful
Goodbye . . . . . . . . . . . . . . . . 4--5
Martha Kim and
Yakun Sophia Shao Hardware Acceleration . . . . . . . . . 6--7
Ronaldo Husemann and
Altamiro Amadeu Susin and
Valter Roesler Optimized Solution to Accelerate in
Hardware an Intra H.264/SVC Video
Encoder . . . . . . . . . . . . . . . . 8--17
Naif Tarafdar and
Nariman Eskandari and
Varun Sharma and
Charles Lo and
Paul Chow Galapagos: A Full Stack Approach to FPGA
Integration in the Cloud . . . . . . . . 18--24
Hyoukjun Kwon and
Ananda Samajdar and
Tushar Krishna A Communication-Centric Approach for
Designing Flexible DNN Accelerators . . 25--35
Davide Giri and
Paolo Mantovani and
Luca P. Carloni Accelerators and Coherence: An SoC
Perspective . . . . . . . . . . . . . . 36--45
Sergi Alcaide and
Leonidas Kosmidis and
Hamid Tabani and
Carles Hernandez and
Jaume Abella and
Francisco J. Cazorla Safety-Related Challenges and
Opportunities for GPUs in the Automotive
Domain . . . . . . . . . . . . . . . . . 46--55
Wen-mei Hwu and
Sanjay Patel Accelerator Architectures: A Ten-Year
Retrospective . . . . . . . . . . . . . 56--62
Omid Akbari and
Mehdi Kamal and
Ali Afzali-Kusha and
Massoud Pedram and
Muhammad Shafique Toward Approximate Computing for
Coarse-Grained Reconfigurable
Architectures . . . . . . . . . . . . . 63--72
Renyuan Zhang and
Noriyuki Uetake and
Takashi Nakada and
Yasuhiko Nakashima Design of Programmable Analog
Calculation Unit by Implementing Support
Vector Regression for Approximate
Computing . . . . . . . . . . . . . . . 73--82
Sandhya Dwarkadas 2018 Maurice Wilkes Award Given to
Gabriel Loh . . . . . . . . . . . . . . 83--84
Anonymous Erratum to Defect-Tolerant Logic
Synthesis for Memristor Crossbars with
Performance Evaluation . . . . . . . . . 85
Shane Greenstein Organized for Cycles of Change . . . . . 86--88
Anonymous Cover . . . . . . . . . . . . . . . . . C1
Anonymous Front Cover . . . . . . . . . . . . . . C1
Anonymous IEEE Computer Society . . . . . . . . . C3
Anonymous IEEE Computer Society . . . . . . . . . C4
E. Ipek Memristive accelerators for dense and
sparse linear algebra: From machine
learning to high-performance scientific
computing . . . . . . . . . . . . . . . 58--61
S. H. Noh Has the Time for EMT Finally Come? . . . 67--68
S. Greenstein Six infrastructure trends . . . . . . . 70--72
Y. Solihin Persistent memory: Abstractions,
abstractions, and abstractions . . . . . 65--66
N. Talati and
H. Ha and
B. Perach and
R. Ronen and
S. Kvatinsky CONCEPT: A Column-Oriented Memory
Controller for Efficient Memory and PIM
Operations in RRAM . . . . . . . . . . . 33--43
S. Swanson Redesigning file systems for nonvolatile
main memory . . . . . . . . . . . . . . 62--64
Y. Xie and
J. Zhao Emerging Memory Technologies . . . . . . 6--7
Anonymous Call for Award Nominations . . . . . . . C2--C2
A. Jain and
S. Lloyd and
M. Gokhale Performance Assessment of Emerging
Memories Through FPGA Emulation . . . . 8--16
M. Qureshi With new memories come new challenges 52--53
Anonymous Table of Contents . . . . . . . . . . . 2--3
P. Zuo and
Y. Hua and
M. Zhao and
W. Zhou and
Y. Guo Write Deduplication and Hash Mode
Encryption for Secure Nonvolatile Main
Memory . . . . . . . . . . . . . . . . . 44--51
L. John To the Era of Intelligent Chips and
Systems . . . . . . . . . . . . . . . . 4--5
M. Xie and
C. Pan and
Y. Zhang and
J. Hu and
Y. Liu and
C. Xue A Novel STT-RAM-Based Hybrid Cache for
Intermittently Powered Processors in IoT
Devices . . . . . . . . . . . . . . . . 24--32
Y. Kim and
M. Imani and
T. Rosing Image Recognition Accelerator Design
Using In-Memory Processing . . . . . . . 17--23
Y. Chen Reshaping Future Computing Systems With
Emerging Nonvolatile Memory Technologies 54--57
B. Gervasi Will Carbon Nanotube Memory Replace
DRAM? . . . . . . . . . . . . . . . . . 45--51
C. Celio and
P. Chiu and
K. Asanovic and
B. Nikolic and
D. Patterson BROOM: An Open-Source Out-of-Order
Processor With Resilient Low-Voltage
Operation in 28-nm CMOS . . . . . . . . 52--60
M. Arafa and
B. Fahim and
S. Kottapalli and
A. Kumar and
L. P. Looi and
S. Mandava and
A. Rudoff and
I. M. Steiner and
B. Valentine and
G. Vedaraman and
S. Vora Cascade Lake: Next Generation Intel Xeon
Scalable Processor . . . . . . . . . . . 29--36
M. D. Hill and
J. Masters and
P. Ranganathan and
P. Turner and
J. L. Hennessy On the Spectre and Meltdown Processor
Security Vulnerabilities . . . . . . . . 9--19
J. Rupley and
B. Burgess and
B. Grayson and
G. D. Zuraski Samsung M3 Processor . . . . . . . . . . 37--44
J. Kubiatowicz and
S. Rusu Hot Chips 30 . . . . . . . . . . . . . . 6--8
Anonymous Call for Award Nominations . . . . . . . C2--C2
Anonymous [Masthead] . . . . . . . . . . . . . . . 1--1
L. John Emerging Hot Chips and Systems . . . . . 4--5
D. Stiles The Hardware Security Behind Azure
Sphere . . . . . . . . . . . . . . . . . 20--28
Anonymous Stay connected [back cover] . . . . . . C4--C4
Anonymous IEEE Computer Society Information . . . C3--C3
S. Greenstein Where the Frontier Thrives: Bricks, Mix,
and Zip . . . . . . . . . . . . . . . . 62--64
Anonymous Table of Contents . . . . . . . . . . . 2--3
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE World Congress on Services 2019 . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of contents . . . . . . . . . . . 2--3
L. K. John Top Picks . . . . . . . . . . . . . . . 4--5
S. Dwarkadas Top Picks in Computer Architecture from
Conferences in 2018 . . . . . . . . . . 6--10
C. Eckert and
X. Wang and
J. Wang and
A. Subramaniyan and
D. Sylvester and
D. Blaauw and
R. Das and
R. Iyer Neural Cache: Bit-Serial In-Cache
Acceleration of Deep Neural Networks . . 11--19
J. Fowers and
K. Ovtcharov and
M. K. Papamichael and
T. Massengill and
M. Liu and
D. Lo and
S. Alkalay and
M. Haselman and
L. Adams and
M. Ghandi and
S. Heil and
P. Patel and
A. Sapek and
G. Weisz and
L. Woods and
S. Lanka and
S. K. Reinhardt and
A. M. Caulfield and
E. S. Chung and
D. Burger Inside Project Brainwave's Cloud-Scale,
Real-Time AI Processor . . . . . . . . . 20--28
Y. Turakhia and
G. Bejerano and
W. J. Dally Darwin: A Genomics Coprocessor . . . . . 29--37
M. Maas and
K. Asanovic and
J. Kubiatowicz A Hardware Accelerator for Tracing
Garbage Collection . . . . . . . . . . . 38--46
S. Zhang and
A. Wright and
T. Bourgeat Composable Building Blocks to Open Up
Processor Design . . . . . . . . . . . . 47--55
S. Karandikar and
H. Mao and
D. Kim and
D. Biancolin and
A. Amid and
D. Lee and
N. Pemberton and
E. Amaro and
C. Schmidt and
A. Chopra and
Q. Huang and
K. Kovacs and
B. Nikoli and
R. H. Katz and
J. Bachrach and
K. Asanovi FireSim: FPGA-Accelerated Cycle-Exact
Scale-Out System Simulation in the
Public Cloud . . . . . . . . . . . . . . 56--65
J. Van Bulck and
M. Minkin and
O. Weisse and
D. Genkin and
B. Kasikci and
F. Piessens and
M. Silberstein and
T. F. Wenisch and
Y. Yarom and
R. Strackx Breaking Virtual Memory Protection and
the SGX Ecosystem with Foreshadow . . . 66--74
M. Taram and
A. Venkat and
D. M. Tullsen Context-Sensitive Decoding: On-Demand
Microcode Customization for Security and
Energy Management . . . . . . . . . . . 75--83
C. Trippel and
D. Lustig and
M. Martonosi Security Verification via Automatic
Hardware-Aware Exploit Synthesis: The
CheckMate Approach . . . . . . . . . . . 84--93
A. Kolli and
V. Gogte and
A. Saidi and
S. Diestelhorst and
W. Wang and
P. M. Chen and
S. Narayanasamy and
T. F. Wenisch Language Support for Memory Persistency 94--102
K. Nguyen and
K. Lyu and
X. Meng and
V. Sridharan and
X. Jian Nonblocking DRAM Refresh . . . . . . . . 103--109
A. Ramrakhyani and
P. V. Gratz and
T. Krishna Synchronized Progress in Interconnection
Networks (SPIN): A New Theory for
Deadlock Freedom . . . . . . . . . . . . 110--117
S. Greenstein Misapplied metaphors in AI policy . . . 118--120
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous Looking for the BEST Tech Job for You? C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous Call for Awards . . . . . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. K. John Secure Architectures . . . . . . . . . . 4--5
Anonymous Call For Articles . . . . . . . . . . . 5--5
S. Sethumadhavan and
M. Tiwari Secure Architectures . . . . . . . . . . 6--7
Anonymous IEEE TRANSACTIONS ON SUSTAINABLE
COMPUTING . . . . . . . . . . . . . . . 7--7
F. Yao and
H. Fang and
M. Doroslova\vcki and
G. Venkataramani Leveraging Cache Management Hardware for
Practical Defense Against Cache Timing
Channel Attacks . . . . . . . . . . . . 8--16
R. Misoczki and
S. Gulley and
V. Gopal and
M. G. Dixon and
H. Vrsalovic and
W. K. Feghali Toward Postquantum Security for Embedded
Cores . . . . . . . . . . . . . . . . . 17--26
Anonymous \booktitleIEEE Annals . . . . . . . . . 26--26
P. Bose and
S. Mukhopadhyay Energy-Secure System Architectures
(ESSA): A Workshop Report . . . . . . . 27--34
C. Sturton and
M. Hicks and
S. T. King and
J. M. Smith FinalFilter: Asserting Security
Properties of a Processor at Runtime . . 35--42
Anonymous IEEE Security Privacy . . . . . . . . . 43--43
R. Kaplan and
L. Yavits and
R. Ginosar RASSA: Resistive Prealignment
Accelerator for Approximate DNA Long
Read Mapping . . . . . . . . . . . . . . 44--54
Anonymous \booktitleIEEE Transactions on Big Data 54--54
A. Mirhosseini and
T. F. Wenisch The Queuing-First Approach for Tail
Management of Interactive Services . . . 55--64
Anonymous \booktitleIEEE Computer Architecture
[Letters] . . . . . . . . . . . . . . . 65--65
S. Greenstein The Aftermath of the Dyn DDOS Attack . . 66--68
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous Keep Your Career Options Open . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. K. John Machine Learning Accelerators and More 4--5
H. Esmaeilzadeh and
J. Park Machine Learning Acceleration . . . . . 6--7
T. Moreau and
T. Chen and
L. Vega and
J. Roesch and
E. Yan and
L. Zheng and
J. Fromm and
Z. Jiang and
L. Ceze and
C. Guestrin and
A. Krishnamurthy A Hardware Software Blueprint for
Flexible Deep Learning Specialization 8--16
Y. Shen and
T. Ji and
M. Ferdman and
P. Milder Argus: An End-to-End Framework for
Accelerating CNNs on FPGAs . . . . . . . 17--25
M. Mahmoud and
D. M. Stuart and
Z. Poulos and
A. D. Lascorz and
P. Judd and
S. Sharify and
M. Nikoli and
K. Siu and
I. E. Vivancos and
J. Albericio and
A. Moshovos Accelerating Image-Sensor-Based Deep
Learning Applications . . . . . . . . . 26--35
M. Riera and
J. Arnau and
A. González CGPA: Coarse-Grained Pruning of
Activations for Energy-Efficient RNN
Inference . . . . . . . . . . . . . . . 36--45
B. Asgari and
R. Hadidi and
H. Kim and
S. Yalamanchili ERIDANUS: Efficiently Running Inference
of DNNs Using Systolic Arrays . . . . . 46--54
A. C. Yüzügüler and
F. Celik and
M. Drumond and
B. Falsafi and
P. Frossard Analog Neural Networks With
Deep-Submicrometer Nonlinear Synapses 55--63
M. Kang and
P. Srivastava and
V. Adve and
N. S. Kim and
N. R. Shanbhag An Energy-Efficient Programmable
Mixed-Signal Accelerator for Machine
Learning Algorithms . . . . . . . . . . 64--72
J. Bae and
H. Jang and
J. Gong and
W. Jin and
S. Kim and
J. Jang and
T. J. Ham and
J. Jeong and
J. W. Lee SSDStreamer: Specializing I/O Stack for
Large-Scale Machine Learning . . . . . . 73--81
Y. Kwon and
M. Rhu A Disaggregated Memory System for Deep
Learning . . . . . . . . . . . . . . . . 82--90
S. Pal and
E. Ebrahimi and
A. Zulfiqar and
Y. Fu and
V. Zhang and
S. Migacz and
D. Nellans and
P. Gupta Optimizing Multi-GPU Parallelization
Strategies for Deep Learning Training 91--101
S. Venkataramani and
J. Choi and
V. Srinivasan and
W. Wang and
J. Zhang and
M. Schaal and
M. J. Serrano and
K. Ishizaki and
H. Inoue and
E. Ogawa and
M. Ohara and
L. Chang and
K. Gopalakrishnan DeepTools: Compiler and Execution
Runtime Extensions for RaPiD AI
Accelerator . . . . . . . . . . . . . . 102--111
Anonymous Call for Papers: \booktitleIEEE Micro
Top Picks 2019 . . . . . . . . . . . . . 112--112
Anonymous \booktitleIEEE Micro . . . . . . . . . . 113--113
R. Mateosian What I Missed . . . . . . . . . . . . . 114--116
Anonymous \booktitleIEE Annals . . . . . . . . . . 117--117
Anonymous \booktitleIEE Annals . . . . . . . . . . 118--118
M. D. Hill Reflections and Research Advice Upon
Receiving the 2019 Eckert--Mauchly Award 119--124
Anonymous Share and Manage Your Research Data . . 125--125
S. Greenstein Earning Stripes in Medical Machine
Learning . . . . . . . . . . . . . . . . 126--128
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous Keep Your Career Options Open . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of contents . . . . . . . . . . . 2--3
L. K. John $3$-D Chips! Chips are Getting Denser
and Taller Than Ever!! . . . . . . . . . 4--5
Anonymous \booktitleSecurity & Privacy . . . . . . 5--5
V. Narayanan Going Vertical: The Future of
Electronics . . . . . . . . . . . . . . 6--7
S. Datta and
S. Dutta and
B. Grisafe and
J. Smith and
S. Srinivasa and
H. Ye Back-End-of-Line Compatible Transistors
for Monolithic $3$-D Integration . . . . 8--15
M. D. Bishop and
H.-P. Wong and
S. Mitra and
M. M. Shulaker Monolithic $3$-D Integration . . . . . . 16--27
Z. Zhang and
X. Si and
S. Srinivasa and
A. K. Ramanathan and
M. Chang Recent Advances in Compute-in-Memory
Support for SRAM Using Monolithic $3$-D
Integration . . . . . . . . . . . . . . 28--37
Anonymous IEEE Computer Society Has You Covered! 37--37
S. Pentapati and
L. Zhu and
L. Bamberg and
D. E. Shim and
A. García-Ortiz and
S. K. Lim A Logic-on-Memory Processor-System
Design With Monolithic $3$-D Technology 38--45
I. Akgun and
D. Stow and
Y. Xie Network-on-Chip Design Guidelines for
Monolithic $3$-D Integration . . . . . . 46--53
S. Yin and
Y. Kim and
X. Han and
H. Barnaby and
S. Yu and
Y. Luo and
W. He and
X. Sun and
J. Kim and
J. Seo Monolithically Integrated RRAM- and
CMOS-Based In-Memory Computing
Optimizations for Efficient Deep
Learning . . . . . . . . . . . . . . . . 54--63
M. Jagasivamani and
C. Walden and
D. Singh and
L. Kang and
S. Li and
M. Asnaashari and
S. Dubois and
B. Jacob and
D. Yeung Analyzing the Monolithic Integration of
a ReRAM-Based Main Memory Into a CPU's
Die . . . . . . . . . . . . . . . . . . 64--72
M. Donato and
L. Pentecost and
D. Brooks and
G. Wei MEMTI: Optimizing On-Chip Nonvolatile
Storage for Visual Multitask Inference
at the Edge . . . . . . . . . . . . . . 73--81
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 81--81
S. Greenstein Antitrust in Three Acts . . . . . . . . 82--84
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous COMPSAC 2020 . . . . . . . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. K. John Connectivity! Connectivity!
Connectivity! May You Be More Connected
Than Ever!! . . . . . . . . . . . . . . 4--5
R. E. Grant and
K. Hamidouche Hot Interconnects 26 . . . . . . . . . . 6--7
G. Maglione-Mathey and
J. Escudero-Sahuquillo and
P. J. Garcia and
F. J. Quiles and
J. Duato Path2SL: Leveraging InfiniBand Resources
to Reduce Head-of-Line Blocking in Fat
Trees . . . . . . . . . . . . . . . . . 8--14
Anonymous Top Technology Trends for 2020 Featured
in \booktitleComputer . . . . . . . . . 14--14
R. Farjadrad and
M. Kuemerle and
B. Vinnakota A Bunch-of-Wires (BoW) Interface for
Interchiplet Communication . . . . . . . 15--24
Anonymous IEEE Computer Society Has You Covered! 24--24
J. Lant and
J. Navaridas and
M. Luján and
J. Goodacre Toward FPGA-Based HPC: Advancing
Interconnect Technologies . . . . . . . 25--34
Anonymous \booktitleIEEE Transactions on Computers 34--34
A. A. Awan and
A. Jain and
C. Chu and
H. Subramoni and
D. K. Panda Communication Profiling and
Characterization of Deep-Learning
Workloads on Clusters With
High-Performance Interconnects . . . . . 35--43
Anonymous \booktitleIEEE Security & Privacy . . . . 43--43
J. Gliksberg and
A. Capra and
A. Louvet and
P. J. García and
D. Sohier High-Quality Fault Resiliency in Fat
Trees . . . . . . . . . . . . . . . . . 44--49
S. Roy and
A. Kaushik and
R. Agrawal and
J. Gergen and
W. Rouwet and
J. Arends A High-Throughput Network Processor
Architecture for Latency-Critical
Applications . . . . . . . . . . . . . . 50--56
Anonymous \booktitleIT Professional . . . . . . . 56--56
P. Stanley-Marbell and
M. Rinard Warp: A Hardware Platform for Efficient
Multimodal Sensing With Adaptive
Approximation . . . . . . . . . . . . . 57--66
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 66--66
H. Mahdiani and
A. Khadem and
A. Ghanbari and
M. Modarressi and
F. Fattahi-Bayat and
M. Daneshtalab $ \Delta $ NN: Power-Efficient Neural
Network Acceleration Using Differential
Weights . . . . . . . . . . . . . . . . 67--74
H. Cai and
J. Lin and
Y. Lin and
Z. Liu and
K. Wang and
T. Wang and
L. Zhu and
S. Han AutoML for Architecting Efficient and
Specialized Neural Networks . . . . . . 75--82
M. Ahmad and
H. Dogan and
J. A. Joao and
O. Khan In-Hardware Moving Compute to Data Model
to Accelerate Thread Synchronization on
Large Multicores . . . . . . . . . . . . 83--92
Anonymous Keep Your Career Options Open . . . . . 93--93
S. Greenstein The Vital Two Percent . . . . . . . . . 94--96
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous HOST 2020 . . . . . . . . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. K. John Did ML Chips Heat Up the Chip Design
Arena? . . . . . . . . . . . . . . . . . 4--5
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 5--5
C. Kozyrakis and
I. Bratt The Hot Chips Renaissance . . . . . . . 6--7
P. Mattson and
V. J. Reddi and
C. Cheng and
C. Coleman and
G. Diamos and
D. Kanter and
P. Micikevicius and
D. Patterson and
G. Schmuelling and
H. Tang and
G. Wei and
C. Wu MLPerf: An Industry Standard Benchmark
Suite for Machine Learning Performance 8--16
E. Medina and
E. Dagan Habana Labs Purpose-Built AI Inference
and Training Processor Architectures:
Scaling AI Training Systems Using
Standard Ethernet With Gaudi Processor 17--24
E. Talpes and
D. D. Sarma and
G. Venkataramanan and
P. Bannon and
B. McGee and
B. Floering and
A. Jalote and
C. Hsiong and
S. Arora and
A. Gorti and
G. S. Sachdev Compute Solution for Tesla's Full
Self-Driving Computer . . . . . . . . . 25--35
J. Burgess RTX on the NVIDIA Turing GPU . . . . . . 36--44
D. Suggs and
M. Subramony and
D. Bouvier The AMD Zen 2 Processor . . . . . . . . 45--52
Anonymous \booktitleIEEE Security & Privacy . . . . 52--52
A. Pellegrini and
N. Stephens and
M. Bruce and
Y. Ishii and
J. Pusdesris and
A. Raja and
C. Abernathy and
J. Koppanalil and
T. Ringe and
A. Tummala and
J. Jalal and
M. Werkheiser and
A. Kona The Arm Neoverse N1 Platform: Building
Blocks for the Next-Gen Cloud-to-Edge
Infrastructure SoC . . . . . . . . . . . 53--62
M. Wade and
E. Anderson and
S. Ardalan and
P. Bhargava and
S. Buchbinder and
M. L.Davenport and
J. Fini and
H. Lu and
C. Li and
R. Meade and
C. Ramamurthy and
M. Rust and
F. Sedgwick and
V. Stojanovic and
D. Van Orden and
C. Zhang and
C. Sun and
S. Y. Shumarayev and
C. O'Keeffe and
T. T. Hoang and
D. Kehlet and
R. V. Mahajan and
M. T. Guzy and
A. Chan and
T. Tran TeraPHY: A Chiplet Technology for
Low-Power, High-Bandwidth In-Package
Optical I/O . . . . . . . . . . . . . . 63--71
Anonymous \booktitleIT Professional . . . . . . . 71--71
Anonymous IEEE Quantum Week 2020 . . . . . . . . . 72--72
Anonymous COMPSAC 2020 . . . . . . . . . . . . . . 73--73
S. Greenstein Expertise at Our Fingertips . . . . . . 74--76
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society Has You Covered! C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. K. John Enjoy These Top Picks, While You Work
From Home! . . . . . . . . . . . . . . . 4--5
H. Kim The 2019 Top Picks in Computer
Architecture . . . . . . . . . . . . . . 6--9
Y. Gan and
Y. Zhang and
D. Cheng and
A. Shetty and
P. Rathi and
N. Katarki and
A. Bruno and
J. Hu and
B. Ritchken and
B. Jackson and
K. Hu and
M. Pancholi and
Y. He and
B. Clancy and
C. Colen and
F. Wen and
C. Leung and
S. Wang and
L. Zaruvinsky and
M. Espinosa and
R. Lin and
Z. Liu and
J. Padilla and
C. Delimitrou Unveiling the Hardware and Software
Implications of Microservices in Cloud
and Edge Systems . . . . . . . . . . . . 10--19
H. Kwon and
P. Chatarasi and
V. Sarkar and
T. Krishna and
M. Pellauer and
A. Parashar MAESTRO: A Data-Centric Approach to
Understand Reuse, Performance, and
Hardware Cost of DNN Mappings . . . . . 20--29
Y. Leng and
J. Huang and
C. Chen and
Q. Sun and
Y. Zhu Energy-Efficient Video Processing for
Virtual Reality . . . . . . . . . . . . 30--36
V. Dadu and
J. Weng and
S. Liu and
T. Nowatzki Towards General-Purpose Acceleration:
Finding Structure in Irregularity . . . 37--46
Y. Hu and
M. Lokhandwala and
T. I and
H. Tseng Varifocal Storage: Dynamic
Multiresolution Data Storage . . . . . . 47--55
Anonymous IEEE Computer Society: Call for Papers 55--55
N. P. Nagendra and
G. Ayers and
D. I. August and
H. K. Cho and
S. Kanev and
C. Kozyrakis and
T. Krishnamurthy and
H. Litz and
T. Moseley and
P. Ranganathan AsmDB: Understanding and Mitigating
Front-End Stalls in Warehouse-Scale
Computers . . . . . . . . . . . . . . . 56--63
P. Gokhale and
J. M. Baker and
C. Duckering and
F. T. Chong and
N. C. Brown and
K. R. Brown Extending the Frontier of Quantum
Computers With Qutrits . . . . . . . . . 64--72
P. Murali and
N. M. Linke and
M. Martonosi and
A. J. Abhari and
N. H. Nguyen and
C. H. Alderete Architecting Noisy Intermediate-Scale
Quantum Computers: A Real-System Study 73--80
J. Yu and
M. Yan and
A. Khyzha and
A. Morrison and
J. Torrellas and
C. W. Fletcher Speculative Taint Tracking (STT): A
Comprehensive Protection for
Speculatively Accessed Data . . . . . . 81--90
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 90--90
D. Skarlatos and
M. Yan and
B. Gopireddy and
R. Sprabery and
J. Torrellas and
C. W. Fletcher MicroScope: Enabling Microarchitectural
Replay Attacks . . . . . . . . . . . . . 91--98
J. Yu and
L. Hsiung and
M. E. Hajj and
C. W. Fletcher Creating Foundations for Secure
Microarchitectures With Data-Oblivious
ISA Extensions . . . . . . . . . . . . . 99--107
D. Dangwal and
W. Cui and
J. McMahan and
T. Sherwood Trace Wringing for Program Trace Privacy 108--115
Anonymous \booktitleIEEE Security & Privacy . . . . 115--115
Anonymous HOST 2020 . . . . . . . . . . . . . . . 116--116
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . 117--117
S. Greenstein Pandemics and the Dismal Technology
Economy . . . . . . . . . . . . . . . . 118--120
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous IEEE Quantum Week . . . . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society Has You Covered! C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. K. John Agile Hardware Design . . . . . . . . . 4--5
Y. Bao and
T. E. Carlson Agile and Open-Source Hardware . . . . . 6--9
Anonymous \booktitleIT Professional . . . . . . . 9--9
A. Amid and
D. Biancolin and
A. Gonzalez and
D. Grubb and
S. Karandikar and
H. Liew and
A. Magyar and
H. Mao and
A. Ou and
N. Pemberton and
P. Rigge and
C. Schmidt and
J. Wright and
J. Zhao and
Y. S. Shao and
K. Asanovi\vc and
B. Nikoli\vc Chipyard: Integrated Design, Simulation,
and Implementation Framework for Custom
SoCs . . . . . . . . . . . . . . . . . . 10--21
Anonymous IEEE Computer Society: Call for Papers 21--21
J. Balkind and
T. Chang and
P. J. Jackson and
G. Tziantzioulis and
A. Li and
F. Gao and
A. Lavrov and
G. Chirkov and
J. Tu and
M. Shahrad and
D. Wentzlaff OpenPiton at 5: A Nexus for Open and
Agile Hardware Design . . . . . . . . . 22--31
P. N. Whatmough and
M. Donato and
G. G. Ko and
S. K. Lee and
D. Brooks and
G. Wei CHIPKIT: An Agile, Reusable Open-Source
Framework for Rapid Test Chip
Development . . . . . . . . . . . . . . 32--40
X. Tang and
E. Giacomin and
B. Chauviere and
A. Alacchi and
P. Gaillardon OpenFPGA: An Open-Source Framework for
Agile Prototyping Customizable FPGAs . . 41--48
K. E. Murray and
M. A. Elgammal and
V. Betz and
T. Ansell and
K. Rothman and
A. Comodi SymbiFlow and VPR: An Open-Source Design
Flow for Commercial and Novel FPGAs . . 49--57
S. Jiang and
P. Pan and
Y. Ou and
C. Batten PyMTL3: a Python Framework for
Open-Source Hardware Modeling,
Generation, Simulation, and Verification 58--66
S. Wang and
R. T. Possignolo and
H. B. Skinner and
J. Renau LiveHD: A Productive Live Hardware
Development Flow . . . . . . . . . . . . 67--75
D. Dangwal and
G. Tzimpragos and
T. Sherwood Agile Hardware Development and
Instrumentation With PyRTL . . . . . . . 76--84
L. Jia and
L. Lu and
X. Wei and
Y. Liang Generating Systolic Array Accelerators
With Reusable Blocks . . . . . . . . . . 85--92
Anonymous \booktitleIEEE Security & Privacy . . . . 92--92
D. Petrisko and
F. Gilani and
M. Wyse and
D. C. Jung and
S. Davidson and
P. Gao and
C. Zhao and
Z. Azad and
S. Canakci and
B. Veluri and
T. Guarino and
A. Joshi and
M. Oskin and
M. B. Taylor BlackParrot: An Agile Open-Source RISC-V
Multicore for Accelerator SoCs . . . . . 93--102
L. Vega and
J. Roesch and
J. McMahan and
L. Ceze LastLayer: Toward Hardware and Software
Continuous Integration . . . . . . . . . 103--111
Anonymous \booktitleIEEE Security & Privacy . . . . 111--111
S. Beamer A Case for Accelerating Software RTL
Simulation . . . . . . . . . . . . . . . 112--119
J. Peltenburg and
J. Van Straten and
M. Brobbel and
Z. Al-Ars and
H. P. Hofstee Tydi: An Open Specification for Complex
Data Structures Over Hardware Streams 120--130
Anonymous Evolving Career Opportunities Need Your
Skills . . . . . . . . . . . . . . . . . 131--131
Anonymous HOST 2020 . . . . . . . . . . . . . . . 132--132
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . 133--133
S. Greenstein Uncomfortable Economic Waters . . . . . 134--136
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous IEEE Quantum Week . . . . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society Has You Covered! C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. Kurian John Machine Learning for Systems, Biological
Computing, and More . . . . . . . . . . 4--5
H. Litz and
M. Hashemi Machine Learning for Systems . . . . . . 6--7
M. Maas A Taxonomy of ML for Systems Problems 8--16
V. Joseph and
G. L. Gopalakrishnan and
S. Muralidharan and
M. Garland and
A. Garg A Programmable Approach to Neural
Network Compression . . . . . . . . . . 17--25
Y. Zhou and
S. Roy and
A. Abdolrashidi and
D. L. Wong and
P. Ma and
Q. Xu and
A. Mirhoseini and
J. Laudon A Single-Shot Generalized Device
Placement for Large Dataflow Graphs . . 26--36
Anonymous IEEE Computer Society: Call for Papers 36--36
A. T. Elthakeb and
P. Pilligundla and
F. Mireshghallah and
A. Yazdanbakhsh and
H. Esmaeilzadeh ReLeQ : A Reinforcement Learning
Approach for Automatic Deep Quantization
of Neural Networks . . . . . . . . . . . 37--45
Anonymous \booktitleIT Professional: Call for
Articles . . . . . . . . . . . . . . . . 45--45
C. Fu and
H. Chen and
Z. Yang and
F. Koushanfar and
Y. Tian and
J. Zhao Enhancing Model Parallelism in Neural
Architecture Search for Multidevice
System . . . . . . . . . . . . . . . . . 46--55
Anonymous \booktitleIEEE Security & Privacy . . . . 55--55
K. Wang and
H. Zheng and
A. Louri TSA-NoC: Learning-Based Threat Detection
and Mitigation for Secure
Network-on-Chip Architecture . . . . . . 56--63
A. Bhattacharjee Biology and Systems Interactions . . . . 64--64
M. Alser and
Z. Bingöl and
D. S. Cali and
J. Kim and
S. Ghose and
C. Alkan and
O. Mutlu Accelerating Genome Analysis: a Primer
on an Ongoing Journey . . . . . . . . . 65--75
A. Stephenson and
M. Willsey and
J. McBride and
S. Newman and
B. Nguyen and
C. Takahashi and
K. Strauss and
L. Ceze PurpleDrop: a Digital
Microfluidics-Based Platform for Hybrid
Molecular--Electronics Applications . . 76--86
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 86--86
Anonymous IEEE Computer Society Jobs Board . . . . 87--87
S. Greenstein Triggers, Transmissions, and Adjustments 88--90
Anonymous IEEE Computer Society . . . . . . . . . C3--C3
Anonymous IEEE Quantum Week . . . . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous CVPR2020: Thank You to Our Sponsors! . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. Kurian John Chip Design 2020 . . . . . . . . . . . . 4--5
J. P. Kulkarni Chip Design 2020 . . . . . . . . . . . . 6--7
A. Ankit and
I. Chakraborty and
A. Agrawal and
M. Ali and
K. Roy Circuits and Architectures for In-Memory
Computing-Based Machine Learning
Accelerators . . . . . . . . . . . . . . 8--22
Anonymous IEEE Computer Society: Call for Papers 22--22
B. Khailany and
H. Ren and
S. Dai and
S. Godil and
B. Keller and
R. Kirby and
A. Klinefelter and
R. Venkatesan and
Y. Zhang and
B. Catanzaro and
W. J. Dally Accelerating Chip Design With Machine
Learning . . . . . . . . . . . . . . . . 23--32
A. Keshavarzi and
K. Ni and
W. Van Den Hoek and
S. Datta and
A. Raychowdhury FerroElectronics for Edge Intelligence 33--48
Anonymous IEEE Pervasive Computing: Call for
Articles . . . . . . . . . . . . . . . . 48--48
D. A. Patterson and
Y. S. Shao Commercial Products . . . . . . . . . . 49--49
C. Jacobi and
C. Webb History of IBM Z Mainframe Processors 50--58
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 58--58
R. Rangan and
N. Turakhia and
A. Joly Countering Load-to-Use Stalls in the
NVIDIA Turing GPU . . . . . . . . . . . 59--66
Anonymous \booktitleITProfessional: Call for
Articles . . . . . . . . . . . . . . . . 66--66
L. Shalev and
H. Ayoub and
N. Bshara and
E. Sabbag A Cloud-Optimized Transport Protocol for
Elastic and Scalable HPC . . . . . . . . 67--73
J. Knechtel and
S. Patnaik and
M. Nabeel and
M. Ashraf and
Y. S. Chauhan and
J. Henkel and
O. Sinanoglu and
H. Amrouch Power Side-Channel Attacks in Negative
Capacitance Transistor . . . . . . . . . 74--84
Anonymous \booktitleIEEE Security & Privacy . . . . 84--84
Anonymous IEEE Computer Society . . . . . . . . . 85--85
S. Greenstein The Fox and Shepherd Problem . . . . . . 86--88
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous \booktitleComputingEdge . . . . . . . . C4--C4
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
L. K. John Connectivity More Needed Than Ever
Before . . . . . . . . . . . . . . . . . 4--5
R. E. Grant and
M. G. Venkata Hot Interconnects 27 . . . . . . . . . . 6--7
V. Krishnan and
O. Serres and
M. Blocksome Configurable Network Protocol
Accelerator (COPA) . . . . . . . . . . . 8--14
K. Tanaka and
Y. Arikawa and
T. Ito and
K. Morita and
N. Nemoto and
K. Terada and
J. Teramoto and
T. Sakamoto Distributed Deep Learning With GPU-FPGA
Heterogeneous Computing . . . . . . . . 15--22
D. Das Sharma PCI Express 6.0 Specification: a
Low-Latency, High-Bandwidth,
High-Reliability, and Cost-Effective
Interconnect With 64.0 GT/s PAM-4
Signaling . . . . . . . . . . . . . . . 23--29
B. Vinnakota and
I. Agarwal and
K. Drucker and
D. Jani and
G. Miller and
M. Mittal and
R. Wang The Open Domain-Specific Architecture 30--36
C. Olmedilla and
J. Escudero-Sahuquillo and
P. J. Garcia-Garcia and
F. Alfaro-Cortés and
J. L. Sánchez and
F. J. Quiles and
W. Sun and
X. Yu and
Y. Xu and
J. Duato DVL-Lossy: Isolating Congesting Flows to
Optimize Packet Dropping in Lossy
Data-Center Networks . . . . . . . . . . 37--44
R. Ben Haim and
O. Rottenstreich Reliable and Time-Efficient Virtualized
Function Placement . . . . . . . . . . . 45--53
S. Ardalan and
R. Farjadrad and
M. Kuemerle and
K. Poulton and
S. Subramaniam and
B. Vinnakota An Open Inter-Chiplet Communication
Link: Bunch of Wires (BoW) . . . . . . . 54--60
I. Tsiokanos and
G. Karakonstantis ExHero: Execution History-Aware
Error-Rate Estimation in Pipelined
Designs . . . . . . . . . . . . . . . . 61--68
Anonymous IEEE Computer Society: Call for Papers 68--68
D. Bertozzi and
G. Miorandi and
A. Ghiribaldi and
W. Burleson and
G. Sadowski and
K. Bhardwaj and
W. Jiang and
S. M. Nowick Cost-Effective and Flexible Asynchronous
Interconnect Technology for GALS Systems 69--81
Anonymous IEEE Computer Society Jobs Board . . . . 82--82
R. Rangan and
N. Turakhia and
A. Joly Corrections to Countering Load-to-Use
Stalls in the NVIDIA Turing GPU . . . . 83--83
Anonymous IEEE Computer Society Volunteer Service
Awards . . . . . . . . . . . . . . . . . 84--84
Anonymous IEEE Computer Society . . . . . . . . . 85--85
S. Greenstein Technology Policy Dilemmas in the New
Administration . . . . . . . . . . . . . 86--88
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Has You Covered! C4--C4
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of contents . . . . . . . . . . . 2--3
L. Kurian John CPUs, GPUs, and More From Hot Chips 32 4--5
P. Raina and
C. Young Best Papers From Hot Chips 32 . . . . . 6--6
W. J. Starke and
B. W. Thompto and
J. A. Stuecheli and
J. E. Moreira IBM's POWER10 Processor . . . . . . . . 7--14
R. Sugumar and
M. Shah and
R. Ramirez Marvell ThunderX3: Next-Generation
Arm-Based Server Processor . . . . . . . 15--21
Anonymous \booktitleIEEE Transactions on
Sustainable Computing . . . . . . . . . 21--21
M. Grossman and
J. Andrews The Xbox Series X System Architecture 22--28
J. Choquette and
W. Gandhi and
O. Giroux and
N. Stam and
R. Krashinsky NVIDIA A100 Tensor Core GPU: Performance
and Innovation . . . . . . . . . . . . . 29--35
F. Zaruba and
F. Schuiki and
L. Benini Manticore: A 4096-Core RISC-V Chiplet
Architecture for Ultraefficient
Floating-Point Computing . . . . . . . . 36--42
M. Galles and
F. Matus Pensando Distributed Services
Architecture . . . . . . . . . . . . . . 43--49
J. Vasiljevic and
L. Bajic and
D. Capalija and
S. Sokorac and
D. Ignjatovic and
L. Bajic and
M. Trajkovic and
I. Hamer and
I. Matosevic and
A. Cejkov and
U. Aydonat and
T. Zhou and
S. Z. Gilani and
A. Paiva and
J. Chu and
D. Maksimovic and
S. A. Chin and
Z. Moudallal and
A. Rakhmati and
S. Nijjar and
A. Bhullar and
B. Drazic and
C. Lee and
J. Sun and
K. -M. Kwong and
J. Connolly and
M. Dooley and
H. Farooq and
J. Y. T. Chen and
M. Walker and
K. Dabiri and
K. Mabee and
R. S. Lal and
N. Rajatheva and
R. Retnamma and
S. Karodi and
D. Rosen and
E. Munoz and
A. Lewycky and
A. Knezevic and
R. Kim and
A. Rui and
A. Drouillard and
D. Thompson Compute Substrate for Software 2.0 . . . 50--55
T. Norrie and
N. Patil and
D. H. Yoon and
G. Kurian and
S. Li and
J. Laudon and
C. Young and
N. Jouppi and
D. Patterson The Design Process for Google's Training
Chips: TPUv2 and TPUv3 . . . . . . . . . 56--63
A. Cheikh and
S. Sordillo and
A. Mastrandrea and
F. Menichelli and
G. Scotti and
M. Olivieri Klessydra-T: Designing Vector
Coprocessors for Multithreaded
Edge-Computing Cores . . . . . . . . . . 64--71
M. Mattioli and
A. Lahtiranta Hidden Potential Within Video Game
Consoles . . . . . . . . . . . . . . . . 72--77
L. A. Barroso A Brief History of Warehouse-Scale
Computing . . . . . . . . . . . . . . . 78--83
Anonymous \booktitleIT Professional . . . . . . . 83--83
Anonymous IEEE Computer Society Information . . . 84--84
Anonymous Subscribe to CiSE Today! . . . . . . . . 85--85
S. Greenstein The Economics of Confrontational
Conversation . . . . . . . . . . . . . . 86--88
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Has You Covered! C4--C4
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Top Picks From Year 2020 . . . . . . . . 4--5
Daniel A. Jimenez Top Picks From the 2020 Computer
Architecture Conferences . . . . . . . . 6--9
Vijay Janapa Reddi and
Christine Cheng and
David Kanter and
Peter Mattson and
Guenther Schmuelling and
Carole-Jean Wu The Vision Behind MLPerf: Understanding
AI Inference Performance . . . . . . . . 10--18
Koki Ishida and
Ilkwon Byun and
Ikki Nagaoka and
Kosuke Fukumitsu and
Masamitsu Tanaka and
Satoshi Kawakami and
Teruo Tanimoto and
Takatsugu Ono and
Jangwoo Kim and
Koji Inoue Superconductor Computing for Neural
Networks . . . . . . . . . . . . . . . . 19--26
Po-An Tsai and
Andres Sanchez and
Christopher W. Fletcher and
Daniel Sanchez Leaking Secrets Through Compressed
Caches . . . . . . . . . . . . . . . . . 27--33
Akshitha Sriraman and
Abhishek Dhanotia Understanding Acceleration Opportunities
at Hyperscale . . . . . . . . . . . . . 34--41
Tae Jun Ham and
Yejin Lee and
Seong Hoon Seo and
U. Gyeong Song and
Jae W. Lee and
David Bruns-Smith and
Brendan Sweeney and
Krste Asanovic and
Young H. Oh and
Lisa Wu Wills Accelerating Genomic Data Analytics With
Composable Hardware Acceleration
Framework . . . . . . . . . . . . . . . 42--49
Di Wu and
Jingjie Li and
Ruokai Yin and
Hsuan Hsiao and
Younghyun Kim and
Joshua San Miguel uGEMM: Unary Computing for GEMM
Applications . . . . . . . . . . . . . . 50--56
Dimitrios Skarlatos and
Umur Darbaz and
Bhargava Gopireddy and
Nam Sung Kim and
Josep Torrellas BabelFish: Fusing Address Translations
for Containers . . . . . . . . . . . . . 57--62
Zixuan Wang and
Xiao Liu and
Jian Yang and
Theodore Michailidis and
Steven Swanson and
Jishen Zhao Characterizing and Modeling Nonvolatile
Memory Systems . . . . . . . . . . . . . 63--70
Anonymous IEEE Computer Society: Call for Papers 70--70
Georgios Tzimpragos and
Jennifer Volk and
Dilip Vasudevan and
Nestan Tsiskaridze and
George Michelogiannakis and
Advait Madhavan and
John Shalf and
Timothy Sherwood Temporal Computing With Superconductors 71--79
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 79--79
Ilkwon Byun and
Dongmoon Min and
Gyuhyeon Lee and
Seongmin Na and
Jangwoo Kim A Next-Generation Cryogenic Processor
Architecture . . . . . . . . . . . . . . 80--86
Ioannis Karageorgos and
Karthik Sriram and
Ján Veselý and
Nick Lindsay and
Xiayuan Wen and
Michael Wu and
Marc Powell and
David Borton and
Rajit Manohar and
Abhishek Bhattacharjee Balancing Specialized Versus Flexible
Computation in Brain--Computer
Interfaces . . . . . . . . . . . . . . . 87--94
Jonathan M. Baker and
Casey Duckering and
David I. Schuster and
Frederic T. Chong Virtual Logical Qubits: a Compact
Architecture for Fault-Tolerant Quantum
Computing . . . . . . . . . . . . . . . 95--101
Anonymous IEEE Computer Society Jobs Board . . . . 102--102
Michael Mattioli and
Tom Garrison and
Baiju V. Patel The Next Security Frontier: Taking the
Mystery Out of the Supply Chain . . . . 103--107
Anonymous IEEE Computer Society . . . . . . . . . 108--108
Anonymous IEEE Computer Society Volunteer Service
Awards . . . . . . . . . . . . . . . . . 109--109
Shane Greenstein Remote Work . . . . . . . . . . . . . . 110--112
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Has You Covered! C4--C4
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John FPGA Computing and More! . . . . . . . . 4--5
Maya Gokhale and
Lesley Shannon FPGA Computing . . . . . . . . . . . . . 6--7
Davide Giri and
Kuan-Lin Chiu and
Guy Eichler and
Paolo Mantovani and
Luca P. Carloni Accelerator Integration for Open-Source
SoC Design . . . . . . . . . . . . . . . 8--14
Nuno Paulino and
João Bispo and
João C. Ferreira and
João M. P. Cardoso A Binary Translation Framework for
Automated Hardware Generation . . . . . 15--23
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 23--23
Nikolaos Alachiotis and
Andreas Brokalakis and
Vasilis Amourgianos and
Sotiris Ioannidis and
Pavlos Malakonakis and
Tasos Bokalidis Accelerating Phylogenetics Using FPGAs
in the Cloud . . . . . . . . . . . . . . 24--30
Junbin Wang and
Shaoxia Fang and
Xi Wang and
Jiangsha Ma and
Taobo Wang and
Yi Shan High-Performance Mixed-Low-Precision CNN
Inference Accelerator on FPGA . . . . . 31--38
Gagandeep Singh and
Mohammed Alser and
Damla Senol Cali and
Dionysios Diamantopoulos and
Juan Gómez-Luna and
Henk Corporaal and
Onur Mutlu FPGA-Based Near-Memory Acceleration of
Modern Data-Intensive Applications . . . 39--48
He Li and
Yaru Pang FPGA-Accelerated Quantum Computing
Emulation and Quantum Key Distillation 49--57
David Biancolin and
Albert Magyar and
Sagar Karandikar and
Alon Amid and
Borivoje Nikoli and
Jonathan Bachrach and
Krste Asanovi Accessible, FPGA Resource-Optimized
Simulation of Multiclock Systems in
FireSim . . . . . . . . . . . . . . . . 58--66
David Biancolin and
Albert Magyar and
Sagar Karandikar and
Alon Amid and
Borivoje Nikoli and
Jonathan Bachrach and
Krste Asanovi Accessible, FPGA Resource-Optimized
Simulation of Multiclock Systems in
FireSim . . . . . . . . . . . . . . . . 58--66
Hammam Kattan and
Sung Woo Chung and
Jörg Henkel and
Hussam Amrouch On-Demand Mobile CPU Cooling With
Thin-Film Thermoelectric Array . . . . . 67--73
Hammam Kattan and
Sung Woo Chung and
Jörg Henkel and
Hussam Amrouch On-Demand Mobile CPU Cooling With
Thin-Film Thermoelectric Array . . . . . 67--73
Joshua J. Yi Recent Patents for Leading Computer
Architecture Companies . . . . . . . . . 74--77
Michael Mattioli Rome to Milan, AMD Continues Its Tour of
Italy . . . . . . . . . . . . . . . . . 78--83
Anonymous IEEE Computer Society: Call for Papers 83--83
Anonymous IEEE Computer Society . . . . . . . . . 84--84
Anonymous IEEE Computer Society Jobs Board . . . . 85--85
Shane Greenstein Shortages of Integrated Circuits . . . . 86--88
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Has You Covered! C4--C4
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Quantum Computing and More! . . . . . . 4--5
Ulya R. Karpuzcu Special Issue on Quantum Computing . . . 6--7
Moinuddin Qureshi and
Swamit Tannu Quantum Computing and the Design of the
Ultimate Accelerator . . . . . . . . . . 8--14
Anonymous Charles Babbage Award . . . . . . . . . 14--14
Travis S. Humble and
Alexander McCaskey and
Dmitry I. Lyakh and
Meenambika Gowrishankar and
Albert Frisch and
Thomas Monz Quantum Computers for High-Performance
Computing . . . . . . . . . . . . . . . 15--23
Koen Bertels and
Aritra Sarkar and
Imran Ashraf Quantum Computing From NISQ to PISQ . . 24--32
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 32--32
Teague Tomesh and
Margaret Martonosi Quantum Codesign . . . . . . . . . . . . 33--40
Jonathan M. Baker and
Frederic T. Chong Emerging Technologies for Quantum
Computing . . . . . . . . . . . . . . . 41--47
Santiago Rodrigo and
Sergi Abadal and
Eduard Alarcón and
Medina Bandic and
Hans van Someren and
Carmen G. Almudéver On Double Full-Stack
Communication-Enabled Architectures for
Multicore Quantum Computers . . . . . . 48--56
Leon Riesebos and
Brad Bondurant and
Kenneth R. Brown Universal Graph-Based Scheduling for
Quantum Systems . . . . . . . . . . . . 57--65
Hsien-Hsin S. Lee Special Issue on Commercial Products
2021 . . . . . . . . . . . . . . . . . . 66--66
Jing Xia and
Chuanning Cheng and
Xiping Zhou and
Yuxing Hu and
Peter Chun Kunpeng 920: The First 7-nm
Chiplet-Based 64-Core ARM SoC for Cloud
Services . . . . . . . . . . . . . . . . 67--75
Alex Gendler and
Ernest Knoll and
Yiannakis Sazeides I-DVFS: Instantaneous Frequency Switch
During Dynamic Voltage and Frequency
Scaling . . . . . . . . . . . . . . . . 76--84
Jianbo Dong and
Shaochuang Wang and
Fei Feng and
Zheng Cao and
Heng Pan and
Lingbo Tang and
Pengcheng Li and
Hao Li and
Qianyuan Ran and
Yiqun Guo and
Shanyuan Gao and
Xin Long and
Jie Zhang and
Yong Li and
Zhisheng Xia and
Liuyihan Song and
Yingya Zhang and
Pan Pan and
Guohui Wang and
Xiaowei Jiang ACCL: Architecting Highly Scalable
Distributed Training Systems With Highly
Efficient Collective Communication
Library . . . . . . . . . . . . . . . . 85--92
Zhaoxia Deng and
Jongsoo Park and
Ping Tak Peter Tang and
Haixin Liu and
Jie Yang and
Hector Yuen and
Jianyu Huang and
Daya Khudia and
Xiaohan Wei and
Ellie Wen and
Dhruv Choudhary and
Raghuraman Krishnamoorthi and
Carole-Jean Wu and
Satish Nadathur and
Changkyu Kim and
Maxim Naumov and
Sam Naghshineh and
Mikhail Smelyanskiy Low-Precision Hardware Architectures
Meet Recommendation Model Inference at
Scale . . . . . . . . . . . . . . . . . 93--100
Lukasz Wesolowski and
Bilge Acun and
Valentin Andrei and
Adnan Aziz and
Gisle Dankel and
Christopher Gregg and
Xiaoqiao Meng and
Cyril Meurillon and
Denis Sheahan and
Lei Tian and
Janet Yang and
Peifeng Yu and
Kim Hazelwood Datacenter-Scale Analysis and
Optimization of GPU Machine Learning
Workloads . . . . . . . . . . . . . . . 101--112
Anonymous IEEE Computer Society: Call for Papers 112--112
Anonymous IEEE Computer Society: Volunteer Service
Awards . . . . . . . . . . . . . . . . . 113--113
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies . . . . 114--123
Anonymous \booktitleITProfessional: Call for
Articles . . . . . . . . . . . . . . . . 123--123
Anonymous IEEE Computer Society Jobs Board . . . . 124--124
Michael Mattioli PCs Take a Page From Xbox With Pluton 125--128
Anonymous IEEE Computer Society . . . . . . . . . 129--129
Shane Greenstein Economic Dependencies in Integrated
Circuits . . . . . . . . . . . . . . . . 130--132
Anonymous \booktitleIEEE Transactions on
Sustainable Computing . . . . . . . . . 132--132
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Has You Covered! C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous [Masthead] . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--4
Lizy Kurian John Microprocessor at 50: Looking Back and
Looking Forward . . . . . . . . . . . . 5--9
Lizy Kurian John and
Vijaykrishnan Narayanan Microprocessor at 50: A Time to
Celebrate and Energize for the Future 10--12
Anonymous IEEE Computer Society: Call for Papers 12--12
Lizy Kurian John and
Vijaykrishnan Narayanan Microprocessor at 50: Industry Leaders
Speak . . . . . . . . . . . . . . . . . 13--15
Anonymous \booktitleIT Professional: Call for
Articles . . . . . . . . . . . . . . . . 15--15
Federico Faggin The Birth of the Microprocessor . . . . 16--19
John L. Hennessy The 50 Year History of the
Microprocessor as Five Technology Eras 20--21
Randy Steck The Middle-Aged Microprocessor . . . . . 22--28
Dave Christie and
Mike Clark and
Mike Schulte What Made Us Stronger: An Inside Look
Back at the History of AMD
Microprocessor Development . . . . . . . 29--36
Robert P. Colwell The Origin of Intel's Micro-Ops . . . . 37--41
William J. Dally and
Stephen W. Keckler and
David B. Kirk Evolution of the Graphics Processing
Unit (GPU) . . . . . . . . . . . . . . . 42--51
Anonymous Computing in Science & Engineering . . . 51--51
Gary Lauterbach The Path to Successful Wafer-Scale
Integration: The Cerebras Story . . . . 52--57
Richard Grisenthwaite The Milestones That Define Arm's Past,
Present, and Future . . . . . . . . . . 58--67
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 67--67
Charles Webb Microprocessor Advances and the
Mainframe Legacy . . . . . . . . . . . . 68--70
Anonymous \booktitleIEEE Transactions on
Sustainable Computing . . . . . . . . . 70--70
Pradip Bose The POWER Processor Family: A Historical
Perspective From the Viewpoint of
Presilicon Modeling . . . . . . . . . . 71--77
Ravi Iyer and
Vivek De and
Ramesh Illikkal and
David Koufaty and
Bhushan Chitlur and
Andrew Herdrich and
Muhammad Khellah and
Fatih Hamzaoglu and
Eric Karl Advances in Microprocessor Cache
Architectures Over the Last 25 Years . . 78--88
G. Glenn Henry From Mainframes to Microprocessors . . . 89--96
Anonymous \booktitleIEEE Transactions on Big Data 96--96
K. Raghu Raghunathan History of Microcontrollers: First 50
Years . . . . . . . . . . . . . . . . . 97--104
Mark McDermott Motorola MC68332: One of the First True
SoCs . . . . . . . . . . . . . . . . . . 105--106
Anonymous \booktitleIEEE Security & Privacy . . . . 106--106
Steven Van Singel The Renesas Automotive Story in the
History of the Microprocessor . . . . . 107--108
Anonymous Call for Articles: \booktitleIEEE
Pervasive Computing . . . . . . . . . . 108--108
Bob Martin 8 Bits in an IoT World: Legacy Chips
Simplify Advanced Architecture
Interfaces . . . . . . . . . . . . . . . 109--111
Karthik Swaminathan and
Augusto Vega Hardware Specialization: From Cell to
Heterogeneous Microprocessors Everywhere 112--120
Ray Simar and
Reid Tatge How VLIWs Were Adopted as Digital Signal
Processors . . . . . . . . . . . . . . . 121--128
Wanda Gass Early History of Texas Instrument's
Digital Signal Processor . . . . . . . . 129--130
John R. Mashey Interactions, Impacts, and Coincidences
of the First Golden Age of Computer
Architecture . . . . . . . . . . . . . . 131--139
John L. Henning How Many VAXes Fit in the Palms of Your
Hands? . . . . . . . . . . . . . . . . . 140--143
Lizy Kurian John From the Memory Lane! . . . . . . . . . 144--147
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 147--147
Murray Goldman Last Chance: The Motorola Microprocessor
Story . . . . . . . . . . . . . . . . . 148--149
John Goodacre The Birth of Arm Multicore Processing 150--152
Pete Harrod Memories From IBM 370 to ARM . . . . . . 153--154
James O. Bondi Special Memories From My Favorite TI
Microprocessor Design Project . . . . . 155--155
D. M. G. Preethichandra Z80: The 1970s Microprocessor Still
Alive . . . . . . . . . . . . . . . . . 156--157
Robert Ryszard Chodorek NEC V20: Inspiring, Inconspicuous . . . 158--159
Ann Marie G. Maynard My Computer Journey . . . . . . . . . . 160--160
Cliff Young Atari's ANTIC: My Favorite
Microprocessor . . . . . . . . . . . . . 161--161
Anindya Banerjee and
Sankar Basu and
Erik Brunvand and
Pinaki Mazumder and
Rance Cleaveland and
Gurdip Singh and
Margaret Martonosi and
Fernanda Pembleton Navigating the Seismic Shift of
Post-Moore Computer Systems Design . . . 162--167
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 167--167
Bagus Hanindhito and
Karthik Swaminathan and
Vijaykrishnan Narayanan and
Lizy Kurian John Intel Wins in Four Decades, but AMD
Catches Up . . . . . . . . . . . . . . . 168--171
Joshua J. Yi Microarchitecture Patents Over Time and
Interesting Early Microarchitecture
Patents . . . . . . . . . . . . . . . . 172--178
Anonymous IEEE Computer Society Has You Covered! 178--178
Michael Mattioli The Apollo Guidance Computer . . . . . . 179--182
Anonymous IEEE Computer Society . . . . . . . . . 183--183
Shane Greenstein Virtuous Cycles . . . . . . . . . . . . 184--186
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Jobs Board . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Smart Agriculture and Smart Memories . . 4--6
Sudip Misra and
Neeraj Kumar Special Issue on Artificial
Intelligence, Edge, and Internet of
Things for Smart Agriculture . . . . . . 6--7
Anonymous IEEE Computer Society: Call for Papers 7--7
Debjani Ghosh and
Akash Anand and
Satya Sankalp Gautam and
Ankit Vidyarthi Soil Fertility Monitoring With Internet
of Underground Things: a Survey . . . . 8--16
Faisal Karim Shaikh and
Mohsin Ali Memon and
Naeem Ahmed Mahoto and
Sherali Zeadally and
Jamel Nebhen Artificial Intelligence Best Practices
in Smart Agriculture . . . . . . . . . . 17--24
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 24--24
Wei-Che Chien and
Mohammad Mehedi Hassan and
Ahmed Alsanad and
Giancarlo Fortino UAV Assisted Joint Wireless Power
Transfer and Data Collection Mechanism
for Sustainable Precision Agriculture in
5G . . . . . . . . . . . . . . . . . . . 25--32
Prabhat Kumar and
Govind P. Gupta and
Rakesh Tripathi PEFL: Deep Privacy-Encoding-Based
Federated Learning Framework for Smart
Agriculture . . . . . . . . . . . . . . 33--40
Muhammad Adil and
Muhammad Khurram Khan and
Mona Jamjoom and
Ahmed Farouk MHADBOR: AI-Enabled
Administrative-Distance-Based
Opportunistic Load Balancing Scheme for
an Agriculture Internet of Things
Network . . . . . . . . . . . . . . . . 41--50
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 50--50
Kaneez Fizza and
Prem Prakash Jayaraman and
Abhik Banerjee and
Dimitrios Georgakopoulos and
Rajiv Ranjan Evaluating Sensor Data Quality in
Internet of Things Smart Agriculture
Applications . . . . . . . . . . . . . . 51--60
Anonymous \booktitleIEEE Transactions on Big Data 60--60
Xu Liu and
Steven W. Chen and
Guilherme V. Nardari and
Chao Qu and
Fernando Cladera Ojeda and
Camillo J. Taylor and
Vijay Kumar Challenges and Opportunities for
Autonomous Micro-UAVs in Precision
Agriculture . . . . . . . . . . . . . . 61--68
Ranveer Chandra and
Manohar Swaminathan and
Tusher Chakraborty and
Jian Ding and
Zerina Kapetanovic and
Peeyush Kumar and
Deepak Vasisht Democratizing Data-Driven Agriculture
Using Affordable Hardware . . . . . . . 69--77
Andrew D. Balmos and
Fabio A. Castiblanco and
Aaron J. Neustedter and
James V. Krogmeier and
Dennis R. Buckmaster ISOBlue Avena: a Framework for
Agricultural Edge Computing and Data
Sovereignty . . . . . . . . . . . . . . 78--86
Reetuparna Das Special Issue on In-Memory Computing . . 87--88
Anonymous \booktitleIEEE Security & Privacy . . . . 88--88
Jian Meng and
Wonbo Shim and
Li Yang and
Injune Yeo and
Deliang Fan and
Shimeng Yu and
Jae-sun Seo Temperature-Resilient RRAM-Based
In-Memory Computing for DNN Inference 89--98
Juhyoung Lee and
Jihoon Kim and
Wooyoung Jo and
Sangyeob Kim and
Sangjin Kim and
Hoi-Jun Yoo ECIM: Exponent Computing in Memory for
an Energy-Efficient Heterogeneous
Floating-Point DNN Training Processor 99--107
Marzieh Lenjani and
Kevin Skadron Supporting Moderate Data Dependency,
Position Dependency, and Divergence in
PIM-Based Accelerators . . . . . . . . . 108--115
Liu Ke and
Xuan Zhang and
Jinin So and
Jong-Geon Lee and
Shin-Haeng Kang and
Sukhan Lee and
Songyi Han and
YeonGon Cho and
Jin Hyun Kim and
Yongsuk Kwon and
KyungSoo Kim and
Jin Jung and
Ilkwon Yun and
Sung Joo Park and
Hyunsun Park and
Joonho Song and
Jeonghyeon Cho and
Kyomin Sohn and
Nam Sung Kim and
Hsien-Hsin S. Lee Near-Memory Processing in Action:
Accelerating Personalized Recommendation
With AxDIMM . . . . . . . . . . . . . . 116--127
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part
II: Prosecution Time and Effective
Patent Term Length . . . . . . . . . . . 128--136
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 136--136
Anonymous IEEE Computer Society . . . . . . . . . 137--137
Shane Greenstein Google and Apple Signed a Deal . . . . . 138--140
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 140--140
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Jobs Board . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Special Issue on Cool Chips and Hot
Interconnects . . . . . . . . . . . . . 4--5
Anonymous IEEE Computer Society: Call for Papers 5--5
Makoto Ikeda and
Fumio Arakawa Special Issue on Cool Chips . . . . . . 6--7
Zhenshan Bao and
Guohang Fu and
Wenbo Zhang and
Kang Zhan and
Junnan Guo LSFQ: A Low-Bit Full Integer
Quantization for High-Performance
FPGA-Based CNN Acceleration . . . . . . 8--15
Donghyeon Han and
Dongseok Im and
Gwangtae Park and
Youngwoo Kim and
Seokchan Song and
Juhyoung Lee and
Hoi-Jun Yoo A Mobile DNN Training Processor With
Automatic Bit Precision Search and
Fine-Grained Sparsity Exploitation . . . 16--25
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 25--25
Mitsuhisa Sato and
Yuetsu Kodama and
Miwako Tsuji and
Tesuya Odajima Co-Design and System for the
Supercomputer Fugaku . . . . . . . . . . 26--34
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 34--34
Sayan Ghosh and
Ryan E. Grant and
Min Si Special Issue on Hot Interconnects . . . 35--36
Debendra Das Sharma A Low-Latency and Low-Power Approach for
Coherency and Memory Protocols on PCI
Express 6.0 PHY at 64.0 GT/s With PAM-4
Signaling . . . . . . . . . . . . . . . 37--43
Kartik Lakhotia and
Fabrizio Petrini and
Rajgopal Kannan and
Viktor Prasanna Accelerating Allreduce With In-Network
Reduction on Intel PIUMA . . . . . . . . 44--52
Arpan Jain and
Nawras Alnaasan and
Aamir Shafi and
Hari Subramoni and
Dhabaleswar K. Panda Optimizing Distributed DNN Training
Using CPUs and BlueField-2 DPUs . . . . 53--60
Cristóbal Camarero and
Carmen Martínez and
Ramón Beivide Polarized Routing for Large
Interconnection Networks . . . . . . . . 61--67
Anonymous \booktitleIEEE Transactions on Big Data 67--67
Yiltan Hassan Temuçin and
Amir Hossein Sojoodi and
Pedram Alizadeh and
Benjamin Kitor and
Ahmad Afsahi Accelerating Deep Learning Using
Interconnect-Aware UCX Communication for
MPI Collectives . . . . . . . . . . . . 68--76
Joshua J. Yi Review of Patents Issued to Computer
Architecture Companies in 2021 [Micro
Law] . . . . . . . . . . . . . . . . . . 77--84
Anonymous \booktitleIEEE Security & Privacy . . . . 84--84
Anonymous IEEE Computer Society . . . . . . . . . 85--85
Shane Greenstein Time for a Change in U.S. Antitrust for
Technology? . . . . . . . . . . . . . . 86--88
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Jobs Board . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Hot Chips 33 and More! . . . . . . . . . 4--5
Alisa Scherer and
Guri Sohi Special Issue on Hot Chips 33 . . . . . 6--6
Mark Evers and
Leslie Barnes and
Mike Clark The AMD Next-Generation ``Zen 3'' Core 7--12
Efraim Rotem and
Adi Yoaz and
Lihu Rappoport and
Stephen J. Robinson and
Julius Yuli Mandelblat and
Arik Gihon and
Eliezer Weissmann and
Rajshree Chabukswar and
Vadim Basin and
Russell Fenger and
Monica Gupta and
Ahmad Yasin Intel Alder Lake CPU Architectures . . . 13--19
Jin Hyun Kim and
Shin-Haeng Kang and
Sukhan Lee and
Hyeonsu Kim and
Yuhwan Ro and
Seungwon Lee and
David Wang and
Jihyun Choi and
Jinin So and
YeonGon Cho and
JoonHo Song and
Jeonghyeon Cho and
Kyomin Sohn and
Nam Sung Kim Aquabolt-XL HBM2-PIM, LPDDR5-PIM With
In-Memory Processing, and AXDIMM With
Acceleration Buffer . . . . . . . . . . 20--30
David R. Ditzel and
the Esperanto team Accelerating ML Recommendation With Over
1,000 RISC-V/Tensor Processors on
Esperanto's ET-SoC-1 Chip . . . . . . . 31--38
Anonymous IEEE Computer Society: Call for Papers 38--38
Anonymous \booktitleComputer: Call for Special
Issue Proposals . . . . . . . . . . . . 39--39
Amlan Ganguly and
Sergi Abadal and
Ishan Thakkar and
Natalie Enright Jerger and
Marc Riedel and
Masoud Babaie and
Rajeev Balasubramonian and
Abu Sebastian and
Sudeep Pasricha and
Baris Taskin Interconnects for DNA, Quantum,
In-Memory, and Optical Computing:
Insights From a Panel Discussion . . . . 40--49
German Maglione-Mathey and
Jesus Escudero-Sahuquillo and
Pedro Javier Garcia and
Francisco J. Quiles Reducing the Impact of Interjob
Interference in Dragonfly Networks Using
Virtual Partitions . . . . . . . . . . . 50--56
Fahrettin Koc and
Behzad Salami and
Oguz Ergin and
Osman Unsal and
Adrian Cristal Kestelman Can We Trust Undervolting in FPGA-Based
Deep Learning Designs at Harsh
Conditions? . . . . . . . . . . . . . . 57--65
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 65--65
Anonymous AI's 10 to Watch Award: Call for
Nominations . . . . . . . . . . . . . . 66--66
Joshua J. Yi Review of Patents Issued to Computer
Architecture Companies in 2021 --- Part
II . . . . . . . . . . . . . . . . . . . 67--77
Anonymous The Humphrey Award Nominations . . . . . 77--77
Michael Mattioli Meet the FaM1ly . . . . . . . . . . . . 78--84
Anonymous IEEE Computer Society . . . . . . . . . 85--85
Shane Greenstein Growth From Breadth and Depth . . . . . 86--88
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Jobs Board . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous \booktitleComputingEdge . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Lizy Kurian John Top Picks from 2021 Computer
Architecture Conferences! . . . . . . . 4--5
Sudhanva Gurumurthi and
Radu Teodorescu Special Issue on Top Picks From the 2021
Computer Architecture Conferences . . . 6--9
Pulkit A. Misra and
Ioannis Manousakis and
Esha Choukse and
Majid Jalili and
Íñigo Goiri and
Ashish Raniwala and
Brijesh Warrier and
Husam Alissa and
Bharath Ramakrishnan and
Phillip Tuma and
Christian Belady and
Marcus Fontoura and
Ricardo Bianchini Overclocking in Immersion-Cooled
Datacenters . . . . . . . . . . . . . . 10--17
Parthasarathy Ranganathan and
Daniel Stodolsky and
Jeff Calow and
Jeremy Dorfman and
Marisabel Guevara and
Clinton Wills Smullen IV and
Aki Kuusela Warehouse-Scale Video Acceleration . . . 18--26
Anonymous IEEE Computer Society Election . . . . . 26--26
Yu Gan and
Mingyu Liang and
Sundar Dev and
David Lo and
Christina Delimitrou Practical and Scalable ML-Driven Cloud
Performance Debugging With Sage . . . . 27--36
Anonymous IEEE Computer Society: Call for Papers 36--36
Udit Gupta and
Young Geun Kim and
Sylvia Lee and
Jordan Tse and
Hsien-Hsin S. Lee and
Gu-Yeon Wei and
David Brooks and
Carole-Jean Wu Chasing Carbon: The Elusive
Environmental Footprint of Computing . . 37--47
Axel Feldmann and
Nikola Samardzic and
Aleksandar Krastev and
Srinivas Devadas and
Ron Dreslinski and
Chris Peikert and
Daniel Sanchez An Architecture to Accelerate
Computation on Encrypted Data . . . . . 59--68
Michael B. Sullivan and
Nirmal R. Saxena and
Mike O Connor and
Donghyuk Lee and
Paul Racunas and
Saurabh Hukerikar and
Timothy Tsai and
Siva Kumar Sastry Hari and
Stephen W. Keckler Characterizing and Mitigating Soft
Errors in GPU DRAM . . . . . . . . . . . 69--77
Anonymous Carnegie Mellon University . . . . . . . 77--77
Vasileios Tsoutsouras and
Orestis Kaparounakis and
Chatura Samarakoon and
Bilgesu Bilgin and
James Meech and
Jan Heck and
Phillip Stanley-Marbell The Laplace Microarchitecture for
Tracking Data Uncertainty . . . . . . . 78--86
Muhammad Huzaifa and
Rishi Desai and
Samuel Grayson and
Xutao Jiang and
Ying Jing and
Jae Lee and
Fang Lu and
Yihan Pang and
Joseph Ravichandran and
Finn Sinclair and
Boyuan Tian and
Hengzhi Yuan and
Jeffrey Zhang and
Sarita V. Adve ILLIXR: an Open Testbed to Enable
Extended Reality Systems Research . . . 97--106
Apostolos Kokolis and
Antonis Psistakis and
Benjamin Reidys and
Jian Huang and
Josep Torrellas Distributed Data Persistency . . . . . . 107--115
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 115--115
Ajeya Naithani and
Sam Ainsworth and
Timothy M. Jones and
Lieven Eeckhout Vector Runahead for Indirect Memory
Accesses . . . . . . . . . . . . . . . . 116--123
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part
III: Claims . . . . . . . . . . . . . . 124--132
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 132--132
Anonymous IEEE Computer Society . . . . . . . . . 133--133
Shane Greenstein Inflation and Technology Markets . . . . 134--136
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Jobs Board . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Quantum Week . . . . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Automatic Compilation Will Be Key for
Success of the Accelerator Revolution! 4--5
Guido Araujo and
Lucas Wanner Special Issue on Compiling for
Accelerators . . . . . . . . . . . . . . 6--8
Anonymous IEEE Computer Society: Call for Papers 8--8
Hsin-I Cindy Liu and
Marius Brehler and
Mahesh Ravishankar and
Nicolas Vasilache and
Ben Vanik and
Stella Laurenzo TinyIREE: An ML Execution Environment
for Embedded Systems From Compilation to
Deployment . . . . . . . . . . . . . . . 9--16
Thien Nguyen and
Alexander McCaskey Retargetable Optimizing Compilers for
Quantum Accelerators via a Multilevel
Intermediate Representation . . . . . . 17--33
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 33--33
João P. L. de Carvalho and
José E. Moreira and
José Nelson Amaral Compiling for the IBM Matrix Engine for
Enterprise Workloads . . . . . . . . . . 34--40
Neil Adit and
Adrian Sampson Performance Left on the Table: An
Evaluation of Compiler Autovectorization
for RISC-V . . . . . . . . . . . . . . . 41--48
Nuno Neves and
Joao Mario Domingos and
Nuno Roma and
Pedro Tomás and
Gabriel Falcao Compiling for Vector Extensions With
Stream-Based Specialization . . . . . . 49--58
Jian Weng and
Sihao Liu and
Dylan Kupsh and
Tony Nowatzki Unifying Spatial Accelerator Compilation
With Idiomatic and Modular
Transformations . . . . . . . . . . . . 59--69
Kevin Angstadt and
Tommy Tracy and
Kevin Skadron and
Jean-Baptiste Jeannin and
Westley Weimer Synthesizing Legacy String Code for
FPGAs Using Bounded Automata Learning 70--77
Nicolas Bohm Agostini and
Serena Curzel and
Jeff Jun Zhang and
Ankur Limaye and
Cheng Tan and
Vinay Amatya and
Marco Minutoli and
Vito Giovanni Castellana and
Joseph Manzano and
David Brooks and
Gu-Yeon Wei and
Antonino Tumeo Bridging Python to Silicon: The SODA
Toolchain . . . . . . . . . . . . . . . 78--88
Joon Kyung Kim and
Byung Hoon Ahn and
Sean Kinzer and
Soroush Ghodrati and
Rohan Mahapatra and
Brahmendra Yatham and
Shu-Ting Wang and
Dohee Kim and
Parisa Sarikhani and
Babak Mahmoudi and
Divya Mahajan and
Jongse Park and
Hadi Esmaeilzadeh Yin-Yang: Programming Abstractions for
Cross-Domain Multi-Acceleration . . . . 89--98
Jean-Michel Gorius and
Simon Rokicki and
Steven Derrien SpecHLS: Speculative Accelerator Design
Using High-Level Synthesis . . . . . . . 99--107
Adel Ejjeh and
Aaron Councilman and
Akash Kothari and
Maria Kotsifakou and
Leon Medvinsky and
Abdul Rafae Noor and
Hashim Sharif and
Yifan Zhao and
Sarita Adve and
Sasa Misailovic and
Vikram Adve HPVM: Hardware-Agnostic Programming for
Heterogeneous Parallel Systems . . . . . 108--117
Anonymous IEEE Computer Society Has You Covered! 118--118
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part
IV: Claims . . . . . . . . . . . . . . . 119--127
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 127--127
Anonymous IEEE Computer Society . . . . . . . . . 128--128
Anonymous IEEE Computer Society D&I Fund . . . . . 129--129
Shane Greenstein Archetypes of Risky Decisions . . . . . 130--132
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Jobs Board . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous ComputingEdge . . . . . . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Artificial Intelligence at the Edge:
Designs and Architectures for Pervasive
Intelligence . . . . . . . . . . . . . . 4--5
Anonymous IEEE Computer Society: Call for Papers 5--5
Gabriel Falcao and
Joseph R. Cavallaro Special Issue on Artificial Intelligence
at the Edge . . . . . . . . . . . . . . 6--8
Sébastien Ollivier and
Xinyi Zhang and
Yue Tang and
Chayanika Choudhuri and
Jingtong Hu and
Alex K. Jones Pod-racing: bulk-bitwise to
floating-point compute in racetrack
memory for machine learning at the edge 9--16
Cecilia De la Parra and
Taha Soliman and
Andre Guntoro and
Akash Kumar and
Norbert Wehn Increasing Throughput of In-Memory DNN
Accelerators by Flexible Layerwise DNN
Approximation . . . . . . . . . . . . . 17--24
Geraldo F. Oliveira and
Juan Gómez-Luna and
Saugata Ghose and
Amirali Boroumand and
Onur Mutlu Accelerating Neural Network Inference
With Processing-in-DRAM: From the Edge
to the Cloud . . . . . . . . . . . . . . 25--38
Mahadev Satyanarayanan and
Ziqiang Feng and
Shilpa George and
Jan Harkes and
Roger Iyengar and
Haithem Turki and
Padmanabhan Pillai Accelerating Silent Witness Storage . . 39--47
Flavio Ponzina and
Simone Machetti and
Marco Rios and
Beno\^\it Walter Denkinger and
Alexandre Levisse and
Giovanni Ansaloni and
Miguel Peón-Quirós and
David Atienza A Hardware/Software Co-Design Vision for
Deep Learning at the Edge . . . . . . . 48--54
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 54--54
Jose Nunez-Yanez Fused Architecture for Dense and Sparse
Matrix Processing in TensorFlow Lite . . 55--66
Esteban Garzón and
Adam Teman and
Marco Lanuzza and
Leonid Yavits AIDA: Associative In-Memory Deep
Learning Accelerator . . . . . . . . . . 67--75
Chuteng Zhou and
Fernando García Redondo and
Julian Büchel and
Irem Boybat and
Xavier Timoneda Comas and
S. R. Nandakumar and
Shidhartha Das and
Abu Sebastian and
Manuel Le Gallo and
Paul N. Whatmough ML-HW Co-Design of Noise-Robust TinyML
Models and Always-On Analog
Compute-in-Memory Edge Accelerator . . . 76--87
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 87--87
Ali Safa and
Jonah Van Assche and
Mark Daniel Alea and
Francky Catthoor and
Georges G. E. Gielen Neuromorphic Near-Sensor Computing: From
Event-Based Sensing to Edge Learning . . 88--95
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 95--95
Hassan Nahas and
Sean Huver and
Billy Y. S. Yiu and
Chris M. Kallweit and
Adrian J. Y. Chee and
Alfred C. H. Yu Artificial-Intelligence-Enhanced
Ultrasound Flow Imaging at the Edge . . 96--106
Anonymous \booktitleIEEE Transactions on Big Data 106--106
Aidin Shiri and
Mozhgan Navardi and
Tejaswini Manjunath and
Nicholas R. Waytowich and
Tinoosh Mohsenin Efficient Language-Guided Reinforcement
Learning for Resource-Constrained
Autonomous Systems . . . . . . . . . . . 107--114
Anonymous \booktitleIEEE Security & Privacy . . . . 114--114
Anonymous IEEE Computer Society Has You Covered! 115--115
Lita Yang and
Robert M. Radway and
Yu-Hsin Chen and
Tony F. Wu and
Huichu Liu and
Elnaz Ansari and
Vikas Chandra and
Subhasish Mitra and
Edith Beigné Three-Dimensional Stacked Neural Network
Accelerator Architectures for AR/VR
Applications . . . . . . . . . . . . . . 116--124
Felix Jentzsch and
Yaman Umuroglu and
Alessandro Pappalardo and
Michaela Blott and
Marco Platzner RadioML Meets FINN: Enabling Future RF
Applications With FPGA Streaming
Architectures . . . . . . . . . . . . . 125--133
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 133--133
Anonymous IEEE Computer Society D&I Fund . . . . . 134--134
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part V:
References . . . . . . . . . . . . . . . 135--140
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 140--140
Anonymous IEEE Computer Society . . . . . . . . . 141--141
Shane Greenstein Distributed Discretion by the Slice . . 142--144
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . C3--C3
Anonymous IEEE Computer Society Jobs Board . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society Has You Covered! C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Environmentally Sustainable Computing 4--6
Anonymous \booktitleIEEE Security & Privacy . . . . 6--6
Carole-Jean Wu Special Issue on Environmentally
Sustainable Computing . . . . . . . . . 7--8
Lieven Eeckhout Kaya for Computer Architects: Toward
Sustainable Computer Systems . . . . . . 9--18
Sébastien Ollivier and
Sheng Li and
Yue Tang and
Stephen Cahoon and
Ryan Caginalp and
Chayanika Chaudhuri and
Peipei Zhou and
Xulong Tang and
Jingtong Hu and
Alex K. Jones Sustainable AI Processing at the Edge 19--28
Soumya Sudhakar and
Vivienne Sze and
Sertac Karaman Data Centers on Wheels: Emissions From
Computing Onboard Autonomous Vehicles 29--39
Ryusuke Egawa and
Yasutaka Wada Special Issue on Cool Chips . . . . . . 40--41
Moritz Scherer and
Alfio Di Mauro and
Tim Fischer and
Georg Rutishauser and
Luca Benini TCN-CUTIE: A 1,036-TOp/s/W, 2.72-$ \mu
$J/Inference, 12.2-mW All-Digital
Ternary Accelerator in 22-nm FDX
Technology . . . . . . . . . . . . . . . 42--48
Takuya Kojima and
Hayate Okuhara and
Masaaki Kondo and
Hideharu Amano A Scalable Body Bias Optimization Method
Toward Low-Power CGRAs . . . . . . . . . 49--57
Deanna Berger and
Christian Jacobi and
Craig R. Walters and
Robert J. Sonnelitter and
Mike Cadigan and
Matthias Klein Enterprise-Class Multilevel Cache
Design: Low Latency, Huge Capacity, and
High Reliability . . . . . . . . . . . . 58--66
Anonymous \booktitleComputing in Science Computing
in Science & Engineering Engineering . . 66--66
Yutaka Sugawara and
Dong Chen and
Ruud A. Haring and
Abdullah Kayi and
Eugene Ratzlaff and
Robert M. Senger and
Krishnan Sugavanam and
Ralph Bellofatto and
Ben J. Nathanson and
Craig Stunkel Data Movement Accelerator Engines on a
Prototype Power10 Processor . . . . . . 67--75
John Snyder and
Alvin R. Lebeck and
Danyang Zhuo RDMA Congestion Control: It Is Only for
the Compliant . . . . . . . . . . . . . 76--82
Joshua J. Yi Does Academic Research Drive Industrial
Innovation in Computer Architecture?
Analyzing Citations to Academic Papers
in Patents . . . . . . . . . . . . . . . 83--88
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 88--88
Anonymous IEEE Computer Society Information . . . 89--89
Shane Greenstein The Modern Digital Operating Model . . . 90--92
Anonymous IEEE Computer Society Jobs Board . . . . C3--C3
Anonymous \booktitleComputingEdge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society Has You Covered! C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Emerging System Interconnects Enabling
More Opportunities Than Ever! . . . . . 4--5
Anonymous \booktitleIEEE Security & Privacy . . . . 5--5
John Kim and
Nam Sung Kim Special Issue on Emerging System
Interconnects . . . . . . . . . . . . . 6--8
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 8--8
Debendra Das Sharma Novel Composable and Scaleout
Architectures Using Compute Express Link 9--19
Kyungsan Kim and
Hyunseok Kim and
Jinin So and
Wonjae Lee and
Junhyuk Im and
Sungjoo Park and
Jeonghyeon Cho and
Hoyoung Song SMT: Software-Defined Memory Tiering for
Heterogeneous Computing Systems With CXL
Memory Expander . . . . . . . . . . . . 20--29
Daniel S. Berger and
Daniel Ernst and
Huaicheng Li and
Pantea Zardoshti and
Monish Shah and
Samir Rajadnya and
Scott Lee and
Lisa Hsu and
Ishwar Agarwal and
Mark D. Hill and
Ricardo Bianchini Design Tradeoffs in CXL-Based Memory
Pools for Public Cloud Platforms . . . . 30--38
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 38--38
Minho Ha and
Junhee Ryu and
Jungmin Choi and
Kwangjin Ko and
Sunwoong Kim and
Sungwoo Hyun and
Donguk Moon and
Byungil Koh and
Hokyoon Lee and
Myoungseo Kim and
Hoshik Kim and
Kyoung Park Dynamic Capacity Service for Improving
CXL Pooled Memory Efficiency . . . . . . 39--47
Donghyun Gouk and
Miryeong Kwon and
Hanyeoreum Bae and
Sangwon Lee and
Myoungsoo Jung Memory Pooling With CXL . . . . . . . . 48--57
David Boles and
Daniel Waddington and
David A. Roberts CXL-Enabled Enhanced Memory Functions 58--65
Miryeong Kwon and
Junhyeok Jang and
Hanjin Choi and
Sangwon Lee and
Myoungsoo Jung Failure Tolerant Training With
Persistent Memory Disaggregation Over
CXL . . . . . . . . . . . . . . . . . . 66--75
Debendra Das Sharma System on a Package Innovations With
Universal Chiplet Interconnect Express
(UCIe) Interconnect . . . . . . . . . . 76--85
Shiqing Zhang and
Ziyue Zhang and
Mahmood Naderan-Tahan and
Hossein SeyyedAghaei and
Xin Wang and
He Li and
Senbiao Qin and
Didier Colle and
Guy Torfs and
Mario Pickavet and
Johan Bauwelinck and
Günther Roelkens and
Lieven Eeckhout Photonic Network-on-Wafer for
Multichiplet GPUs . . . . . . . . . . . 86--95
Anonymous Call for Papers: IEEE Computer Society 95--95
Anonymous Get Published in the New \booktitleIEEE
Open Journal of the Computer Society . . 96--96
Scott Levy Special Issue on Hot Interconnects 29 97--98
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 98--98
Debendra Das Sharma Compute Express Link (CXL): Enabling
Heterogeneous Data-Centric Computing
With Heterogeneous Memory Hierarchy . . 99--109
Yao Xin and
Wenjun Li and
Gaogang Xie and
Yang Xu and
Yi Wang A Parallel and Updatable Architecture
for FPGA-Based Packet Classification
With Large-Scale Rule Sets . . . . . . . 110--119
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 119--119
Alberto Cascajo and
Gabriel Gomez-Lopez and
Jesus Escudero-Sahuquillo and
Pedro Javier Garcia and
David E. Singh and
Francisco Alfaro-Cortés and
Francisco J. Quiles and
Jesus Carretero Monitoring InfiniBand Networks to React
Efficiently to Congestion . . . . . . . 120--130
Kaushik Kandadi Suresh and
Kawthar Shafie Khorassani and
Chen Chun Chen and
Bharath Ramesh and
Mustafa Abduljabbar and
Aamir Shafi and
Hari Subramoni and
Dhabaleswar K. Panda Network-Assisted Noncontiguous Transfers
for GPU-Aware MPI Libraries . . . . . . 131--139
Anonymous 2023 IEEE Conference on Artificial
Intelligence . . . . . . . . . . . . . . 140--140
Anonymous IEEE Computer Society Information . . . 141--141
Shane Greenstein Butterfly Effects and Legacies . . . . . 142--144
Anonymous IEEE Computer Society Jobs Board . . . . C3--C3
Anonymous \booktitleComputingEdge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous 2023 IEEE Conference on Artificial
Intelligence . . . . . . . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Hot Chips 34 and More! . . . . . . . . . 4--6
Anonymous Call for Papers for IEEE Computer
Society . . . . . . . . . . . . . . . . 6--6
Ron Diamant and
Krste Asanovic Special Issue on Hot Chips 34 . . . . . 7--8
Anonymous IEEE Computer Society Has You Covered! 8--8
Jack Choquette NVIDIA Hopper H100 GPU: Scaling
Performance . . . . . . . . . . . . . . 9--17
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 17--17
Sean Lie Cerebras Architecture Deep Dive: First
Look Inside the Hardware/Software
Co-Design for Deep Learning . . . . . . 18--30
Anonymous Watts S. Humphrey Software Quality Award 30--30
Emil Talpes and
Debjit Das Sarma and
Doug Williams and
Sahil Arora and
Thomas Kunjan and
Benjamin Floering and
Ankit Jalote and
Christopher Hsiong and
Chandrasekhar Poorna and
Vaidehi Samant and
John Sicilia and
Anantha Kumar Nivarti and
Raghuvir Ramachandran and
Tim Fischer and
Ben Herzberg and
Bill McGee and
Ganesh Venkataramanan and
Pete Banon The Microarchitecture of DOJO, Tesla's
Exa-Scale Computer . . . . . . . . . . . 31--39
Jaideep Dastidar and
David Riddoch and
Jason Moore and
Steven Pope and
Jim Wesselkamper The AMD 400-G Adaptive SmartNIC System
on Chip: a Technology Preview . . . . . 40--49
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 49--49
Richard Grisenthwaite and
Graeme Barnes and
Robert N. M. Watson and
Simon W. Moore and
Peter Sewell and
Jonathan Woodruff The Arm Morello Evaluation Platform
Validating CHERI-Based Security in a
High-Performance System . . . . . . . . 50--57
Martin Snelgrove and
Robert Beachler speedAI240: a 2-Petaflop, 30-Teraflops/W
At-Memory Inference Acceleration Device
With 1456 RISC-V Cores . . . . . . . . . 58--63
Karthik Sriram and
Ioannis Karageorgos and
Xiayuan Wen and
Ján Veselý and
Nick Lindsay and
Michael Wu and
Lenny Khazan and
Raghavendra Pradyumna Pothukuchi and
Rajit Manohar and
Abhishek Bhattacharjee HALO: a Hardware Software Co-Designed
Processor for Brain Computer Interfaces 64--72
Anonymous \booktitleIEEE Open Journal of the
Computer Society . . . . . . . . . . . . 73--73
Dongseok Im and
Gwangtae Park and
Zhiyong Li and
Junha Ryu and
Sanghoon Kang and
Donghyeon Han and
Jinsu Lee and
Wonhoon Park and
Hankyul Kwon and
Hoi-Jun Yoo A Mobile 3-D Object Recognition
Processor With Deep-Learning-Based
Monocular Depth Estimation . . . . . . . 74--82
Anonymous IEEE Computer Society D&I Fund . . . . . 83--83
Anonymous Call for 2023 Major Awards Nominations 84--84
Anonymous IEEE Computer Society . . . . . . . . . 85--85
Shane Greenstein Bank Runs Without the Wisdom of the
Crowds . . . . . . . . . . . . . . . . . 86--88
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 88--88
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous IEEE Quantum Week . . . . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Quantum Week . . . . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Top Picks From Computer Architecture
Conferences! . . . . . . . . . . . . . . 4--5
Anonymous Call for Papers for IEEE Computer
Society . . . . . . . . . . . . . . . . 5--5
Christopher Batten and
Jae W. Lee Special Issue on Top Picks From the 2022
Computer Architecture Conferences . . . 6--10
Joseph Ravichandran and
Weon Taek Na and
Jay Lang and
Mengjia Yan PACMAN: Attacking ARM Pointer
Authentication With Speculative
Execution . . . . . . . . . . . . . . . 11--18
Anonymous IEEE Computer Society Has You Covered! 18--18
Yingchen Wang and
Riccardo Paccagnella and
Elizabeth Tang He and
Hovav Shacham and
Christopher W. Fletcher and
David Kohlbrenner Hertzbleed: Turning Power Side-Channel
Attacks Into Remote Timing Attacks on
x86 . . . . . . . . . . . . . . . . . . 19--27
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 27--27
Jack Cook and
Jules Drean and
Jonathan Behrens and
Mengjia Yan There's Always a Bigger Fish: a
Clarifying Analysis of a
Machine-Learning-Assisted Side-Channel
Attack . . . . . . . . . . . . . . . . . 28--36
Anonymous Watts S. Humphrey Software Quality Award 36--36
Oleksii Oleksenko and
Christof Fetzer and
Boris Köpf and
Mark Silberstein Revizor: Testing Black-Box CPUs Against
Speculation Contracts . . . . . . . . . 37--44
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 44--44
Ishan Shah and
Akanksha Jain and
Calvin Lin Effective Mimicry of Bélády's MIN Policy 45--52
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 52--52
Evgeny Manzhosov and
Adam Hastings and
Meghna Pancholi and
Ryan Piersma and
Mohamed Tarek Ibn Ziad and
Simha Sethumadhavan Revisiting Residue Codes for Modern
Memories . . . . . . . . . . . . . . . . 53--61
Nicolai Oswald and
Vijay Nagarajan and
Daniel J. Sorin and
Vasilis Gavrielatos and
Theo X. Olausson and
Reece Carr HeteroGen: Automatic Synthesis of
Heterogeneous Cache Coherence Protocols 62--70
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 70--70
Yuxuan Zhang and
Tanvir Ahmed Khan and
Gilles Pokam and
Baris Kasikci and
Heiner Litz and
Joseph Devietti Online Code Layout Optimizations via
OCOLOS . . . . . . . . . . . . . . . . . 71--79
Anonymous \booktitleIEEE Security & Privacy . . . . 79--79
Tejun Heo and
Dan Schatzberg and
Andrew Newell and
Song Liu and
Saravanan Dhakshinamurthy and
Iyswarya Narayanan and
Josef Bacik and
Chris Mason and
Chunqiang Tang and
Dimitrios Skarlatos IOCost: Block Input Output Control for
Containers in Datacenters . . . . . . . 80--87
Anonymous Call for Articles: \booktitleIEEE
Pervasive Computing . . . . . . . . . . 87--87
Haoran You and
Yang Zhao and
Cheng Wan and
Zhongzhi Yu and
Yonggan Fu and
Jiayi Yuan and
Shang Wu and
Shunyao Zhang and
Yongan Zhang and
Chaojian Li and
Vivek Boominathan and
Ashok Veeraraghavan and
Ziyun Li and
Yingyan Celine Lin EyeCoD: Eye Tracking System Acceleration
via FlatCam-Based Algorithm and Hardware
Co-Design . . . . . . . . . . . . . . . 88--97
Anonymous Call for Articles: \booktitleIT
Professional . . . . . . . . . . . . . . 97--97
Yinan Xu and
Zihao Yu and
Dan Tang and
Ye Cai and
Dandan Huan and
Wei He and
Ninghui Sun and
Yungang Bao Toward Developing High-Performance
RISC-V Processors Using Agile
Methodology . . . . . . . . . . . . . . 98--106
Udit Gupta and
Mariam Elgamal and
Gage Hills and
Gu-Yeon Wei and
Hsien-Hsin S. Lee and
David Brooks and
Carole-Jean Wu Architectural CO2 Footprint Tool:
Designing Sustainable Computer Systems
With an Architectural Carbon Modeling
Tool . . . . . . . . . . . . . . . . . . 107--117
Anonymous IEEE Computer Society D&I Fund . . . . . 118--118
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies --- Part
VI: Relationship Between Prosecution
Time and Claims . . . . . . . . . . . . 119--123
Anonymous IEEE Computer Society . . . . . . . . . 124--124
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous IEEE Quantum Week . . . . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society D&I Fund . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John Hardware Security and Privacy: Threats
and Opportunities . . . . . . . . . . . 4--5
Guru Venkataramani Special Issue on Security and
Privacy-Preserving Execution
Environments . . . . . . . . . . . . . . 6--7
Anonymous IEEE Computer Society --- Call for
Papers . . . . . . . . . . . . . . . . . 7--7
Md Hafizul Islam Chowdhuryy and
Rickard Ewetz and
Amro Awad and
Fan Yao Understanding and Characterizing Side
Channels Exploiting Phase-Change
Memories . . . . . . . . . . . . . . . . 8--15
Naveed Ul Mustafa and
Yan Solihin Persistent Memory Security Threats to
Interprocess Isolation . . . . . . . . . 16--23
Kyle Thomas and
Muhammad Santriaji and
David Mohaisen and
Yan Solihin Exploration of Bitflip's Effect on Deep
Neural Network Accuracy in Plaintext and
Ciphertext . . . . . . . . . . . . . . . 24--34
Najmeh Nazari and
Hosein Mohammadi Makrani and
Chongzhou Fang and
Behnam Omidi and
Setareh Rafatirad and
Hossein Sayadi and
Khaled N. Khasawneh and
Houman Homayoun Adversarial Attacks Against Machine
Learning-Based Resource Provisioning
Systems . . . . . . . . . . . . . . . . 35--44
Anonymous IEEE Computer Society Has You Covered! 44--44
Sarabjeet Singh and
Xiong Fan and
Ananth Krishna Prasad and
Lin Jia and
Anirban Nag and
Rajeev Balasubramonian and
Mahdi Nazm Bojnordi and
Elaine Shi XCRYPT: Accelerating Lattice-Based
Cryptography With Memristor Crossbar
Arrays . . . . . . . . . . . . . . . . . 45--54
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 54--54
Neal Livesay and
Gilbert Jonatan and
Evelio Mora and
Kaustubh Shivdikar and
Rashmi Agrawal and
Ajay Joshi and
José L. Abellán and
John Kim and
David Kaeli Accelerating Finite Field Arithmetic for
Homomorphic Encryption on GPUs . . . . . 55--63
Animesh Basak Chowdhury and
Anushree Mahapatra and
Yang Liu and
Prashanth Krishnamurthy and
Farshad Khorrami and
Ramesh Karri A Golden-Free Approach to Detect Trojans
in COTS Multi-PCB Systems . . . . . . . 64--76
Anonymous IEEE Quantum Week . . . . . . . . . . . 76--76
Anonymous IEEE DataPort . . . . . . . . . . . . . 77--77
Sriram Aananthakrishnan and
Shamsul Abedin and
Vincent Cavé and
Fabio Checconi and
Kristof Du Bois and
Stijn Eyerman and
Joshua B. Fryman and
Wim Heirman and
Jason Howard and
Ibrahim Hur and
Samkit Jain and
Marek M. Landowski and
Kevin Ma and
Jarrod A. Nelson and
Robert Pawlowski and
Fabrizio Petrini and
Sebastian Szkoda and
Sanjaya Tayal and
Jesmin Jahan Tithi and
Yves Vandriessche The Intel Programmable and Integrated
Unified Memory Architecture Graph
Analytics Processor . . . . . . . . . . 78--87
Guiming Wu and
Qianwen He and
Jiali Jiang and
Zhenxiang Zhang and
Yunfeng Shi and
Xin Long and
Linquan Jiang and
Shuangchen Li and
Yuan Xie and
Changzheng Wei and
Yuan Zhao and
Ying Yan and
Hui Zhang and
Yinchao Zou E-Booster: a Field-Programmable Gate
Array-Based Accelerator for Secure Tree
Boosting Using Additively Homomorphic
Encryption . . . . . . . . . . . . . . . 88--96
Anonymous IEEE Computer Society . . . . . . . . . 97--97
Shane Greenstein Interview With Ronnie Chatterji,
Coordinator for the Creating Helpful
Incentives to Produce Semiconductors and
Science Act . . . . . . . . . . . . . . 98--100
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 100--100
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society D&I Fund . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Lizy Kurian John TinyML but by No Means a Tiny Feat! . . 4--6
Vijay Janapa Reddi and
Boris Murmann Special Issue on TinyML . . . . . . . . 7--10
Marius Brehler and
Lucas Camphausen and
Benjamin Heidebroek and
Dennis Krön and
Henri Gründer and
Simon Camphausen Making Machine Learning More Energy
Efficient by Bringing It Closer to the
Sensor . . . . . . . . . . . . . . . . . 11--18
Atsutake Kosuge and
Yao-Chung Hsu and
Rei Sumikawa and
Mototsugu Hamada and
Tadahiro Kuroda and
Tomoe Ishikawa A 10.7-$ \mu $J/Frame 88% Accuracy
CIFAR-10 Single-Chip Neuromorphic
Field-Programmable Gate Array Processor
Featuring Various Nonlinear Functions of
Dendrites in the Human Cerebrum . . . . 19--27
Anonymous IEEE Computer Society Has You Covered! 27--27
Anonymous IEEE Computer Society Volunteer Service
Awards . . . . . . . . . . . . . . . . . 28--28
Mozhgan Navardi and
Edward Humes and
Tejaswini Manjunath and
Tinoosh Mohsenin MetaE2RL: Toward Meta-Reasoning for
Energy-Efficient Multigoal Reinforcement
Learning With Squeezed-Edge You Only
Look Once . . . . . . . . . . . . . . . 29--39
Anonymous Over the Rainbow: 21st Century Security &
Privacy Podcast . . . . . . . . . . . . 39--39
Vivek Parmar and
Syed Shakib Sarwar and
Ziyun Li and
Hsien-Hsin S. Lee and
Barbara De Salvo and
Manan Suri Exploring Memory-Oriented Design
Optimization of Edge AI Hardware for
Extended Reality Applications . . . . . 40--49
Manuele Rusci and
Tinne Tuytelaars On-Device Customization of Tiny Deep
Learning Models for Keyword Spotting
With Few Examples . . . . . . . . . . . 50--57
Eduardo S. Pereira and
Leonardo S. Marcondes and
Josemar M. Silva On-Device Tiny Machine Learning for
Anomaly Detection Based on the Extreme
Values Theory . . . . . . . . . . . . . 58--65
Kazuki Sunaga and
Masaaki Kondo and
Hiroki Matsutani Addressing the Gap Between Training Data
and Deployed Environment by On-Device
Learning . . . . . . . . . . . . . . . . 66--73
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 73--73
Arnab Neelim Mazumder and
Tinoosh Mohsenin Reg-TuneV2: a Hardware-Aware and
Multiobjective Regression-Based
Fine-Tuning Approach for Deep Neural
Networks on Embedded Platforms . . . . . 74--83
Shunyao Zhang and
Yonggan Fu and
Shang Wu and
Jyotikrishna Dass and
Haoran You and
Yingyan Lin NetDistiller: Empowering Tiny Deep
Learning via In Situ Distillation . . . 84--92
Payman Behnam and
Jianming Tong and
Alind Khare and
Yangyu Chen and
Yue Pan and
Pranav Gadikar and
Abhimanyu Bambhaniya and
Tushar Krishna and
Alexey Tumanov Hardware Software Co-Design for
Real-Time Latency Accuracy Navigation in
Tiny Machine Learning Applications . . . 93--101
Anonymous Publications Seek 2025 Editors in Chief 102--102
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part
VII: Relationship Between Prosecution
Time and Claims . . . . . . . . . . . . 103--108
Matthew D. Sinclair and
Parthasarathy Ranganathan and
Gaurang Upasani and
Adrian Sampson and
David Patterson and
Rutwik Jain and
Nidhi Parthasarathy and
Shaan Shah Fifty Years of the International
Symposium on Computer Architecture: a
Data-Driven Retrospective . . . . . . . 109--124
Anonymous IEEE Computer Society Information . . . 125--125
Shane Greenstein The AI Gold Rush . . . . . . . . . . . . 126--128
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society D&I Fund . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Hsien-Hsin S. Lee Computing With COOL Chips . . . . . . . 4--5
Anonymous IEEE Computer Society Has You Covered! 5--5
Ryusuke Egawa and
Yasutaka Wada Special Issue on COOL Chips . . . . . . 6--7
Reon Oshio and
Takuya Sugahara and
Atsushi Sawada and
Mutsumi Kimura and
Renyuan Zhang and
Yasuhiko Nakashima A Compressed Spiking Neural Network Onto
a Memcapacitive In-Memory Computing
Array . . . . . . . . . . . . . . . . . 8--16
Donghyeon Han and
Junha Ryu and
Sangyeob Kim and
Sangjin Kim and
Jongjun Park and
Hoi-Jun Yoo A Low-Power
Artificial-Intelligence-Based 3-D
Rendering Processor With Hybrid Deep
Neural Network Computing . . . . . . . . 17--27
Sangyeob Kim and
Soyeon Kim and
Seongyon Hong and
Sangjin Kim and
Jiwon Choi and
Donghyeon Han and
Hoi-Jun Yoo COOL-NPU: Complementary Online Learning
Neural Processing Unit . . . . . . . . . 28--37
Anonymous \booktitleIEEE Security&Privacy Magazine 37--37
Tatsuya Kubo and
Shinya Takamaeda-Yamazaki Cachet: Low-Overhead Integrity
Verification on Metadata Cache in Secure
Nonvolatile Memory Systems . . . . . . . 38--48
Jianqing Liu and
Na Gong Privacy by Memory Design: Visions and
Open Problems . . . . . . . . . . . . . 49--58
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 58--58
Cyrius Nugier and
Vincent Migliore Acceleration of a Classic McEliece
Postquantum Cryptosystem With Cache
Processing . . . . . . . . . . . . . . . 59--68
Anonymous IEEE Computer Society Information . . . 69--69
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies Part
VIII: Patent Families . . . . . . . . . 70--74
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 74--74
Anonymous Publications Seek 2025 Editors in Chief 75--75
Shane Greenstein After the Gold Rush . . . . . . . . . . 76--78
Anonymous \booktitleIT Professional . . . . . . . 78--78
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous IEEE Computer Society D&I Fund . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Hsien-Hsin S. Lee Beyond Wires: The Future of
Interconnects . . . . . . . . . . . . . 4--5
Scott Levy and
Whit Schonbein Special Issue on Hot Interconnects 30 6--7
Anonymous IEEE Computer Society --- Call for
Papers . . . . . . . . . . . . . . . . . 7--7
Yuke Li and
Arjun Kashyap and
Yanfei Guo and
Xiaoyi Lu Compression Analysis for BlueField-2/-3
Data Processing Units: Lossy and
Lossless Perspectives . . . . . . . . . 8--19
Anonymous Get Published in the New \booktitleIEEE
Transactions on Privacy . . . . . . . . 19--19
Rafael Oliveira and
Ada Gavrilovska Comprex: In-Network Compression for
Accelerating IoT Analytics at Scale . . 20--30
Liuyao Dai and
Hao Qi and
Weicong Chen and
Xiaoyi Lu High-Speed Data Communication With
Advanced Networks in Large Language
Model Training . . . . . . . . . . . . . 31--40
Dennis Abts and
John Kim Enabling Artificial Intelligence
Supercomputers With Domain-Specific
Networks . . . . . . . . . . . . . . . . 41--49
Debendra Das Sharma and
Swadesh Choudhary Pipelined and Partitionable Forward
Error Correction and Cyclic Redundancy
Check Circuitry Implementation for PCI
Express 6.0 and Compute Express Link 3.0 50--59
Anonymous \booktitleIEEE Security & Privacy
Magazine . . . . . . . . . . . . . . . . 59--59
Anonymous IEEE Computer Society Information . . . 60--60
H. Ekin Sumbul and
Jae-sun Seo and
Daniel H. Morris and
Edith Beigne A Fully Digital and Row-Pipelined
Compute-in-Memory Neural Network
Accelerator With System-on-Chip-Level
Benchmarking for Augmented/Virtual
Reality Applications . . . . . . . . . . 61--70
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 70--70
Anonymous IEEE Computer Society Volunteer Service
Awards . . . . . . . . . . . . . . . . . 71--71
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part
IX: Patent Families . . . . . . . . . . 72--77
Anonymous \booktitle\booktitleComputing in Science
& Engineering . . . . . . . . . . . . . . 77--77
Shane Greenstein Party Like It's 1999? . . . . . . . . . 78--80
Anonymous \booktitleIT Professional . . . . . . . 80--80
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
Anonymous Front Cover . . . . . . . . . . . . . . C1--C1
Anonymous Get Published in the New \booktitleIEEE
Transactions on Privacy . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Hsien-Hsin S. Lee An Incoming World of Decoupling
Siliconomy . . . . . . . . . . . . . . . 4--5
Heiner Litz and
Natalia Vassilieva Special Issue on Hot Chips 2023 . . . . 6--7
Ravi Bhargava and
Kai Troester AMD Next-Generation ``Zen 4'' Core and
4th Gen AMD EPYC Server CPUs . . . . . . 8--17
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 17--17
Mahesh Subramony and
David Kramer and
Indrani Paul AMD Ryzen 7040 Series . . . . . . . . . 18--24
Jason Howard and
Joshua B. Fryman and
Shamsul Abedin The First Direct Mesh-to-Mesh Photonic
Fabric . . . . . . . . . . . . . . . . . 25--32
Anonymous \booktitleIT Professional: Call for
Articles . . . . . . . . . . . . . . . . 32--32
Amir Gholami and
Zhewei Yao and
Sehoon Kim and
Coleman Hooper and
Michael W. Mahoney and
Kurt Keutzer AI and Memory Wall . . . . . . . . . . . 33--39
Anonymous \booktitleIEEE Pervasive Computing: Call
for Articles . . . . . . . . . . . . . . 39--39
Byeongho Kim and
Sanghoon Cha and
Sangsoo Park and
Jieun Lee and
Sukhan Lee and
Shin-haeng Kang and
Jinin So and
Kyungsoo Kim and
Jin Jung and
Jong-Geon Lee and
Sunjung Lee and
Yoonah Paik and
Hyeonsu Kim and
Jin-Seong Kim and
Won-Jo Lee and
Yuhwan Ro and
YeonGon Cho and
Jin Hyun Kim and
JoonHo Song and
Jaehoon Yu and
Seungwon Lee and
Jeonghyeon Cho and
Kyomin Sohn The Breakthrough Memory Solutions for
Improved Performance on LLM Inference 40--48
Sean Lie Inside the Cerebras Wafer-Scale Cluster 49--57
Anonymous \booktitleIEEE Security & Privacy
Magazine . . . . . . . . . . . . . . . . 57--57
Ian Winfield and
Tim Ouradnik and
Joseph Madril and
Michael Matthews and
Guillermo Romero High-Performance Cooling for Power
Electronics via Electrochemical Additive
Manufacturing . . . . . . . . . . . . . 58--66
Michael Gibbs and
Kieran Woodward and
Eiman Kanjo Combining Multiple Tiny Machine Learning
Models for Multimodal Context-Aware
Stress Recognition on Constrained
Microcontrollers . . . . . . . . . . . . 67--75
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part X:
Patent Families . . . . . . . . . . . . 76--80
Anonymous IEEE Computer Society Information . . . 81--81
Reviewed by Shane Greenstein Book Review: \booktitleThe Worlds I See:
Curiosity, Exploration, and the
Discovery at the Dawn of AI, Fei-Fei Li
(New York, NY, USA: Flatiron Books,
2023, 336 pp.) . . . . . . . . . . . . . 82--84
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 84--84
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4
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Anonymous Get Published in the New \booktitleIEEE
Transactions on Privacy . . . . . . . . C2--C2
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Hsien-Hsin S. Lee Top Picks Ignite Innovation . . . . . . 4--5
Anonymous \booktitleComputing in Science &
Engineering . . . . . . . . . . . . . . 5--5
Yan Solihin Special Issue on Top Picks From the 2023
Computer Architecture Conferences . . . 6--10
Anonymous \booktitleIT Professional . . . . . . . 19--19
Kuan-Chieh Hsu and
Hung-Wei Tseng Simultaneous and Heterogeneous
Multithreading: Exploiting Simultaneous
and Heterogeneous Parallelism in
Accelerator-Rich Architectures . . . . . 11--19
Ajeya Naithani and
Jaime Roelandts and
Sam Ainsworth and
Timothy M. Jones and
Lieven Eeckhout Decoupled Vector Runahead for
Prefetching Nested Memory-Access Chains 20--26
Mingyu Liang and
Yu Gan and
Yueying Li and
Carlos Torres and
Abhishek Dhanotia and
Mahesh Ketkar and
Christina Delimitrou End-to-End Cloud Application Cloning
With Ditto . . . . . . . . . . . . . . . 34--43
Kaiyang Zhao and
Kaiwen Xue and
Ziqi Wang and
Dan Schatzberg and
Leon Yang and
Antonis Manousis and
Johannes Weiner and
Rik Van Riel and
Bikash Sharma and
Chunqiang Tang and
Dimitrios Skarlatos Contiguitas: The Pursuit of Physical
Memory Contiguity in Data Centers . . . 44--51
Anonymous Call for Articles: \booktitleIEEE
Pervasive Computing . . . . . . . . . . 51--51
Jaehyun Han and
Krishnan Gosakan and
William Kuszmaul and
Ibrahim N. Mubarek and
Nirjhar Mukherjee and
Karthik Sriram and
Guido Tagliavini and
Evan West and
Michael A. Bender and
Abhishek Bhattacharjee and
Alex Conway and
Martín Farach-Colton and
Jayneel Gandhi and
Rob Johnson and
Sudarsun Kannan and
Donald E. Porter Mosaic Pages: Big TLB Reach With Small
Pages . . . . . . . . . . . . . . . . . 52--59
Shravan Narayan and
Tal Garfinkel and
Mohammadkazem Taram and
Joey Rudek and
Daniel Moghimi and
Evan Johnson and
Chris Fallin and
Anjo Vahldiek-Oberwagner and
Michael LeMay and
Ravi Sahita and
Dean Tullsen and
Deian Stefan Hardware-Assisted Fault Isolation: Going
Beyond the Limits of Software-Based
Sandboxing . . . . . . . . . . . . . . . 70--79
Anonymous \booktitleIEEE Security & Privacy
Magazine . . . . . . . . . . . . . . . . 79--79
Gerasimos Gerogiannis and
Josep Torrellas Practical Online Reinforcement Learning
for Microprocessors With Micro-Armed
Bandit . . . . . . . . . . . . . . . . . 80--87
Nathaniel Bleier and
Abigail Wezelis and
Lav Varshney and
Rakesh Kumar Programmable Olfactory Computing . . . . 88--96
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies. Part
XI: Patent Families . . . . . . . . . . 116--120
Anonymous IEEE Computer Society Information . . . 121--121
Shane Greenstein Navigating Applications Development in
Generative AI . . . . . . . . . . . . . 122--124
Anonymous IEEE Computer Society Career Center . . C3--C3
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Transactions on Privacy . . . . . . . . C2--C2
Anonymous Masthead . . . . . . . . . . . . . . . . 1--1
Anonymous Table of Contents . . . . . . . . . . . 2--3
Hsien-Hsin S. Lee The Path to Powering Intelligence . . . 4--5
John L. Hennessy and
Christos Kozyrakis and
Gabriel Falcão Special Issue on The Past, Present, and
Future of Warehouse-Scale Computing . . 6--7
John L. Hennessy Luiz André Barroso: Brilliant Engineer,
Humble Leader, and Mentor . . . . . . . 8--10
Anonymous \booktitle\booktitleComputing in Science
& Engineering . . . . . . . . . . . . . . 10--10
Parthasarathy Ranganathan and
Urs Hölzle Twenty Five Years of Warehouse-Scale
Computing . . . . . . . . . . . . . . . 11--22
Leah Shalev and
Hani Ayoub and
Nafea Bshara and
Yuval Fatael and
Ori Golan and
Omer Ilany and
Anna Levin and
Zorik Machulsky and
Kevin Milczewski and
Marc Olson and
Valentin Priescu and
Shyam Rajagopal and
Ali Saidi The Tail at Amazon Web Services Scale 23--29
Ricardo Bianchini and
Christian Belady and
Anand Sivasubramaniam Data Center Power and Energy Management:
Past, Present, and Future . . . . . . . 30--36
Anonymous \booktitleIT Professional . . . . . . . 36--36
Carole-Jean Wu and
Bilge Acun and
Ramya Raghavendra and
Kim Hazelwood Beyond Efficiency: Scaling AI
Sustainably . . . . . . . . . . . . . . 37--46
Anonymous Call for Articles: \booktitleIEEE
Pervasive Computing . . . . . . . . . . 46--46
Yiquan Chen and
Yuan Xie and
Yijing Wang and
Jiexiong Xu and
Zhen Jin and
Anyu Li and
Xiaoyan Fu and
Qiang Liu and
Wenzhi Chen Optimizing NVMe Storage for Large-Scale
Deployment: Key Technologies and
Strategies in Alibaba Cloud . . . . . . 47--56
Anonymous \booktitleIEEE Security & Privacy
Magazine . . . . . . . . . . . . . . . . 56--56
Christina Delimitrou and
Michael Marty Tales of the Tail: Past and Future . . . 57--64
Babak Falsafi and
Michael Ferdman and
Boris Grot Server Architecture From Enterprise to
Post-Moore . . . . . . . . . . . . . . . 65--73
Anonymous IEEE Computer Society Information . . . 74--74
Andrei Bersatti and
Euna Kim and
Hyesoon Kim Quantifying CO$_2$ Emission Reduction
Through Spatial Partitioning in Deep
Learning Recommendation System Workloads 75--82
Joshua J. Yi Analysis of Historical Patenting
Behavior and Patent Characteristics of
Computer Architecture Companies --- Part
XII: Patent Families . . . . . . . . . . 83--88
Anonymous IEEE Computer Society Has You Covered! 89--89
Shane Greenstein Commercial and Scientific Prototypes . . 90--92
Anonymous \booktitleIEEE Computer Graphics and
Applications . . . . . . . . . . . . . . 92--92
Anonymous IEEE Computer Society Career Center . . C3--C3
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Anonymous Publish With the IEEE Computer Society C2--C2
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Anonymous Table of Contents . . . . . . . . . . . 2--3
Hsien-Hsin S. Lee Strategic Pivot of Long-Standing x86
Rivals . . . . . . . . . . . . . . . . . 4--5
John B. Carter Special Issue on Contemporary Industry
Products 2024 . . . . . . . . . . . . . 6--7
Patrick Meaney and
Ashutosh Mishra and
Rajat Rao Synchronous, Low-Latency, Off-Module
Interface for the IBM z16 Telum
Processor . . . . . . . . . . . . . . . 8--16
Anonymous Call for Papers: IEEE Computer Society 16--16
Seungjae Moon and
Jung-Hoon Kim and
Junsoo Kim and
Seongmin Hong and
Junseo Cha and
Minsu Kim and
Sukbin Lim and
Gyubin Choi and
Dongjin Seo and
Jongho Kim and
Hunjong Lee and
Hyunjun Park and
Ryeowook Ko and
Soongyu Choi and
Jongse Park and
Jinwon Lee and
Joo-Young Kim A Latency Processing Unit: a
Latency-Optimized and Highly Scalable
Processor for Large Language Model
Inference . . . . . . . . . . . . . . . 17--33
Raghu Prabhakar and
Ram Sivaramakrishnan and
Darshan Gandhi and
Yun Du and
Mingran Wang and
Xiangyu Song and
Kejie Zhang and
Tianren Gao and
Angela Wang and
Xiaoyan Li and
Joshua Brot and
Calvin Leung and
Tuowen Zhao and
Mark Gottscho and
Zhengyu Chen and
Kaizhao Liang and
Swayambhoo Jain and
Urmish Thakker and
Kevin J. Brown and
Kunle Olukotun Composition of Experts on the SN40L
Reconfigurable Dataflow Unit . . . . . . 34--43
Krishnakumar Nair and
Avinash-Chandra Pandey and
Siddappa Karabannavar and
Meena Arunachalam and
John Kalamatianos and
Varun Agrawal and
Saurabh Gupta and
Ashish Sirasao and
Elliott Delaye and
Steve Reinhardt and
Rajesh Vivekanandham and
Ralph Wittig and
Vinod Kathail and
Padmini Gopalakrishnan and
Satyaprakash Pareek and
Rishabh Jain and
Mahmut Taylan Kandemir and
Jun-Liang Lin and
Gulsum Gudukbay Akbulut and
Chita R. Das Parallelization Strategies for DLRM
Embedding Bag Operator on AMD CPUs . . . 44--51
Nathan Beckmann and
Brandon Lucia and
Graham Gobieski and
Tony Nowatzki and
Thomas Jackson and
Guénolé Lallement and
Keyi Zhang and
Amolak Nagi and
Atharv Sathe and
Harsh Desai Monza: an Energy-Minimal,
General-Purpose Dataflow System-on-Chip
for the Internet of Things . . . . . . . 52--62
Sanchari Sen and
Shubham Jain and
Sarada Krithivasan and
Swagath Venkataramani and
Vijayalakshmi Srinivasan DNNDaSher: a Compiler Framework for
Dataflow Compatible End-to-End
Acceleration on IBM AIU . . . . . . . . 63--72
Alejandro Rico and
Satyaprakash Pareek and
Javier Cabezas and
David Clarke and
Baris Ozgul and
Francisco Barat and
Yao Fu and
Stephan Münz and
Dylan Stuart and
Patrick Schlangen and
Pedro Duarte and
Sneha Date and
Indrani Paul and
Jian Weng and
Sonal Santan and
Vinod Kathail and
Ashish Sirasao and
Juanjo Noguera AMD XDNA NPU in Ryzen AI Processors . . 73--82
Jade Alglave and
Richard Grisenthwaite and
Artem Khyzha and
Luc Maranget and
Nikos Nikoleris Puss in Boots: Formalizing Arm's Virtual
Memory System Architecture . . . . . . . 83--91
Joshua J. Yi A Review of Wisconsin Alumni Research
Foundation v. Apple --- Part I . . . . . 92--96
Anonymous \booktitleIEEE Annals of the History of
Computing . . . . . . . . . . . . . . . 96--96
Anonymous IEEE Computer Society Information . . . 97--97
Lizy Kurian John Mauricio Breternitz, Jr. . . . . . . . . 98--99
Shane Greenstein Unpriced and Crucial . . . . . . . . . . 100--102
Anonymous Call for Papers: \booktitleIEEE
Transactions on Computers . . . . . . . 102--102
Anonymous IEEE Computer Society Career Center . . C3--C3
Anonymous \booktitleComputing Edge . . . . . . . . C4--C4