# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Bos:2017:FAM
author: Joppe W. Bos and Simon Friedberger
title: Fast Arithmetic Modulo $ 2^x p^y pm 1 $
crossref: Burgess:2017:ISC
pages: 148--155
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.15
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Joppe W. Bos and Simon Friedberger
rawtitle: Fast Arithmetic Modulo $ 2^x p^y \pm 1 $
abstract:
We give a systematic overview of techniques to compute arithmetic modulo $ 2^x p^y pm 1 $ and propose improvements. This is useful for computations in the supersingular isogeny Diffie-Hellman (SIDH) key-exchange protocol which is one of the more recent contenders in the post-quantum public-key arena. One of the main computational bottlenecks in this cryptographic key-exchange protocol is computing modular arithmetic in a finite field defined by a prime of this special shape. Recent implementations already use this special prime shape to speed up the cryptographic implementations but it remains unclear if the choices made are optimal or if one can do better. Our overview shows that in the SIDH setting, where arithmetic over a quadratic extension field is required, the approaches based on Montgomery multiplication are to be preferred. Based on our results, we give selection criteria for such moduli and the outcome of our search reveals that there exist moduli which result in even faster implementations.

keywords:
Barrett reduction; computational bottlenecks; cryptographic key-exchange protocol; cryptographic protocols; Electronic mail; Elliptic curves; fast arithmetic modulo; finite field; modular arithmetic; Montgomery multiplication; Optimization; post-quantum cryptography; post-quantum public-key arena; Protocols; Public key cryptography; public key cryptography; quadratic extension field; quantum cryptography; selection criteria; Shape; SIDH; SIDH key-exchange protocol; supersingular isogeny Diffie--Hellman key-exchange protocol

rawabstract:
We give a systematic overview of techniques to compute arithmetic modulo $ 2^x p^y \pm 1 $ and propose improvements. This is useful for computations in the supersingular isogeny Diffie-Hellman (SIDH) key-exchange protocol which is one of the more recent contenders in the post-quantum public-key arena. One of the main computational bottlenecks in this cryptographic key-exchange protocol is computing modular arithmetic in a finite field defined by a prime of this special shape. Recent implementations already use this special prime shape to speed up the cryptographic implementations but it remains unclear if the choices made are optimal or if one can do better. Our overview shows that in the SIDH setting, where arithmetic over a quadratic extension field is required, the approaches based on Montgomery multiplication are to be preferred. Based on our results, we give selection criteria for such moduli and the outcome of our search reveals that there exist moduli which result in even faster implementations.

entry:
@InProceedings{Bos:2017:FAM,
  author =       "Joppe W. Bos and Simon Friedberger",
  title =        "Fast Arithmetic Modulo $ 2^x p^y \pm 1 $",
  crossref =     "Burgess:2017:ISC",
  pages =        "148--155",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.15",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We give a systematic overview of techniques to compute
                 arithmetic modulo $ 2^x p^y \pm 1 $ and propose
                 improvements. This is useful for computations in the
                 supersingular isogeny Diffie-Hellman (SIDH)
                 key-exchange protocol which is one of the more recent
                 contenders in the post-quantum public-key arena. One of
                 the main computational bottlenecks in this
                 cryptographic key-exchange protocol is computing
                 modular arithmetic in a finite field defined by a prime
                 of this special shape. Recent implementations already
                 use this special prime shape to speed up the
                 cryptographic implementations but it remains unclear if
                 the choices made are optimal or if one can do better.
                 Our overview shows that in the SIDH setting, where
                 arithmetic over a quadratic extension field is
                 required, the approaches based on Montgomery
                 multiplication are to be preferred. Based on our
                 results, we give selection criteria for such moduli and
                 the outcome of our search reveals that there exist
                 moduli which result in even faster implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "Barrett reduction; computational bottlenecks;
                 cryptographic key-exchange protocol; cryptographic
                 protocols; Electronic mail; Elliptic curves; fast
                 arithmetic modulo; finite field; modular arithmetic;
                 Montgomery multiplication; Optimization; post-quantum
                 cryptography; post-quantum public-key arena; Protocols;
                 Public key cryptography; public key cryptography;
                 quadratic extension field; quantum cryptography;
                 selection criteria; Shape; SIDH; SIDH key-exchange
                 protocol; supersingular isogeny Diffie--Hellman
                 key-exchange protocol",
}


bibtype: article
filename: fparith.bib
label: Brisebarre:2017:ESC
author: Nicolas Brisebarre and Guillaume Hanrot and Olivier Robert
title: Exponential Sums and Correctly-Rounded Functions
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2044--2057
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2690850
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7891945/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Nicolas Brisebarre and Guillaume Hanrot and Olivier Robert
rawtitle: Exponential Sums and Correctly-Rounded Functions
entry:
@Article{Brisebarre:2017:ESC,
  author =       "Nicolas Brisebarre and Guillaume Hanrot and Olivier
                 Robert",
  title =        "Exponential Sums and Correctly-Rounded Functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2044--2057",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2690850",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7891945/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: phdthesis
filename: fparith.bib
label: Brisebarre:2017:PTN
author: Nicolas Brisebarre
type: Habilitation a Diriger des Recherches
school: LIP --- Laboratoire de l'Informatique du Parallelisme
address: Lyon, France
pages: 125
year: 2017
bibdate: Fri Dec 08 10:49:49 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 10:49:49 ???
URL: https://theses.hal.science/tel-01658342v3
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre
title:
Un peu de theorie des nombres et de calcul formel au service de l'arithmetique des ordinateurs. (French) [A little number theory and computer algebra in the service of computer arithmetic]

rawtitle:
Un peu de th{\'e}orie des nombres et de calcul formel au service de l'arithm{\'e}tique des ordinateurs. ({French}) [{A} little number theory and computer algebra in the service of computer arithmetic]

entry:
@PhdThesis{Brisebarre:2017:PTN,
  author =       "Nicolas Brisebarre",
  title =        "Un peu de th{\'e}orie des nombres et de calcul formel
                 au service de l'arithm{\'e}tique des ordinateurs.
                 ({French}) [{A} little number theory and computer
                 algebra in the service of computer arithmetic]",
  type =         "Habilitation {\`a} Diriger des Recherches",
  school =       "LIP --- Laboratoire de l'Informatique du
                 Parall{\'e}lisme",
  address =      "Lyon, France",
  pages =        "125",
  year =         "2017",
  bibdate =      "Fri Dec 08 10:49:49 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://theses.hal.science/tel-01658342v3",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Brunie:2017:MFM
author: Nicolas Brunie
title: Modified Fused Multiply and Add for Exact Low Precision Product Accumulation
crossref: Burgess:2017:ISC
pages: 106--113
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.29
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Nicolas Brunie
rawtitle: Modified Fused Multiply and Add for Exact Low Precision Product Accumulation
abstract:
The implementation of the Fused Multiply and Add (FMA) operation has been extensively studied in the literature on standard and large precisions. We suggest re- visiting those studies for 16-bit precision. We introduce a variation of the Mixed precision FMA targeted for applications processing low precision inputs (such as machine learning). We also introduce several versions of a fixed point based floating- point FMA which performs an exact accumulation of binary16 numbers. We study the implementation and area footprint of those operators in comparison with standard FMAs.

keywords:
adders; Adders; arithmetic; Complexity theory; Computer architecture; exact low precision product accumulation; fixed point arithmetic; fixed point based floating- point FMA; floating-point; FMA; FPU; fused multiply and add operation; half precision; Hardware; Linear algebra; logic design; mixed precision FMA; multiplying circuits; Standards

rawabstract:
The implementation of the Fused Multiply and Add (FMA) operation has been extensively studied in the literature on standard and large precisions. We suggest re- visiting those studies for 16-bit precision. We introduce a variation of the Mixed precision FMA targeted for applications processing low precision inputs (such as machine learning). We also introduce several versions of a fixed point based floating- point FMA which performs an exact accumulation of binary16 numbers. We study the implementation and area footprint of those operators in comparison with standard FMAs.

entry:
@InProceedings{Brunie:2017:MFM,
  author =       "Nicolas Brunie",
  title =        "Modified Fused Multiply and Add for Exact Low
                 Precision Product Accumulation",
  crossref =     "Burgess:2017:ISC",
  pages =        "106--113",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.29",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The implementation of the Fused Multiply and Add (FMA)
                 operation has been extensively studied in the
                 literature on standard and large precisions. We suggest
                 re- visiting those studies for 16-bit precision. We
                 introduce a variation of the Mixed precision FMA
                 targeted for applications processing low precision
                 inputs (such as machine learning). We also introduce
                 several versions of a fixed point based floating- point
                 FMA which performs an exact accumulation of binary16
                 numbers. We study the implementation and area footprint
                 of those operators in comparison with standard FMAs.",
  acknowledgement = ack-nhfb,
  keywords =     "adders; Adders; arithmetic; Complexity theory;
                 Computer architecture; exact low precision product
                 accumulation; fixed point arithmetic; fixed point based
                 floating- point FMA; floating-point; FMA; FPU; fused
                 multiply and add operation; half precision; Hardware;
                 Linear algebra; logic design; mixed precision FMA;
                 multiplying circuits; Standards",
}


bibtype: misc
filename: fparith.bib
label: Carter:2017:PAO
title: Performing arithmetic operations using both large and small floating point values
pages: 106--113
day: 30
month: may
monthnumber: 5
year: 2017
bibdate: Thu Oct 17 11:38:25 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 11:38:25 ???
URL: https://patents.google.com/patent/US9665346B2
acknowledgement: ack-nhfb
howpublished: US Patent 9,665,346
rawtitle: Performing arithmetic operations using both large and small floating point values
author:
John B. Carter and Bruce G. Mealey and Karthick Rajamani and Eric E. Retter and Jeffrey A. Stuecheli

abstract:
Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

remark:
Patent filed 28 October 2014, granted to IBM 30 May 2017, expected expiration 22 December 2031 (in 17th year after filing).

rawabstract:
Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

rawauthor:
John B. Carter and Bruce G. Mealey and Karthick Rajamani and Eric E. Retter and Jeffrey A. Stuecheli

entry:
@Misc{Carter:2017:PAO,
  author =       "John B. Carter and Bruce G. Mealey and Karthick
                 Rajamani and Eric E. Retter and Jeffrey A. Stuecheli",
  title =        "Performing arithmetic operations using both large and
                 small floating point values",
  howpublished = "US Patent 9,665,346",
  day =          "30",
  month =        may,
  year =         "2017",
  bibdate =      "Thu Oct 17 11:38:25 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US9665346B2",
  abstract =     "Mechanisms are provided for performing a floating
                 point arithmetic operation in a data processing system.
                 A plurality of floating point operands of the floating
                 point arithmetic operation are received and bits in a
                 mantissa of at least one floating point operand of the
                 plurality of floating point operands are shifted. One
                 or more bits of the mantissa that are shifted outside a
                 range of bits of the mantissa of at least one floating
                 point operand are stored and a vector value is
                 generated based on the stored one or more bits of the
                 mantissa that are shifted outside of the range of bits
                 of the mantissa of the at least one floating point
                 operand. A resultant value is generated for the
                 floating point arithmetic operation based on the vector
                 value and the plurality of floating point operands.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 28 October 2014, granted to IBM 30 May
                 2017, expected expiration 22 December 2031 (in 17th
                 year after filing).",
}


bibtype: mastersthesis
filename: fparith.bib
label: Chapp:2017:SIN
author: Dylan Chapp
title: Study of the impact of non-determinism on numerical reproducibility and debugging at the exascale
type: Master of Science in Computer Science
school: University of Delaware
address: Newark, DE, USA
pages: 69
month: Spring
year: 2017
ISBN: 0-355-25168-X OR 035525168X
ISBN13: 978-0-355-25168-5 OR 9780355251685
bibdate: Mon Feb 10 06:07:39 MST 2020
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 06:07:39 MST
acknowledgement: ack-nhfb
advisor: Michela Taufer
rawauthor: Dylan Chapp
rawtitle: Study of the impact of non-determinism on numerical reproducibility and debugging at the exascale
URL:
http://udspace.udel.edu/handle/19716/24492; https://search.proquest.com/pqdtglobal/docview/1957944576

abstract:
Non-determinism in high performance scientific applications has severe detrimental impacts for both numerical reproducibility and accuracy, and debugging. As scientific simulations are migrated to extreme-scale platforms, the increase in platform concurrency and the attendant increase in non-determinism is likely to exacerbate both of these problems. In this thesis, we address the dual challenges of non-determinism's impact on numerical reproducibility and on debugging. To address the numerical challenge, our work investigates the power of mathematical methods to mitigate error propagation at the exascale. We focus on floating-point error accumulation over global summations where enforcing any reduction order is expensive or impossible. We model parallel summations with reduction trees and identify those parameters that can be used to estimate the reduction's sensitivity to variability in the reduction tree. We assess the impact of these parameters on the ability of different reduction methods to successfully mitigate errors. Our results illustrate the pressing need for intelligent runtime selection of reduction operators that ensure a given degree of reproducible accuracy. To address the debugging challenge, our work examines the impact of logical clock ticking policies on the Clock-Delta Compression record-and-replay technique. We assess three logical clock ticking policies in terms of the number of out-of-order messages that result during recording executions under these policies. We examine the performance of Clock-Delta Compression when using the three ticking policies in four distinct application scenarios to probe the impact of floating-point workload and communication intensity on recording performance. Our results illustrate the pressing need for fine-grained logical clock ticking policies that reduce the out-of-order message rate of the Clock-Delta Compression record-and-replay technique.

rawabstract:
Non-determinism in high performance scientific applications has severe detrimental impacts for both numerical reproducibility and accuracy, and debugging. As scientific simulations are migrated to extreme-scale platforms, the increase in platform concurrency and the attendant increase in non-determinism is likely to exacerbate both of these problems. In this thesis, we address the dual challenges of non-determinism's impact on numerical reproducibility and on debugging. To address the numerical challenge, our work investigates the power of mathematical methods to mitigate error propagation at the exascale. We focus on floating-point error accumulation over global summations where enforcing any reduction order is expensive or impossible. We model parallel summations with reduction trees and identify those parameters that can be used to estimate the reduction's sensitivity to variability in the reduction tree. We assess the impact of these parameters on the ability of different reduction methods to successfully mitigate errors. Our results illustrate the pressing need for intelligent runtime selection of reduction operators that ensure a given degree of reproducible accuracy. To address the debugging challenge, our work examines the impact of logical clock ticking policies on the Clock-Delta Compression record-and-replay technique. We assess three logical clock ticking policies in terms of the number of out-of-order messages that result during recording executions under these policies. We examine the performance of Clock-Delta Compression when using the three ticking policies in four distinct application scenarios to probe the impact of floating-point workload and communication intensity on recording performance. Our results illustrate the pressing need for fine-grained logical clock ticking policies that reduce the out-of-order message rate of the Clock-Delta Compression record-and-replay technique.

entry:
@MastersThesis{Chapp:2017:SIN,
  author =       "Dylan Chapp",
  title =        "Study of the impact of non-determinism on numerical
                 reproducibility and debugging at the exascale",
  type =         "Master of Science in Computer Science",
  school =       "University of Delaware",
  address =      "Newark, DE, USA",
  pages =        "69",
  month =        "Spring",
  year =         "2017",
  ISBN =         "0-355-25168-X",
  ISBN-13 =      "978-0-355-25168-5",
  LCCN =         "????",
  bibdate =      "Mon Feb 10 06:07:39 MST 2020",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://udspace.udel.edu/handle/19716/24492;
                 https://search.proquest.com/pqdtglobal/docview/1957944576",
  abstract =     "Non-determinism in high performance scientific
                 applications has severe detrimental impacts for both
                 numerical reproducibility and accuracy, and debugging.
                 As scientific simulations are migrated to extreme-scale
                 platforms, the increase in platform concurrency and the
                 attendant increase in non-determinism is likely to
                 exacerbate both of these problems. In this thesis, we
                 address the dual challenges of non-determinism's impact
                 on numerical reproducibility and on debugging. To
                 address the numerical challenge, our work investigates
                 the power of mathematical methods to mitigate error
                 propagation at the exascale. We focus on floating-point
                 error accumulation over global summations where
                 enforcing any reduction order is expensive or
                 impossible. We model parallel summations with reduction
                 trees and identify those parameters that can be used to
                 estimate the reduction's sensitivity to variability in
                 the reduction tree. We assess the impact of these
                 parameters on the ability of different reduction
                 methods to successfully mitigate errors. Our results
                 illustrate the pressing need for intelligent runtime
                 selection of reduction operators that ensure a given
                 degree of reproducible accuracy. To address the
                 debugging challenge, our work examines the impact of
                 logical clock ticking policies on the Clock-Delta
                 Compression record-and-replay technique. We assess
                 three logical clock ticking policies in terms of the
                 number of out-of-order messages that result during
                 recording executions under these policies. We examine
                 the performance of Clock-Delta Compression when using
                 the three ticking policies in four distinct application
                 scenarios to probe the impact of floating-point
                 workload and communication intensity on recording
                 performance. Our results illustrate the pressing need
                 for fine-grained logical clock ticking policies that
                 reduce the out-of-order message rate of the Clock-Delta
                 Compression record-and-replay technique.",
  acknowledgement = ack-nhfb,
  advisor =      "Michela Taufer",
}


bibtype: inproceedings
filename: fparith.bib
label: Chiang:2017:RFP
booktitle: Proceedings of the ACM SIGPLAN Symposium on Principles of Programming Languages (POPL)
title: Rigorous Floating-Point Mixed-Precision Tuning
publisher: pub-ACM
address: pub-ACM:adr
pages: 300--315
year: 2017
DOI: https://doi.org/10.1145/3009837.3009846
bibdate: Fri Mar 31 10:00:31 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.03.31 10:00:31 ???
acknowledgement: ack-nhfb
rawbooktitle: Proceedings of the {ACM SIGPLAN Symposium on Principles of Programming Languages (POPL)}
rawtitle: Rigorous Floating-Point Mixed-Precision Tuning
author:
Wei-Fan Chiang and Mark Baranowski and Ian Briggs and Alexey Solovyev and Ganesh Gopalakrishnan and Zvonimir Rakamaric

abstract:
Virtually all real-valued computations are carried out using floating-point data types and operations. The precision of these data types must be set with the goals of reducing the overall round-off error, but also emphasizing performance improvements. Often, a mixed-precision allocation achieves this optimum; unfortunately, there are no techniques available to compute such allocations and conservatively meet a given error target across all program inputs. In this work, we present a rigorous approach to precision allocation based on formal analysis via Symbolic Taylor Expansions, and error analysis based on interval functions. This approach is implemented in an automated tool called FPTuner that generates and solves a quadratically constrained quadratic program to obtain a precision-annotated version of the given expression. FPTuner automatically introduces all the requisite precision up and down casting operations. It also allows users to flexibly control precision allocation using constraints to cap the number of high precision operators as well as group operators to allocate the same precision to facilitate vectorization. We evaluate FPTuner by tuning several benchmarks and measuring the proportion of lower precision operators allocated as we increase the error threshold. We also measure the reduction in energy consumption resulting from executing mixed-precision tuned code on a real hardware platform. We observe significant energy savings in response to mixed-precision tuning, but also observe situations where unexpected compiler behaviors thwart intended optimizations.

rawabstract:
Virtually all real-valued computations are carried out using floating-point data types and operations. The precision of these data types must be set with the goals of reducing the overall round-off error, but also emphasizing performance improvements. Often, a mixed-precision allocation achieves this optimum; unfortunately, there are no techniques available to compute such allocations and conservatively meet a given error target across all program inputs. In this work, we present a rigorous approach to precision allocation based on formal analysis via Symbolic Taylor Expansions, and error analysis based on interval functions. This approach is implemented in an automated tool called FPTuner that generates and solves a quadratically constrained quadratic program to obtain a precision-annotated version of the given expression. FPTuner automatically introduces all the requisite precision up and down casting operations. It also allows users to flexibly control precision allocation using constraints to cap the number of high precision operators as well as group operators to allocate the same precision to facilitate vectorization. We evaluate FPTuner by tuning several benchmarks and measuring the proportion of lower precision operators allocated as we increase the error threshold. We also measure the reduction in energy consumption resulting from executing mixed-precision tuned code on a real hardware platform. We observe significant energy savings in response to mixed-precision tuning, but also observe situations where unexpected compiler behaviors thwart intended optimizations.

rawauthor:
Wei-Fan Chiang and Mark Baranowski and Ian Briggs and Alexey Solovyev and Ganesh Gopalakrishnan and Zvonimir Rakamari{\'c}

entry:
@InProceedings{Chiang:2017:RFP,
  author =       "Wei-Fan Chiang and Mark Baranowski and Ian Briggs and
                 Alexey Solovyev and Ganesh Gopalakrishnan and Zvonimir
                 Rakamari{\'c}",
  booktitle =    "Proceedings of the {ACM SIGPLAN Symposium on
                 Principles of Programming Languages (POPL)}",
  title =        "Rigorous Floating-Point Mixed-Precision Tuning",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "300--315",
  year =         "2017",
  DOI =          "https://doi.org/10.1145/3009837.3009846",
  bibdate =      "Fri Mar 31 10:00:31 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Virtually all real-valued computations are carried out
                 using floating-point data types and operations. The
                 precision of these data types must be set with the
                 goals of reducing the overall round-off error, but also
                 emphasizing performance improvements. Often, a
                 mixed-precision allocation achieves this optimum;
                 unfortunately, there are no techniques available to
                 compute such allocations and conservatively meet a
                 given error target across all program inputs. In this
                 work, we present a rigorous approach to precision
                 allocation based on formal analysis via Symbolic Taylor
                 Expansions, and error analysis based on interval
                 functions. This approach is implemented in an automated
                 tool called FPTuner that generates and solves a
                 quadratically constrained quadratic program to obtain a
                 precision-annotated version of the given expression.
                 FPTuner automatically introduces all the requisite
                 precision up and down casting operations. It also
                 allows users to flexibly control precision allocation
                 using constraints to cap the number of high precision
                 operators as well as group operators to allocate the
                 same precision to facilitate vectorization. We evaluate
                 FPTuner by tuning several benchmarks and measuring the
                 proportion of lower precision operators allocated as we
                 increase the error threshold. We also measure the
                 reduction in energy consumption resulting from
                 executing mixed-precision tuned code on a real hardware
                 platform. We observe significant energy savings in
                 response to mixed-precision tuning, but also observe
                 situations where unexpected compiler behaviors thwart
                 intended optimizations.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Chohra:2017:RAR
author: Chemseddine Chohra and Philippe Langlois and David Parello
title: Reproducible, accurately rounded and efficient BLAS
crossref: Desprez:2017:EPP
pages: 609--620
year: 2017
DOI: https://doi.org/10.1007/978-3-319-58943-5_49
bibdate: Mon Feb 10 06:36:40 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 06:36:40 ???
acknowledgement: ack-nhfb
rawauthor: Chemseddine Chohra and Philippe Langlois and David Parello
rawtitle: Reproducible, accurately rounded and efficient {BLAS}
entry:
@InProceedings{Chohra:2017:RAR,
  author =       "Chemseddine Chohra and Philippe Langlois and David
                 Parello",
  title =        "Reproducible, accurately rounded and efficient
                 {BLAS}",
  crossref =     "Desprez:2017:EPP",
  pages =        "609--620",
  year =         "2017",
  DOI =          "https://doi.org/10.1007/978-3-319-58943-5_49",
  bibdate =      "Mon Feb 10 06:36:40 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Constantinides:2017:AAC
author: George Anthony Constantinides
title: Algorithms and Arithmetic: Choose Wisely
crossref: Burgess:2017:ISC
pages: 142--143
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.17
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: George Anthony Constantinides
rawtitle: Algorithms and Arithmetic: Choose Wisely
abstract:
I will introduce a semi-formalism to allow us to conceptually reason about the differences between customised arithmetic design, as one might see in FPGA-based compute, and general purpose arithmetic, as one might find in microprocessor design. This framework will, I hope, expose to the reader the reason that we should be thinking carefully about appropriate data representations when designing custom hardware for compute, as well as clearly showing the link between these decisions and algorithmic ones. I will then provide a concrete example from the literature on matrix computation where some careful algorithmic tweaking results in the ability to use fixed-point arithmetic and, hence, far higher performance than would otherwise be achieved.

keywords:
Algorithm design and analysis; arithmetic design; Automation; data representations; data structures; digital arithmetic; field programmable gate arrays; Field programmable gate arrays; fixed-point arithmetic; FPGA; general purpose arithmetic; Hardware; Kernel; logic design; matrix algebra; matrix computation; microprocessor design; Microprocessors; Signal processing algorithms

rawabstract:
I will introduce a semi-formalism to allow us to conceptually reason about the differences between customised arithmetic design, as one might see in FPGA-based compute, and general purpose arithmetic, as one might find in microprocessor design. This framework will, I hope, expose to the reader the reason that we should be thinking carefully about appropriate data representations when designing custom hardware for compute, as well as clearly showing the link between these decisions and algorithmic ones. I will then provide a concrete example from the literature on matrix computation where some careful algorithmic tweaking results in the ability to use fixed-point arithmetic and, hence, far higher performance than would otherwise be achieved.

entry:
@InProceedings{Constantinides:2017:AAC,
  author =       "George Anthony Constantinides",
  title =        "Algorithms and Arithmetic: Choose Wisely",
  crossref =     "Burgess:2017:ISC",
  pages =        "142--143",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.17",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "I will introduce a semi-formalism to allow us to
                 conceptually reason about the differences between
                 customised arithmetic design, as one might see in
                 FPGA-based compute, and general purpose arithmetic, as
                 one might find in microprocessor design. This framework
                 will, I hope, expose to the reader the reason that we
                 should be thinking carefully about appropriate data
                 representations when designing custom hardware for
                 compute, as well as clearly showing the link between
                 these decisions and algorithmic ones. I will then
                 provide a concrete example from the literature on
                 matrix computation where some careful algorithmic
                 tweaking results in the ability to use fixed-point
                 arithmetic and, hence, far higher performance than
                 would otherwise be achieved.",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; arithmetic design;
                 Automation; data representations; data structures;
                 digital arithmetic; field programmable gate arrays;
                 Field programmable gate arrays; fixed-point arithmetic;
                 FPGA; general purpose arithmetic; Hardware; Kernel;
                 logic design; matrix algebra; matrix computation;
                 microprocessor design; Microprocessors; Signal
                 processing algorithms",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2017:URE
author: Marius Cornea
title: ULPs and Relative Error
crossref: Burgess:2017:ISC
pages: 90--97
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.30
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Marius Cornea
rawtitle: {ULPs} and Relative Error
abstract:
The paper establishes several simple, but useful relationships between ulp (unit in the last place) errors and the corresponding relative errors. These can be used when converting between the two types of errors, ensuring that the least amount of information is lost in the process. The properties presented here were already useful in IEEE conformance proofs for iterative division and square root algorithms, and should be so again to numerical analysts both in 'hand' proofs of error bounds for floating-point computations, and in automated tools which carry out, or support deriving such proofs. In most cases, the properties shown herein establish tighter bounds than found in the literature. They also provide 'conversion' rules of finer granularity, at floating-point value level instead of binade level, and take into account the special conditions which occur at binade ends. For this reason, the paper includes a small, but non-negligible element of novelty.

keywords:
approximation; correctly rounded; error; floating point arithmetic; floating-point; floating-point computations; IEEE 754-2008; IEEE conformance proofs; iterative division; iterative methods; numerical analysis; quantum; relative error; square root algorithms; ULP; ulp; ulp error; unit in the last place

rawabstract:
The paper establishes several simple, but useful relationships between ulp (unit in the last place) errors and the corresponding relative errors. These can be used when converting between the two types of errors, ensuring that the least amount of information is lost in the process. The properties presented here were already useful in IEEE conformance proofs for iterative division and square root algorithms, and should be so again to numerical analysts both in 'hand' proofs of error bounds for floating-point computations, and in automated tools which carry out, or support deriving such proofs. In most cases, the properties shown herein establish tighter bounds than found in the literature. They also provide 'conversion' rules of finer granularity, at floating-point value level instead of binade level, and take into account the special conditions which occur at binade ends. For this reason, the paper includes a small, but non-negligible element of novelty.

entry:
@InProceedings{Cornea:2017:URE,
  author =       "Marius Cornea",
  title =        "{ULPs} and Relative Error",
  crossref =     "Burgess:2017:ISC",
  pages =        "90--97",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.30",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper establishes several simple, but useful
                 relationships between ulp (unit in the last place)
                 errors and the corresponding relative errors. These can
                 be used when converting between the two types of
                 errors, ensuring that the least amount of information
                 is lost in the process. The properties presented here
                 were already useful in IEEE conformance proofs for
                 iterative division and square root algorithms, and
                 should be so again to numerical analysts both in 'hand'
                 proofs of error bounds for floating-point computations,
                 and in automated tools which carry out, or support
                 deriving such proofs. In most cases, the properties
                 shown herein establish tighter bounds than found in the
                 literature. They also provide 'conversion' rules of
                 finer granularity, at floating-point value level
                 instead of binade level, and take into account the
                 special conditions which occur at binade ends. For this
                 reason, the paper includes a small, but non-negligible
                 element of novelty.",
  acknowledgement = ack-nhfb,
  keywords =     "approximation; correctly rounded; error; floating
                 point arithmetic; floating-point; floating-point
                 computations; IEEE 754-2008; IEEE conformance proofs;
                 iterative division; iterative methods; numerical
                 analysis; quantum; relative error; square root
                 algorithms; ULP; ulp; ulp error; unit in the last
                 place",
}


bibtype: article
filename: fparith.bib
label: Cui:2017:HPP
author: Xiaoping Cui and Wenwen Dong and Weiqiang Liu and Earl E. Swartzlander and Fabrizio Lombardi
title: High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 1994--2004
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2706262
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7931610/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Xiaoping Cui and Wenwen Dong and Weiqiang Liu and Earl E. Swartzlander and Fabrizio Lombardi
rawtitle: High Performance Parallel Decimal Multipliers Using Hybrid {BCD} Codes
entry:
@Article{Cui:2017:HPP,
  author =       "Xiaoping Cui and Wenwen Dong and Weiqiang Liu and Earl
                 E. Swartzlander and Fabrizio Lombardi",
  title =        "High Performance Parallel Decimal Multipliers Using
                 Hybrid {BCD} Codes",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "1994--2004",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2706262",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7931610/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Dai:2017:ATE
author: Wangchen Dai and Donald Donglong Chen and Ray C. C. Cheung and Cetin Kaya Koc
title: Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 3
pages: 375--388
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2016.2601334
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Feb 10 09:07:14 MST 2017
bibtimestamp: 2017.02.10 09:07:14 MST
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Wangchen Dai and Donald Donglong Chen and Ray C. C. Cheung and {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: Area-Time Efficient Architecture of {FFT}-Based {Montgomery} Multiplication
entry:
@Article{Dai:2017:ATE,
  author =       "Wangchen Dai and Donald Donglong Chen and Ray C. C.
                 Cheung and {\c{C}}etin Kaya Ko{\c{c}}",
  title =        "Area-Time Efficient Architecture of {FFT}-Based
                 {Montgomery} Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "3",
  pages =        "375--388",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2016.2601334",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 10 09:07:14 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Damouche:2017:INA
author: Nasrine Damouche and Matthieu Martel and Alexandre Chapoutot
title: Improving the numerical accuracy of programs by automatic transformation
journal: j-INT-J-SOFTW-TOOLS-TECHNOL-TRANSFER
volume: 19
number: 4
pages: 427--448
month: aug
monthnumber: 8
year: 2017
DOI: https://doi.org/10.1007/s10009-016-0435-0
ISSN: 1433-2779 (print), 1433-2787 (electronic) OR 14332779 (print), 14332787 (electronic)
ISSNL: 1433-2779 OR 14332779
bibdate: Thu Nov 23 07:32:25 MST 2017
bibtimestamp: 2017.11.23 07:32:25 MST
URL: https://link.springer.com/article/10.1007/s10009-016-0435-0
fjournal: International Journal on Software Tools for Technology Transfer (STTT)
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10009
rawauthor: Nasrine Damouche and Matthieu Martel and Alexandre Chapoutot
rawtitle: Improving the numerical accuracy of programs by automatic transformation
bibsource:
http://link.springer.com/journal/10009/19/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sttt.bib

keywords:
Floating-point numbers; IEEE 754 standard; Numerical accuracy; Program transformation; Static analysis

entry:
@Article{Damouche:2017:INA,
  author =       "Nasrine Damouche and Matthieu Martel and Alexandre
                 Chapoutot",
  title =        "Improving the numerical accuracy of programs by
                 automatic transformation",
  journal =      j-INT-J-SOFTW-TOOLS-TECHNOL-TRANSFER,
  volume =       "19",
  number =       "4",
  pages =        "427--448",
  month =        aug,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s10009-016-0435-0",
  ISSN =         "1433-2779 (print), 1433-2787 (electronic)",
  ISSN-L =       "1433-2779",
  bibdate =      "Thu Nov 23 07:32:25 MST 2017",
  bibsource =    "http://link.springer.com/journal/10009/19/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sttt.bib",
  URL =          "https://link.springer.com/article/10.1007/s10009-016-0435-0",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal on Software Tools for Technology
                 Transfer (STTT)",
  journal-URL =  "http://link.springer.com/journal/10009",
  keywords =     "Floating-point numbers; IEEE 754 standard; Numerical
                 accuracy; Program transformation; Static analysis",
}


bibtype: article
filename: fparith.bib
label: Darulova:2017:TCR
author: Eva Darulova and Viktor Kuncak
title: Towards a Compiler for Reals
journal: j-TOPLAS
volume: 39
number: 2
pages: 8:1--8:??
month: may
monthnumber: 5
year: 2017
CODEN: ATPSDT
DOI: https://doi.org/10.1145/3014426
ISSN: 0164-0925 (print), 1558-4593 (electronic) OR 01640925 (print), 15584593 (electronic)
ISSNL: 0164-0925 OR 01640925
bibdate: Mon Jul 24 09:44:40 MDT 2017
bibtimestamp: 2017.07.24 09:44:40 MDT
fjournal: ACM Transactions on Programming Languages and Systems
acknowledgement: ack-nhfb
articleno: 8
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J783
rawauthor: Eva Darulova and Viktor Kuncak
rawtitle: Towards a Compiler for Reals
bibsource:
http://www.acm.org/pubs/contents/journals/toplas/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toplas.bib

abstract:
Numerical software, common in scientific computing or embedded systems, inevitably uses a finite-precision approximation of the real arithmetic in which most algorithms are designed. In many applications, the roundoff errors introduced by finite-precision arithmetic are not the only source of inaccuracy, and measurement and other input errors further increase the uncertainty of the computed results. Adequate tools are needed to help users select suitable data types and evaluate the provided accuracy, especially for safety-critical applications. We present a source-to-source compiler called Rosa that takes as input a real-valued program with error specifications and synthesizes code over an appropriate floating-point or fixed-point data type. The main challenge of such a compiler is a fully automated, sound, and yet accurate-enough numerical error estimation. We introduce a unified technique for bounding roundoff errors from floating-point and fixed-point arithmetic of various precisions. The technique can handle nonlinear arithmetic, determine closed-form symbolic invariants for unbounded loops, and quantify the effects of discontinuities on numerical errors. We evaluate Rosa on a number of benchmarks from scientific computing and embedded systems and, comparing it to the state of the art in automated error estimation, show that it presents an interesting tradeoff between accuracy and performance.

rawabstract:
Numerical software, common in scientific computing or embedded systems, inevitably uses a finite-precision approximation of the real arithmetic in which most algorithms are designed. In many applications, the roundoff errors introduced by finite-precision arithmetic are not the only source of inaccuracy, and measurement and other input errors further increase the uncertainty of the computed results. Adequate tools are needed to help users select suitable data types and evaluate the provided accuracy, especially for safety-critical applications. We present a source-to-source compiler called Rosa that takes as input a real-valued program with error specifications and synthesizes code over an appropriate floating-point or fixed-point data type. The main challenge of such a compiler is a fully automated, sound, and yet accurate-enough numerical error estimation. We introduce a unified technique for bounding roundoff errors from floating-point and fixed-point arithmetic of various precisions. The technique can handle nonlinear arithmetic, determine closed-form symbolic invariants for unbounded loops, and quantify the effects of discontinuities on numerical errors. We evaluate Rosa on a number of benchmarks from scientific computing and embedded systems and, comparing it to the state of the art in automated error estimation, show that it presents an interesting tradeoff between accuracy and performance.

entry:
@Article{Darulova:2017:TCR,
  author =       "Eva Darulova and Viktor Kuncak",
  title =        "Towards a Compiler for Reals",
  journal =      j-TOPLAS,
  volume =       "39",
  number =       "2",
  pages =        "8:1--8:??",
  month =        may,
  year =         "2017",
  CODEN =        "ATPSDT",
  DOI =          "https://doi.org/10.1145/3014426",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Mon Jul 24 09:44:40 MDT 2017",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toplas/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toplas.bib",
  abstract =     "Numerical software, common in scientific computing or
                 embedded systems, inevitably uses a finite-precision
                 approximation of the real arithmetic in which most
                 algorithms are designed. In many applications, the
                 roundoff errors introduced by finite-precision
                 arithmetic are not the only source of inaccuracy, and
                 measurement and other input errors further increase the
                 uncertainty of the computed results. Adequate tools are
                 needed to help users select suitable data types and
                 evaluate the provided accuracy, especially for
                 safety-critical applications. We present a
                 source-to-source compiler called Rosa that takes as
                 input a real-valued program with error specifications
                 and synthesizes code over an appropriate floating-point
                 or fixed-point data type. The main challenge of such a
                 compiler is a fully automated, sound, and yet
                 accurate-enough numerical error estimation. We
                 introduce a unified technique for bounding roundoff
                 errors from floating-point and fixed-point arithmetic
                 of various precisions. The technique can handle
                 nonlinear arithmetic, determine closed-form symbolic
                 invariants for unbounded loops, and quantify the
                 effects of discontinuities on numerical errors. We
                 evaluate Rosa on a number of benchmarks from scientific
                 computing and embedded systems and, comparing it to the
                 state of the art in automated error estimation, show
                 that it presents an interesting tradeoff between
                 accuracy and performance.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J783",
}


bibtype: article
filename: fparith.bib
label: David:2017:LLD
author: Jean Pierre David
title: Low latency and division free Gauss--Jordan solver in floating point arithmetic
journal: j-J-PAR-DIST-COMP
volume: 106
pages: 185--193
month: aug
monthnumber: 8
year: 2017
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Aug 19 13:10:31 MDT 2017
bibtimestamp: 2017.08.19 13:10:31 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0743731516301897
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: Jean Pierre David
rawtitle: Low latency and division free {Gauss--Jordan} solver in floating point arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib

entry:
@Article{David:2017:LLD,
  author =       "Jean Pierre David",
  title =        "Low latency and division free {Gauss--Jordan} solver
                 in floating point arithmetic",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "106",
  number =       "??",
  pages =        "185--193",
  month =        aug,
  year =         "2017",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Aug 19 13:10:31 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0743731516301897",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: article
filename: fparith.bib
label: Dawson:2017:RVE
author: Andrew Dawson and Peter D. Duben
title: rpe v5: an emulator for reduced floating-point precision in large numerical simulations
journal: j-GEOSCI-MODEL-DEV
volume: 10
number: 6
pages: 2221--2230
month: jun
monthnumber: 6
year: 2017
DOI: https://doi.org/10.5194/gmd-10-2221-2017
ISSN: 1991-959X (print), 1991-9603 (electronic) OR 1991959X (print), 19919603 (electronic)
ISSNL: 1991-959X OR 1991959X
bibdate: Thu Nov 7 16:40:41 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.11.07 16:40:41 ???
fjournal: Geoscientific Model Development
acknowledgement: ack-nhfb
journalURL: http://www.geosci-model-dev.net
rawauthor: Andrew Dawson and Peter D. D{\"u}ben
rawtitle: {rpe v5}: an emulator for reduced floating-point precision in large numerical simulations
entry:
@Article{Dawson:2017:RVE,
  author =       "Andrew Dawson and Peter D. D{\"u}ben",
  title =        "{rpe v5}: an emulator for reduced floating-point
                 precision in large numerical simulations",
  journal =      j-GEOSCI-MODEL-DEV,
  volume =       "10",
  number =       "6",
  pages =        "2221--2230",
  month =        jun,
  year =         "2017",
  DOI =          "https://doi.org/10.5194/gmd-10-2221-2017",
  ISSN =         "1991-959X (print), 1991-9603 (electronic)",
  ISSN-L =       "1991-959X",
  bibdate =      "Thu Nov 7 16:40:41 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Geoscientific Model Development",
  journal-URL =  "http://www.geosci-model-dev.net",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimitrov:2017:PMC
title: A Parallel Method for the Computation of Matrix Exponential Based on Truncated Neumann Series
crossref: Burgess:2017:ISC
pages: 35--42
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.23
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawtitle: A Parallel Method for the Computation of Matrix Exponential Based on Truncated {Neumann} Series
author:
Vassil Dimitrov and Viduneth Ariyarathna and Diego F. G. Coelho and Logan Rakai and Arjuna Madanayake and Renato J. Cintra

abstract:
This paper introduces a new method for computing matrix exponential based on truncated Neumann series. The efficiency of the method is based on smart factorizations for evaluation of several Neumann series that can be done in parallel and divided across different processors with low communication overhead. A physical realization on FPGA is provided for proof-of-concept. The method is verified to be advantageous over the usual Horner's rule approach for polynomial evaluation. The hardware verification shows a reduction of 62% in time required for processing for series approximations with 9 terms. Software verification demonstrates a 30% reduction in time compared to Horner's rule and the trade-offs between using a higher precision approach is illustrated.

keywords:
Approximation algorithms; approximation theory; Eigenvalues and eigenfunctions; Error analysis; Fast algorithms; field programmable gate arrays; FPGA; Hardware; Horner's rule approach; low communication overhead; matrix algebra; matrix decomposition; matrix exponential; Matrix exponential; Neumann series; parallel method; polynomial evaluation; polynomials; Program processors; series (mathematics); series approximations; smart factorizations; Software algorithms; software verification; truncated Neumann series; VLSI

rawabstract:
This paper introduces a new method for computing matrix exponential based on truncated Neumann series. The efficiency of the method is based on smart factorizations for evaluation of several Neumann series that can be done in parallel and divided across different processors with low communication overhead. A physical realization on FPGA is provided for proof-of-concept. The method is verified to be advantageous over the usual Horner's rule approach for polynomial evaluation. The hardware verification shows a reduction of 62\% in time required for processing for series approximations with 9 terms. Software verification demonstrates a 30\% reduction in time compared to Horner's rule and the trade-offs between using a higher precision approach is illustrated.

rawauthor:
Vassil Dimitrov and Viduneth Ariyarathna and Diego F. G. Coelho and Logan Rakai and Arjuna Madanayake and Renato J. Cintra

entry:
@InProceedings{Dimitrov:2017:PMC,
  author =       "Vassil Dimitrov and Viduneth Ariyarathna and Diego F.
                 G. Coelho and Logan Rakai and Arjuna Madanayake and
                 Renato J. Cintra",
  title =        "A Parallel Method for the Computation of Matrix
                 Exponential Based on Truncated {Neumann} Series",
  crossref =     "Burgess:2017:ISC",
  pages =        "35--42",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.23",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper introduces a new method for computing
                 matrix exponential based on truncated Neumann series.
                 The efficiency of the method is based on smart
                 factorizations for evaluation of several Neumann series
                 that can be done in parallel and divided across
                 different processors with low communication overhead. A
                 physical realization on FPGA is provided for
                 proof-of-concept. The method is verified to be
                 advantageous over the usual Horner's rule approach for
                 polynomial evaluation. The hardware verification shows
                 a reduction of 62\% in time required for processing for
                 series approximations with 9 terms. Software
                 verification demonstrates a 30\% reduction in time
                 compared to Horner's rule and the trade-offs between
                 using a higher precision approach is illustrated.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; approximation theory;
                 Eigenvalues and eigenfunctions; Error analysis; Fast
                 algorithms; field programmable gate arrays; FPGA;
                 Hardware; Horner's rule approach; low communication
                 overhead; matrix algebra; matrix decomposition; matrix
                 exponential; Matrix exponential; Neumann series;
                 parallel method; polynomial evaluation; polynomials;
                 Program processors; series (mathematics); series
                 approximations; smart factorizations; Software
                 algorithms; software verification; truncated Neumann
                 series; VLSI",
}


bibtype: article
filename: fparith.bib
label: Du:2017:AQD
author: Peibing Du and Roberto Barrio and Hao Jiang and Lizhi Cheng
title: Accurate quotient-difference algorithm: Error analysis, improvements and applications
journal: j-APPL-MATH-COMP
volume: 309
pages: 245--271
day: 15
month: sep
monthnumber: 9
year: 2017
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Aug 12 16:28:39 MDT 2017
bibtimestamp: 2017.08.12 16:28:39 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0096300317302394
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Peibing Du and Roberto Barrio and Hao Jiang and Lizhi Cheng
rawtitle: Accurate quotient-difference algorithm: Error analysis, improvements and applications
bibsource:
https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Du:2017:AQD,
  author =       "Peibing Du and Roberto Barrio and Hao Jiang and Lizhi
                 Cheng",
  title =        "Accurate quotient-difference algorithm: Error
                 analysis, improvements and applications",
  journal =      j-APPL-MATH-COMP,
  volume =       "309",
  number =       "??",
  pages =        "245--271",
  day =          "15",
  month =        sep,
  year =         "2017",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Aug 12 16:28:39 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0096300317302394",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: book
filename: fparith.bib
label: Esmay:2017:HNS
author: Gabriel Esmay
title: The History of Number Systems
publisher: Teacher Created Materials
address: Huntington Beach, CA
pages: 32
year: 2017
LCCN: QA141.3 .E86 2018
bibdate: Fri Mar 17 08:27:53 MDT 2023
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.03.17 08:27:53 MDT
acknowledgement: ack-nhfb
rawauthor: Gabriel Esmay
rawtitle: The History of Number Systems
ISBN:
0-7439-2834-2 (e-book), 1-0876-2972-1, 1-4807-5794-2 (paperback), 1-4807-5858-2 (e-book) OR 0743928342 (ebook), 1087629721, 1480757942 (paperback), 1480758582 (ebook)

ISBN13:
978-0-7439-2834-2 (e-book), 978-1-0876-2972-8, 978-1-4807-5794-3 (paperback), 978-1-4807-5858-2 (e-book) OR 9780743928342 (ebook), 9781087629728, 9781480757943 (paperback), 9781480758582 (ebook)

abstract:
Learn the history of number systems with this engaging math reader! This text combines mathematics and literacy skills, and uses practical, real-world examples of problem solving to teach math and language arts content. Students will learn place value while reading about the number systems of the Egyptians and Romans, and also learn important vocabulary terms like cuneiform, binary systems, roman numerals, and more! The full-color images, math charts, and practice problems make learning math easy and fun. The table of contents, glossary, and index will further understanding of math and reading concepts. The Math Talk problems and Explore Math sidebars provide additional learning opportunities while developing students higher-order thinking skills.

subject:
Numeration; History; Juvenile literature; Counting; Calcul; Ouvrages pour la jeunesse; Counting.; Numeration.

TOC:
Timeless need Egypt Babylon Roman empire Americas Modern beginnings Future of number systems Problem solving Glossary

rawabstract:
Learn the history of number systems with this engaging math reader! This text combines mathematics and literacy skills, and uses practical, real-world examples of problem solving to teach math and language arts content. Students will learn place value while reading about the number systems of the Egyptians and Romans, and also learn important vocabulary terms like cuneiform, binary systems, roman numerals, and more! The full-color images, math charts, and practice problems make learning math easy and fun. The table of contents, glossary, and index will further understanding of math and reading concepts. The Math Talk problems and Explore Math sidebars provide additional learning opportunities while developing students higher-order thinking skills.

rawTOC:
Timeless need \\ Egypt \\ Babylon \\ Roman empire \\ Americas \\ Modern beginnings \\ Future of number systems \\ Problem solving \\ Glossary

entry:
@Book{Esmay:2017:HNS,
  author =       "Gabriel Esmay",
  title =        "The History of Number Systems",
  publisher =    "Teacher Created Materials",
  address =      "Huntington Beach, CA",
  pages =        "32",
  year =         "2017",
  ISBN =         "0-7439-2834-2 (e-book), 1-0876-2972-1, 1-4807-5794-2
                 (paperback), 1-4807-5858-2 (e-book)",
  ISBN-13 =      "978-0-7439-2834-2 (e-book), 978-1-0876-2972-8,
                 978-1-4807-5794-3 (paperback), 978-1-4807-5858-2
                 (e-book)",
  LCCN =         "QA141.3 .E86 2018",
  bibdate =      "Fri Mar 17 08:27:53 MDT 2023",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Learn the history of number systems with this engaging
                 math reader! This text combines mathematics and
                 literacy skills, and uses practical, real-world
                 examples of problem solving to teach math and language
                 arts content. Students will learn place value while
                 reading about the number systems of the Egyptians and
                 Romans, and also learn important vocabulary terms like
                 cuneiform, binary systems, roman numerals, and more!
                 The full-color images, math charts, and practice
                 problems make learning math easy and fun. The table of
                 contents, glossary, and index will further
                 understanding of math and reading concepts. The Math
                 Talk problems and Explore Math sidebars provide
                 additional learning opportunities while developing
                 students higher-order thinking skills.",
  acknowledgement = ack-nhfb,
  subject =      "Numeration; History; Juvenile literature; Counting;
                 Calcul; Ouvrages pour la jeunesse; Counting.;
                 Numeration.",
  tableofcontents = "Timeless need \\
                 Egypt \\
                 Babylon \\
                 Roman empire \\
                 Americas \\
                 Modern beginnings \\
                 Future of number systems \\
                 Problem solving \\
                 Glossary",
}


bibtype: misc
filename: fparith.bib
label: Fevotte:2017:LLI
author: Francois Fevotte and Bruno Lathuiliere
title: LibEFT: a library implementing Error-Free transformations
pages: 32
year: 2017
bibdate: Sat Feb 08 10:47:59 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 10:47:59 ???
URL: https://github.com/ffevotte/libeft
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Fran{\c{c}}ois F{\'e}votte and Bruno Lathuili{\`e}re
rawtitle: {LibEFT}: a library implementing Error-Free transformations
entry:
@Misc{Fevotte:2017:LLI,
  author =       "Fran{\c{c}}ois F{\'e}votte and Bruno Lathuili{\`e}re",
  title =        "{LibEFT}: a library implementing Error-Free
                 transformations",
  howpublished = "Web site.",
  year =         "2017",
  bibdate =      "Sat Feb 08 10:47:59 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://github.com/ffevotte/libeft",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Fu:2017:AHC
author: Zhoulai Fu and Zhendong Su
title: Achieving high coverage for floating-point code via unconstrained programming
journal: j-SIGPLAN
volume: 52
number: 6
pages: 306--319
month: jun
monthnumber: 6
year: 2017
CODEN: SINODQ
DOI: https://doi.org/10.1145/3140587.3062383
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sat Sep 16 10:18:17 MDT 2017
bibtimestamp: 2017.09.16 10:18:17 MDT
fjournal: ACM SIGPLAN Notices
remark: PLDI '17 conference proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Zhoulai Fu and Zhendong Su
rawtitle: Achieving high coverage for floating-point code via unconstrained programming
abstract:
Achieving high code coverage is essential in testing, which gives us confidence in code quality. Testing floating-point code usually requires painstaking efforts in handling floating-point constraints, e.g., in symbolic execution. This paper turns the challenge of testing floating-point code into the opportunity of applying unconstrained programming --- the mathematical solution for calculating function minimum points over the entire search space. Our core insight is to derive a representing function from the floating-point program, any of whose minimum points is a test input guaranteed to exercise a new branch of the tested program. This guarantee allows us to achieve high coverage of the floating-point program by repeatedly minimizing the representing function. We have realized this approach in a tool called CoverMe and conducted an extensive evaluation of it on Sun's C math library. Our evaluation results show that CoverMe achieves, on average, 90.8% branch coverage in 6.9 seconds, drastically outperforming our compared tools: (1) Random testing, (2) AFL, a highly optimized, robust fuzzer released by Google, and (3) Austin, a state-of-the-art coverage-based testing tool designed to support floating-point code.

rawabstract:
Achieving high code coverage is essential in testing, which gives us confidence in code quality. Testing floating-point code usually requires painstaking efforts in handling floating-point constraints, e.g., in symbolic execution. This paper turns the challenge of testing floating-point code into the opportunity of applying unconstrained programming --- the mathematical solution for calculating function minimum points over the entire search space. Our core insight is to derive a representing function from the floating-point program, any of whose minimum points is a test input guaranteed to exercise a new branch of the tested program. This guarantee allows us to achieve high coverage of the floating-point program by repeatedly minimizing the representing function. We have realized this approach in a tool called CoverMe and conducted an extensive evaluation of it on Sun's C math library. Our evaluation results show that CoverMe achieves, on average, 90.8\% branch coverage in 6.9 seconds, drastically outperforming our compared tools: (1) Random testing, (2) AFL, a highly optimized, robust fuzzer released by Google, and (3) Austin, a state-of-the-art coverage-based testing tool designed to support floating-point code.

entry:
@Article{Fu:2017:AHC,
  author =       "Zhoulai Fu and Zhendong Su",
  title =        "Achieving high coverage for floating-point code via
                 unconstrained programming",
  journal =      j-SIGPLAN,
  volume =       "52",
  number =       "6",
  pages =        "306--319",
  month =        jun,
  year =         "2017",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3140587.3062383",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sat Sep 16 10:18:17 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "Achieving high code coverage is essential in testing,
                 which gives us confidence in code quality. Testing
                 floating-point code usually requires painstaking
                 efforts in handling floating-point constraints, e.g.,
                 in symbolic execution. This paper turns the challenge
                 of testing floating-point code into the opportunity of
                 applying unconstrained programming --- the mathematical
                 solution for calculating function minimum points over
                 the entire search space. Our core insight is to derive
                 a representing function from the floating-point
                 program, any of whose minimum points is a test input
                 guaranteed to exercise a new branch of the tested
                 program. This guarantee allows us to achieve high
                 coverage of the floating-point program by repeatedly
                 minimizing the representing function. We have realized
                 this approach in a tool called CoverMe and conducted an
                 extensive evaluation of it on Sun's C math library. Our
                 evaluation results show that CoverMe achieves, on
                 average, 90.8\% branch coverage in 6.9 seconds,
                 drastically outperforming our compared tools: (1)
                 Random testing, (2) AFL, a highly optimized, robust
                 fuzzer released by Google, and (3) Austin, a
                 state-of-the-art coverage-based testing tool designed
                 to support floating-point code.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "PLDI '17 conference proceedings.",
}


bibtype: article
filename: fparith.bib
label: Fumex:2017:AVF
author: Clement Fumex and Claude Marche and Yannick Moy
editor: Andrei Paskevich and Thomas Wies
title: Automating the Verification of Floating-Point Programs
journal: j-LECT-NOTES-COMP-SCI
volume: 10712
publisher: pub-SV
address: pub-SV:adr
pages: 102--119
year: 2017
DOI: https://doi.org/10.1007/978-3-319-72308-2_7
ISBN: 3-319-72308-1 OR 3319723081
ISBN13: 978-3-319-72308-2 OR 9783319723082
ISSN: 1611-3349 OR 16113349
bibdate: Sat Jun 8 09:04:13 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.06.08 09:04:13 ???
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-319-72308-2
rawauthor: Cl{\'e}ment Fumex and Claude March{\'e} and Yannick Moy
raweditor: Andrei Paskevich and Thomas Wies
rawtitle: Automating the Verification of Floating-Point Programs
booktitle:
Verified Software. Theories, Tools, and Experiments: 9th International Conference, VSTTE 2017, Heidelberg, Germany, July 22--23, 2017, Revised Selected Papers

rawbooktitle:
Verified Software. Theories, Tools, and Experiments: {9th International Conference, VSTTE 2017, Heidelberg, Germany, July 22--23, 2017, Revised Selected Papers}

entry:
@Article{Fumex:2017:AVF,
  author =       "Cl{\'e}ment Fumex and Claude March{\'e} and Yannick
                 Moy",
  editor =       "Andrei Paskevich and Thomas Wies",
  booktitle =    "Verified Software. Theories, Tools, and Experiments:
                 {9th International Conference, VSTTE 2017, Heidelberg,
                 Germany, July 22--23, 2017, Revised Selected Papers}",
  title =        "Automating the Verification of Floating-Point
                 Programs",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "10712",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "102--119",
  year =         "2017",
  DOI =          "https://doi.org/10.1007/978-3-319-72308-2_7",
  ISBN =         "3-319-72308-1",
  ISBN-13 =      "978-3-319-72308-2",
  ISSN =         "1611-3349",
  bibdate =      "Sat Jun 8 09:04:13 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-319-72308-2",
}


bibtype: inproceedings
filename: fparith.bib
label: Gonzalez-Navarro:2017:NNO
author: Sonia Gonzalez-Navarro and Javier Hormigo
title: Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems
crossref: Burgess:2017:ISC
pages: 188--195
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.16
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Sonia Gonzalez-Navarro and Javier Hormigo
abstract:
Emerging embedded applications lack of a specific standard when they require floating-point arithmetic. In this situation they use the IEEE-754 standard or ad hoc variations of it. However, this standard was not designed for this purpose. This paper aims to open a debate to define a new extension of the standard to cover embedded applications. In this work, we only focus on the impact of not performing normalization. We show how eliminating the condition of normalized numbers, implementation costs can be dramatically reduced, at the expense of a moderate loss of accuracy. Several architectures to implement addition and multiplication for non-normalized numbers are proposed and analyzed. We show that a combined architecture (adder-multiplier) can halve the area and power consumption of its counterpart IEEE-754 architecture. This saving comes at the cost of reducing an average of about 10 dBs the Signal-to-Noise Ratio for the tested algorithms. We think these results should encourage researchers to perform further investigation in this issue.

keywords:
ad hoc variations; adder-multiplier; adders; Adders; Computer architecture; DSP; embedded applications; embedded systems; Embedded systems; embedded systems; Field programmable gate arrays; floating point arithmetic; floating-point; floating-point arithmetic; Hardware; IEEE standards; IEEE-754 architecture; IEEE-754 standard; Loss measurement; nonnormalized numbers; Normalization; normalized number condition; power consumption; signal-to-noise ratio; standard; Standards

rawabstract:
Emerging embedded applications lack of a specific standard when they require floating-point arithmetic. In this situation they use the IEEE-754 standard or ad hoc variations of it. However, this standard was not designed for this purpose. This paper aims to open a debate to define a new extension of the standard to cover embedded applications. In this work, we only focus on the impact of not performing normalization. We show how eliminating the condition of normalized numbers, implementation costs can be dramatically reduced, at the expense of a moderate loss of accuracy. Several architectures to implement addition and multiplication for non-normalized numbers are proposed and analyzed. We show that a combined architecture (adder-multiplier) can halve the area and power consumption of its counterpart IEEE-754 architecture. This saving comes at the cost of reducing an average of about 10 dBs the Signal-to-Noise Ratio for the tested algorithms. We think these results should encourage researchers to perform further investigation in this issue.

rawtitle:
Normalizing or Not Normalizing? {An} Open Question for Floating-Point Arithmetic in Embedded Systems

entry:
@InProceedings{Gonzalez-Navarro:2017:NNO,
  author =       "Sonia Gonzalez-Navarro and Javier Hormigo",
  title =        "Normalizing or Not Normalizing? {An} Open Question for
                 Floating-Point Arithmetic in Embedded Systems",
  crossref =     "Burgess:2017:ISC",
  pages =        "188--195",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.16",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Emerging embedded applications lack of a specific
                 standard when they require floating-point arithmetic.
                 In this situation they use the IEEE-754 standard or ad
                 hoc variations of it. However, this standard was not
                 designed for this purpose. This paper aims to open a
                 debate to define a new extension of the standard to
                 cover embedded applications. In this work, we only
                 focus on the impact of not performing normalization. We
                 show how eliminating the condition of normalized
                 numbers, implementation costs can be dramatically
                 reduced, at the expense of a moderate loss of accuracy.
                 Several architectures to implement addition and
                 multiplication for non-normalized numbers are proposed
                 and analyzed. We show that a combined architecture
                 (adder-multiplier) can halve the area and power
                 consumption of its counterpart IEEE-754 architecture.
                 This saving comes at the cost of reducing an average of
                 about 10 dBs the Signal-to-Noise Ratio for the tested
                 algorithms. We think these results should encourage
                 researchers to perform further investigation in this
                 issue.",
  acknowledgement = ack-nhfb,
  keywords =     "ad hoc variations; adder-multiplier; adders; Adders;
                 Computer architecture; DSP; embedded applications;
                 embedded systems; Embedded systems; embedded systems;
                 Field programmable gate arrays; floating point
                 arithmetic; floating-point; floating-point arithmetic;
                 Hardware; IEEE standards; IEEE-754 architecture;
                 IEEE-754 standard; Loss measurement; nonnormalized
                 numbers; Normalization; normalized number condition;
                 power consumption; signal-to-noise ratio; standard;
                 Standards",
}


bibtype: article
filename: fparith.bib
label: Gorantla:2017:DAC
author: Anusha Gorantla and Deepa P.
title: Design of Approximate Compressors for Multiplication
journal: j-JETC
volume: 13
number: 3
pages: 44:1--44:??
month: may
monthnumber: 5
year: 2017
DOI: https://doi.org/10.1145/3007649
ISSN: 1550-4832 (print), 1550-4840 (electronic) OR 15504832 (print), 15504840 (electronic)
ISSNL: 1550-4832 OR 15504832
bibdate: Tue Jul 11 17:10:31 MDT 2017
bibtimestamp: 2017.07.11 17:10:31 MDT
fjournal: ACM Journal on Emerging Technologies in Computing Systems (JETC)
acknowledgement: ack-nhfb
articleno: 44
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J967
rawauthor: Anusha Gorantla and Deepa P.
rawtitle: Design of Approximate Compressors for Multiplication
bibsource:
http://www.acm.org/pubs/contents/journals/jetc/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jetc.bib

abstract:
Approximate computing is a promising technique for energy-efficient Very Large Scale Integration (VLSI) system design. It is best suited for error-resilient applications such as signal processing and multimedia. Approximate computing reduces accuracy but still provides significant and faster results with lower power consumption. This is attractive to arithmetic circuits. In this article, various novel design approaches of approximate 4-2 and 5-2 compressors have been proposed for reduction of the partial product stages in multiplication. Three approximate 8 $ times $ 8 Dadda multiplier designs using three novel approximate 4-2 compressors and two approximate 8 $ times $ 8 Dadda multiplier designs using two novel approximate 5-2 compressors have proposed. The synthesis results show that the proposed designs achieved significant accuracy improvement together with power and delay reductions compared to the existing approximate designs.

rawabstract:
Approximate computing is a promising technique for energy-efficient Very Large Scale Integration (VLSI) system design. It is best suited for error-resilient applications such as signal processing and multimedia. Approximate computing reduces accuracy but still provides significant and faster results with lower power consumption. This is attractive to arithmetic circuits. In this article, various novel design approaches of approximate 4-2 and 5-2 compressors have been proposed for reduction of the partial product stages in multiplication. Three approximate 8 $ \times $ 8 Dadda multiplier designs using three novel approximate 4-2 compressors and two approximate 8 $ \times $ 8 Dadda multiplier designs using two novel approximate 5-2 compressors have proposed. The synthesis results show that the proposed designs achieved significant accuracy improvement together with power and delay reductions compared to the existing approximate designs.

entry:
@Article{Gorantla:2017:DAC,
  author =       "Anusha Gorantla and Deepa P.",
  title =        "Design of Approximate Compressors for Multiplication",
  journal =      j-JETC,
  volume =       "13",
  number =       "3",
  pages =        "44:1--44:??",
  month =        may,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3007649",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Jul 11 17:10:31 MDT 2017",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Approximate computing is a promising technique for
                 energy-efficient Very Large Scale Integration (VLSI)
                 system design. It is best suited for error-resilient
                 applications such as signal processing and multimedia.
                 Approximate computing reduces accuracy but still
                 provides significant and faster results with lower
                 power consumption. This is attractive to arithmetic
                 circuits. In this article, various novel design
                 approaches of approximate 4-2 and 5-2 compressors have
                 been proposed for reduction of the partial product
                 stages in multiplication. Three approximate 8 $ \times
                 $ 8 Dadda multiplier designs using three novel
                 approximate 4-2 compressors and two approximate 8 $
                 \times $ 8 Dadda multiplier designs using two novel
                 approximate 5-2 compressors have proposed. The
                 synthesis results show that the proposed designs
                 achieved significant accuracy improvement together with
                 power and delay reductions compared to the existing
                 approximate designs.",
  acknowledgement = ack-nhfb,
  articleno =    "44",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}


bibtype: techreport
filename: fparith.bib
label: Graillat:2017:AAE
author: Stef Graillat
title: An accurate algorithm for evaluating rational functions
type: Report
number: HAL-01578486
institution: Laboratoire d'Informatique de Paris 6, Universite Sorbonne, Campus Pierre et Marie Curie
address: 4, place Jussieu, F-75252 Paris Cedex 05, France
pages: 44:1--44:??
day: 29
month: aug
monthnumber: 8
year: 2017
MRclass: 15-04 65G99 65-04
bibdate: Mon Mar 19 08:17:18 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.19 08:17:18 ???
URL: https://hal.archives-ouvertes.fr/hal-01578486
acknowledgement: ack-nhfb
rawauthor: Stef Graillat
rawtitle: An accurate algorithm for evaluating rational functions
abstract:
Several different techniques intend to improve the accuracy of results computed in floating-point precision. Here, we focus on a method to improve the accuracy of the evaluation of rational functions. We present a compensated algorithm to evaluate rational functions. This algorithm is accurate and fast. The accuracy of the computed result is similar to the one given by the classical algorithm computed in twice the working precision and then rounded to the current working precision. This algorithm runs much more faster than existing implementation producing the same output accuracy.

keywords:
accuracy; error-free transformation; floating-point; Horner scheme; rational function; rounding errors

rawabstract:
Several different techniques intend to improve the accuracy of results computed in floating-point precision. Here, we focus on a method to improve the accuracy of the evaluation of rational functions. We present a compensated algorithm to evaluate rational functions. This algorithm is accurate and fast. The accuracy of the computed result is similar to the one given by the classical algorithm computed in twice the working precision and then rounded to the current working precision. This algorithm runs much more faster than existing implementation producing the same output accuracy.

entry:
@TechReport{Graillat:2017:AAE,
  author =       "Stef Graillat",
  title =        "An accurate algorithm for evaluating rational
                 functions",
  type =         "Report",
  number =       "HAL-01578486",
  institution =  "Laboratoire d'Informatique de Paris 6, Universit{\'e}
                 Sorbonne, Campus Pierre et Marie Curie",
  address =      "4, place Jussieu, F-75252 Paris Cedex 05, France",
  day =          "29",
  month =        aug,
  year =         "2017",
  MRclass =      "15-04 65G99 65-04",
  bibdate =      "Mon Mar 19 08:17:18 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.archives-ouvertes.fr/hal-01578486",
  abstract =     "Several different techniques intend to improve the
                 accuracy of results computed in floating-point
                 precision. Here, we focus on a method to improve the
                 accuracy of the evaluation of rational functions. We
                 present a compensated algorithm to evaluate rational
                 functions. This algorithm is accurate and fast. The
                 accuracy of the computed result is similar to the one
                 given by the classical algorithm computed in twice the
                 working precision and then rounded to the current
                 working precision. This algorithm runs much more faster
                 than existing implementation producing the same output
                 accuracy.",
  acknowledgement = ack-nhfb,
  keywords =     "accuracy; error-free transformation; floating-point;
                 Horner scheme; rational function; rounding errors",
}


bibtype: inproceedings
filename: fparith.bib
label: Guney:2017:OMM
title: Optimizing Matrix Multiplication on Intel Xeon Phi TH x200 Architecture
crossref: Burgess:2017:ISC
pages: 144--145
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.19
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawtitle: Optimizing Matrix Multiplication on {Intel Xeon Phi TH x200} Architecture
author:
Murat Efe Guney and Kazushige Goto and Timothy B. Costa and Sarah Knepper and Louise Huot and Arthur Mitrano and Shane Story

abstract:
Matrix multiplication is ubiquitous in scientific computing. From computational science to machine learning, a large and diverse set of applications rely on the performance of general matrix-matrix multiplication (GEMM) subroutines. The Intel Math Kernel Library(R) provides highly optimized GEMM subroutines that take full advantage of the available parallelism and vectorization in both Intel Xeon and Intel Xeon Phi(TM) processors. In this paper we discuss the optimization of GEMM subroutines for the Intel Xeon PhiTM x200 (code-named Knights Landing).

keywords:
Algorithms; Bandwidth; blas; computational science; Computer architecture; general matrix-matrix multiplication; Intel Math Kernel Library; intel xeon phi; Intel Xeon Phi x200 architecture; Kernel; Knights Landing; machine learning; matrix multiplication; microprocessor chips; Optimization; performance optimization; Prefetching; processors; scientific computing

rawabstract:
Matrix multiplication is ubiquitous in scientific computing. From computational science to machine learning, a large and diverse set of applications rely on the performance of general matrix-matrix multiplication (GEMM) subroutines. The Intel Math Kernel Library(R) provides highly optimized GEMM subroutines that take full advantage of the available parallelism and vectorization in both Intel Xeon and Intel Xeon Phi(TM) processors. In this paper we discuss the optimization of GEMM subroutines for the Intel Xeon PhiTM x200 (code-named Knights Landing).

rawauthor:
Murat Efe Guney and Kazushige Goto and Timothy B. Costa and Sarah Knepper and Louise Huot and Arthur Mitrano and Shane Story

entry:
@InProceedings{Guney:2017:OMM,
  author =       "Murat Efe Guney and Kazushige Goto and Timothy B.
                 Costa and Sarah Knepper and Louise Huot and Arthur
                 Mitrano and Shane Story",
  title =        "Optimizing Matrix Multiplication on {Intel Xeon Phi TH
                 x200} Architecture",
  crossref =     "Burgess:2017:ISC",
  pages =        "144--145",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.19",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Matrix multiplication is ubiquitous in scientific
                 computing. From computational science to machine
                 learning, a large and diverse set of applications rely
                 on the performance of general matrix-matrix
                 multiplication (GEMM) subroutines. The Intel Math
                 Kernel Library(R) provides highly optimized GEMM
                 subroutines that take full advantage of the available
                 parallelism and vectorization in both Intel Xeon and
                 Intel Xeon Phi(TM) processors. In this paper we discuss
                 the optimization of GEMM subroutines for the Intel Xeon
                 PhiTM x200 (code-named Knights Landing).",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithms; Bandwidth; blas; computational science;
                 Computer architecture; general matrix-matrix
                 multiplication; Intel Math Kernel Library; intel xeon
                 phi; Intel Xeon Phi x200 architecture; Kernel; Knights
                 Landing; machine learning; matrix multiplication;
                 microprocessor chips; Optimization; performance
                 optimization; Prefetching; processors; scientific
                 computing",
}


bibtype: misc
filename: fparith.bib
label: Gustafson:2017:BFPa
author: John Gustafson
title: Beyond Floating Point: Next Generation Computer Arithmetic
pages: 144--145
month: feb
monthnumber: 2
year: 2017
bibdate: Mon Feb 06 06:47:46 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.02.06 06:47:46 ???
keywords: unum floating-point format
acknowledgement: ack-nhfb
howpublished: Web video
rawauthor: John Gustafson
rawtitle: Beyond Floating Point: Next Generation Computer Arithmetic
URL:
http://insidehpc.com/2017/02/john-gustafson-presents-beyond-floating-point-next-generation-computer-arithmetic

entry:
@Misc{Gustafson:2017:BFPa,
  author =       "John Gustafson",
  title =        "Beyond Floating Point: Next Generation Computer
                 Arithmetic",
  howpublished = "Web video",
  month =        feb,
  year =         "2017",
  bibdate =      "Mon Feb 06 06:47:46 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://insidehpc.com/2017/02/john-gustafson-presents-beyond-floating-point-next-generation-computer-arithmetic",
  acknowledgement = ack-nhfb,
  keywords =     "unum floating-point format",
}


bibtype: techreport
filename: fparith.bib
label: Gustafson:2017:BFPb
author: John Gustafson and Isaac Yonemoto
title: Beating Floating Point at its Own Game: Posit Arithmetic
type: Report
pages: 16
day: 12
month: jun
monthnumber: 6
year: 2017
bibdate: Mon Sep 26 13:38:16 2022
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2022.09.26 13:38:16 ???
URL: http://www.johngustafson.net/pdfs/BeatingFloatingPoint.pdf
acknowledgement: ack-nhfb
rawauthor: John Gustafson and Isaac Yonemoto
rawtitle: Beating Floating Point at its Own Game: Posit Arithmetic
institution:
A*STAR Computational Resources Centre and National University of Singapore (joint appointment) [JG], Singapore Interplanetary Robot and Electric Brain Company, Saratoga, California USA [IY]

abstract:
A new data type called a posit is designed as a direct drop-in replacement for IEEE Standard 754 floating-point numbers (floats). Unlike earlier forms of universal number (unum) arithmetic, posits do not require interval arithmetic or variable size operands; like floats, they round if an answer is inexact. However, they provide compelling advantages over floats, including larger dynamic range, higher accuracy, better closure, bitwise identical results across systems, simpler hardware, and simpler exception handling. Posits never overflow to infinity or underflow to zero, and ``Not-a-Number'' (NaN) indicates an action instead of a bit pattern. A posit processing unit takes less circuitry than an IEEE float FPU. With lower power use and smaller silicon footprint, the posit operations per second (POPS) supported by a chip can be significantly higher than the FLOPS using similar hardware resources. GPU accelerators and Deep Learning processors, in particular, can do more per watt and per dollar with posits, yet deliver superior answer quality.par A comprehensive series of benchmarks compares floats and posits for decimals of accuracy produced for a set precision. Low precision posits provide a better solution than ``approximate computing'' methods that try to tolerate decreased answer quality. High precision posits provide more correct decimals than floats of the same size; in some cases, a 32-bit posit may safely replace a 64-bit float. In other words, posits beat floats at their own game.

keywords:
computer arithmetic; energy-efficient computing; floating point; linear algebra; LINPACK; neural networks; posits; unum computing; valid arithmetic

rawabstract:
A new data type called a posit is designed as a direct drop-in replacement for IEEE Standard 754 floating-point numbers (floats). Unlike earlier forms of universal number (unum) arithmetic, posits do not require interval arithmetic or variable size operands; like floats, they round if an answer is inexact. However, they provide compelling advantages over floats, including larger dynamic range, higher accuracy, better closure, bitwise identical results across systems, simpler hardware, and simpler exception handling. Posits never overflow to infinity or underflow to zero, and ``Not-a-Number'' (NaN) indicates an action instead of a bit pattern. A posit processing unit takes less circuitry than an IEEE float FPU. With lower power use and smaller silicon footprint, the posit operations per second (POPS) supported by a chip can be significantly higher than the FLOPS using similar hardware resources. GPU accelerators and Deep Learning processors, in particular, can do more per watt and per dollar with posits, yet deliver superior answer quality.\par A comprehensive series of benchmarks compares floats and posits for decimals of accuracy produced for a set precision. Low precision posits provide a better solution than ``approximate computing'' methods that try to tolerate decreased answer quality. High precision posits provide more correct decimals than floats of the same size; in some cases, a 32-bit posit may safely replace a 64-bit float. In other words, posits beat floats at their own game.

entry:
@TechReport{Gustafson:2017:BFPb,
  author =       "John Gustafson and Isaac Yonemoto",
  title =        "Beating Floating Point at its Own Game: Posit
                 Arithmetic",
  type =         "Report",
  institution =  "A*STAR Computational Resources Centre and National
                 University of Singapore (joint appointment) [JG],
                 Singapore Interplanetary Robot and Electric Brain
                 Company, Saratoga, California USA [IY]",
  pages =        "16",
  day =          "12",
  month =        jun,
  year =         "2017",
  bibdate =      "Mon Sep 26 13:38:16 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.johngustafson.net/pdfs/BeatingFloatingPoint.pdf",
  abstract =     "A new data type called a posit is designed as a direct
                 drop-in replacement for IEEE Standard 754
                 floating-point numbers (floats). Unlike earlier forms
                 of universal number (unum) arithmetic, posits do not
                 require interval arithmetic or variable size operands;
                 like floats, they round if an answer is inexact.
                 However, they provide compelling advantages over
                 floats, including larger dynamic range, higher
                 accuracy, better closure, bitwise identical results
                 across systems, simpler hardware, and simpler exception
                 handling. Posits never overflow to infinity or
                 underflow to zero, and ``Not-a-Number'' (NaN) indicates
                 an action instead of a bit pattern. A posit processing
                 unit takes less circuitry than an IEEE float FPU. With
                 lower power use and smaller silicon footprint, the
                 posit operations per second (POPS) supported by a chip
                 can be significantly higher than the FLOPS using
                 similar hardware resources. GPU accelerators and Deep
                 Learning processors, in particular, can do more per
                 watt and per dollar with posits, yet deliver superior
                 answer quality.\par

                 A comprehensive series of benchmarks compares floats
                 and posits for decimals of accuracy produced for a set
                 precision. Low precision posits provide a better
                 solution than ``approximate computing'' methods that
                 try to tolerate decreased answer quality. High
                 precision posits provide more correct decimals than
                 floats of the same size; in some cases, a 32-bit posit
                 may safely replace a 64-bit float. In other words,
                 posits beat floats at their own game.",
  acknowledgement = ack-nhfb,
  keywords =     "computer arithmetic; energy-efficient computing;
                 floating point; linear algebra; LINPACK; neural
                 networks; posits; unum computing; valid arithmetic",
}


bibtype: article
filename: fparith.bib
label: Gustafson:2017:BFPc
author: John L. Gustafson and Isaac Yonemoto
title: Beating Floating Point at Its Own Game: Posit Arithmetic
journal: j-SUPERFRI
volume: 4
number: 2
pages: 71--86
year: 2017
DOI: https://doi.org/10.14529/jsfi170206
ISSN: 2313-8734 (print), 2409-6008 (electronic) OR 23138734 (print), 24096008 (electronic)
ISSNL: 2313-8734 OR 23138734
bibdate: Sun Dec 10 14:34:44 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.10 14:34:44 ???
URL: https://superfri.org/index.php/superfri/article/view/137/232
fjournal: Supercomputing Frontiers and Innovations: an International Journal
acknowledgement: ack-nhfb
journalURL: https://superfri.org/index.php/superfri/
rawauthor: John L. Gustafson and Isaac Yonemoto
rawtitle: Beating Floating Point at Its Own Game: Posit Arithmetic
remark:
Published at South Ural State University, Chelyabinsk, Russia, Russia. Not in US Library of Congress or CASSI.

entry:
@Article{Gustafson:2017:BFPc,
  author =       "John L. Gustafson and Isaac Yonemoto",
  title =        "Beating Floating Point at Its Own Game: Posit
                 Arithmetic",
  journal =      j-SUPERFRI,
  volume =       "4",
  number =       "2",
  pages =        "71--86",
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.14529/jsfi170206",
  ISSN =         "2313-8734 (print), 2409-6008 (electronic)",
  ISSN-L =       "2313-8734",
  bibdate =      "Sun Dec 10 14:34:44 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://superfri.org/index.php/superfri/article/view/137/232",
  acknowledgement = ack-nhfb,
  fjournal =     "Supercomputing Frontiers and Innovations: an
                 International Journal",
  journal-doi =  "https://doi.org/10.14529/jsfi",
  journal-URL =  "https://superfri.org/index.php/superfri/",
  remark =       "Published at South Ural State University, Chelyabinsk,
                 Russia, Russia. Not in US Library of Congress or
                 CASSI.",
  xx-journal-url = "https://superfri.org/index.php/superfri/issue/archive",
}


bibtype: misc
filename: fparith.bib
label: Gustafson:2017:PA
author: John L. Gustafson
title: Posit Arithmetic
pages: 1--137
day: 10
month: oct
monthnumber: 10
year: 2017
bibdate: Tue Jul 09 10:34:12 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.07.09 10:34:12 ???
URL: https://posithub.org/docs/Posits4.pdf
acknowledgement: ack-nhfb
howpublished: Web PDF file.
rawauthor: John L. Gustafson
rawtitle: Posit Arithmetic
entry:
@Misc{Gustafson:2017:PA,
  author =       "John L. Gustafson",
  title =        "Posit Arithmetic",
  howpublished = "Web PDF file.",
  pages =        "1--137",
  day =          "10",
  month =        oct,
  year =         "2017",
  bibdate =      "Tue Jul 09 10:34:12 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://posithub.org/docs/Posits4.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Gustafsson:2017:ANS
author: Oscar Gustafsson and Erik Bertilsson and Johannes Klasson and Carl Ingemarsson
title: Approximate Neumann Series or Exact Matrix Inversion for Massive MIMO?
crossref: Burgess:2017:ISC
pages: 62--63
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.11
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Oscar Gustafsson and Erik Bertilsson and Johannes Klasson and Carl Ingemarsson
rawtitle: Approximate {Neumann} Series or Exact Matrix Inversion for Massive {MIMO}?
abstract:
Approximate matrix inversion based on Neumann series has seen a recent increased interest motivated by massive MIMO systems. There, the matrices are in many cases diagonally dominant, and, hence, a reasonable approximation can be obtained within a few iterations of a Neumann series. In this work, we clarify that the complexity of exact methods are about the same as when three terms are used for the Neumann series, so in this case, the complexity is not lower as often claimed. The second common argument for Neumann series approximation, higher parallelism, is indeed correct. However, in most current practical use cases, such a high degree of parallelism is not required to obtain a low latency realization. Hence, we conclude that a careful evaluation, based on accuracy and latency requirements must be performed and that exact matrix inversion is in fact viable in many more cases than the current literature claims.

keywords:
approximate matrix inversion; approximate Neumann series; approximation theory; Clocks; Complexity theory; Computer architecture; exact matrix inversion; iterative methods; Large-scale MIMO; Latency; Massive MIMO; massive MIMO systems; matrix algebra; Matrix inversion; MIMO; MIMO communication; Neumann series; Pipeline processing; Symmetric matrices

rawabstract:
Approximate matrix inversion based on Neumann series has seen a recent increased interest motivated by massive MIMO systems. There, the matrices are in many cases diagonally dominant, and, hence, a reasonable approximation can be obtained within a few iterations of a Neumann series. In this work, we clarify that the complexity of exact methods are about the same as when three terms are used for the Neumann series, so in this case, the complexity is not lower as often claimed. The second common argument for Neumann series approximation, higher parallelism, is indeed correct. However, in most current practical use cases, such a high degree of parallelism is not required to obtain a low latency realization. Hence, we conclude that a careful evaluation, based on accuracy and latency requirements must be performed and that exact matrix inversion is in fact viable in many more cases than the current literature claims.

entry:
@InProceedings{Gustafsson:2017:ANS,
  author =       "Oscar Gustafsson and Erik Bertilsson and Johannes
                 Klasson and Carl Ingemarsson",
  title =        "Approximate {Neumann} Series or Exact Matrix Inversion
                 for Massive {MIMO}?",
  crossref =     "Burgess:2017:ISC",
  pages =        "62--63",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.11",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Approximate matrix inversion based on Neumann series
                 has seen a recent increased interest motivated by
                 massive MIMO systems. There, the matrices are in many
                 cases diagonally dominant, and, hence, a reasonable
                 approximation can be obtained within a few iterations
                 of a Neumann series. In this work, we clarify that the
                 complexity of exact methods are about the same as when
                 three terms are used for the Neumann series, so in this
                 case, the complexity is not lower as often claimed. The
                 second common argument for Neumann series
                 approximation, higher parallelism, is indeed correct.
                 However, in most current practical use cases, such a
                 high degree of parallelism is not required to obtain a
                 low latency realization. Hence, we conclude that a
                 careful evaluation, based on accuracy and latency
                 requirements must be performed and that exact matrix
                 inversion is in fact viable in many more cases than the
                 current literature claims.",
  acknowledgement = ack-nhfb,
  keywords =     "approximate matrix inversion; approximate Neumann
                 series; approximation theory; Clocks; Complexity
                 theory; Computer architecture; exact matrix inversion;
                 iterative methods; Large-scale MIMO; Latency; Massive
                 MIMO; massive MIMO systems; matrix algebra; Matrix
                 inversion; MIMO; MIMO communication; Neumann series;
                 Pipeline processing; Symmetric matrices",
}


bibtype: inproceedings
filename: fparith.bib
label: Gustafsson:2017:LBF
author: Oscar Gustafsson
title: On Lifting-Based Fixed-Point Complex Multiplications and Rotations
crossref: Burgess:2017:ISC
pages: 43--49
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.10
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Oscar Gustafsson
rawtitle: On Lifting-Based Fixed-Point Complex Multiplications and Rotations
abstract:
Lifting-based complex multiplications and rotations are integer invertible, i.e., an integer input value is mapped to the same integer output value when rotating forward and backward. This is an important aspect for lossless transform based source coding, but since the structure only require three real-valued multiplications and three real-valued additions it is also a potentially attractive way to perform complex multiplications when the coefficient has unity magnitude. In this work, we consider two aspects of these structures. First, we show that both the magnitude and angular error is dependent on the angle of input value and derive both exact and approximated expressions for these. Second, we discuss how to design such structures without the typical separation into three subsequent matrix multiplications. It is shown that the proposed design method allows many more values which are integer invertible, but can not be separated into three subsequent matrix multiplications with fixed-point values. The results show good correspondence between the error approximations and the actual error as well as a significantly increased design space.

keywords:
complex multiplication; complex rotation; Design methodology; digital arithmetic; Digital arithmetic; Discrete cosine transforms; Electrical engineering; error analysis; error approximations; fixed-point; lifting; lifting-based fixed-point complex multiplications; lifting-based fixed-point complex rotations; logic design; lossless transform based source coding; Matrix decomposition; real-valued additions; real-valued multiplications; rotation; source coding; Source coding; transform coding

rawabstract:
Lifting-based complex multiplications and rotations are integer invertible, i.e., an integer input value is mapped to the same integer output value when rotating forward and backward. This is an important aspect for lossless transform based source coding, but since the structure only require three real-valued multiplications and three real-valued additions it is also a potentially attractive way to perform complex multiplications when the coefficient has unity magnitude. In this work, we consider two aspects of these structures. First, we show that both the magnitude and angular error is dependent on the angle of input value and derive both exact and approximated expressions for these. Second, we discuss how to design such structures without the typical separation into three subsequent matrix multiplications. It is shown that the proposed design method allows many more values which are integer invertible, but can not be separated into three subsequent matrix multiplications with fixed-point values. The results show good correspondence between the error approximations and the actual error as well as a significantly increased design space.

entry:
@InProceedings{Gustafsson:2017:LBF,
  author =       "Oscar Gustafsson",
  title =        "On Lifting-Based Fixed-Point Complex Multiplications
                 and Rotations",
  crossref =     "Burgess:2017:ISC",
  pages =        "43--49",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.10",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Lifting-based complex multiplications and rotations
                 are integer invertible, i.e., an integer input value is
                 mapped to the same integer output value when rotating
                 forward and backward. This is an important aspect for
                 lossless transform based source coding, but since the
                 structure only require three real-valued
                 multiplications and three real-valued additions it is
                 also a potentially attractive way to perform complex
                 multiplications when the coefficient has unity
                 magnitude. In this work, we consider two aspects of
                 these structures. First, we show that both the
                 magnitude and angular error is dependent on the angle
                 of input value and derive both exact and approximated
                 expressions for these. Second, we discuss how to design
                 such structures without the typical separation into
                 three subsequent matrix multiplications. It is shown
                 that the proposed design method allows many more values
                 which are integer invertible, but can not be separated
                 into three subsequent matrix multiplications with
                 fixed-point values. The results show good
                 correspondence between the error approximations and the
                 actual error as well as a significantly increased
                 design space.",
  acknowledgement = ack-nhfb,
  keywords =     "complex multiplication; complex rotation; Design
                 methodology; digital arithmetic; Digital arithmetic;
                 Discrete cosine transforms; Electrical engineering;
                 error analysis; error approximations; fixed-point;
                 lifting; lifting-based fixed-point complex
                 multiplications; lifting-based fixed-point complex
                 rotations; logic design; lossless transform based
                 source coding; Matrix decomposition; real-valued
                 additions; real-valued multiplications; rotation;
                 source coding; Source coding; transform coding",
}


bibtype: inproceedings
filename: fparith.bib
label: Haidar:2017:IHP
author: Azzam Haidar and Panruo Wu and Stanimire Tomov and Jack Dongarra
title: Investigating half precision arithmetic to accelerate dense linear system solvers
publisher: pub-ACM
address: pub-ACM:adr
pages: 43--49
year: 2017
DOI: https://doi.org/10.1145/3148226.3148237
ISBN: 1-4503-5125-5 (hardcover) OR 1450351255 (hardcover)
ISBN13: 978-1-4503-5125-6 (hardcover) OR 9781450351256 (hardcover)
bibdate: Thu Nov 7 16:51:39 2019
bibtimestamp: 2019.11.07 16:51:39 ???
acknowledgement: ack-nhfb
rawauthor: Azzam Haidar and Panruo Wu and Stanimire Tomov and Jack Dongarra
rawtitle: Investigating half precision arithmetic to accelerate dense linear system solvers
ORCID: Dongarra, Jack/0000-0003-3247-1782
booktitle:
Proceedings of the 8th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems --- ScalA'17

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawbooktitle:
Proceedings of the {8th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems --- ScalA'17}

entry:
@InProceedings{Haidar:2017:IHP,
  author =       "Azzam Haidar and Panruo Wu and Stanimire Tomov and
                 Jack Dongarra",
  booktitle =    "Proceedings of the {8th Workshop on Latest Advances in
                 Scalable Algorithms for Large-Scale Systems ---
                 ScalA'17}",
  title =        "Investigating half precision arithmetic to accelerate
                 dense linear system solvers",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  year =         "2017",
  DOI =          "https://doi.org/10.1145/3148226.3148237",
  ISBN =         "1-4503-5125-5 (hardcover)",
  ISBN-13 =      "978-1-4503-5125-6 (hardcover)",
  LCCN =         "????",
  bibdate =      "Thu Nov 7 16:51:39 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ORCID-numbers = "Dongarra, Jack/0000-0003-3247-1782",
}


bibtype: article
filename: fparith.bib
label: Hiasat:2017:ERS
author: Ahmad Hiasat
title: Efficient RNS Scalers for the Extended Three-Moduli Set $ (2^n - 1, 2^n + p, 2^n + 1) $
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 7
pages: 1253--1260
month: jul
monthnumber: 7
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2652474
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jun 8 10:22:00 MDT 2017
bibtimestamp: 2017.06.08 10:22:00 MDT
URL: https://www.computer.org/csdl/trans/tc/2017/07/07815319-abs.html
fjournal: IEEE Transactions on Computers
keywords: Residue Number System (RNS)
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Ahmad Hiasat
rawtitle: Efficient {RNS} Scalers for the Extended Three-Moduli Set $ (2^n - 1, 2^{n + p}, 2^n + 1) $
entry:
@Article{Hiasat:2017:ERS,
  author =       "Ahmad Hiasat",
  title =        "Efficient {RNS} Scalers for the Extended Three-Moduli
                 Set $ (2^n - 1, 2^{n + p}, 2^n + 1) $",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "7",
  pages =        "1253--1260",
  month =        jul,
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2652474",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jun 8 10:22:00 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://www.computer.org/csdl/trans/tc/2017/07/07815319-abs.html",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Residue Number System (RNS)",
}


bibtype: book
filename: fparith.bib
label: Higham:2017:MG
author: Desmond J. Higham and Nicholas J. Higham
title: MATLAB guide
publisher: pub-SIAM
address: pub-SIAM:adr
pages: xxvi + 476
year: 2017
ISBN: 1-61197-465-8 OR 1611974658
ISBN13: 978-1-61197-465-2 OR 9781611974652
MRclass: 65-00 (00A20)
MRnumber: 3601107
bibdate: Sat Aug 26 17:40:10 2017
bibtimestamp: 2017.08.26 17:40:10 ???
remark: Third edition of cite Higham:2000:MG,Higham:2005:MG.
acknowledgement: ack-nhfb
rawauthor: Desmond J. Higham and Nicholas J. Higham
rawtitle: {MATLAB} guide
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/numana2010.bib

abstract:
MATLAB is an interactive system for numerical computation that is widely used for teaching and research in industry and academia. It provides a modern programming language and problem solving environment, with powerful data structures, customizable graphics, and easy-to-use editing and debugging tools. This third edition of MATLAB Guide completely revises and updates the best-selling second edition and is more than 25 percent longer. The book remains a lively, concise introduction to the most popular and important features of MATLAB and the Symbolic Math Toolbox. Key features are a tutorial in Chapter 1 that gives a hands-on overview of MATLAB, a thorough treatment of MATLAB mathematics, including the linear algebra and numerical analysis functions and the differential equation solvers, and a web page that provides a link to example program files, updates, and links to MATLAB resources. The new edition contains color figures throughout, includes pithy discussions of related topics in new `Asides' boxes that augment the text, has new chapters on the Parallel Computing Toolbox, object-oriented programming, graphs, and large data sets, covers important new MATLAB data types such as categorical arrays, string arrays, tall arrays, tables, and timetables, contains more on MATLAB workflow, including the Live Editor and unit tests, and fully reflects major updates to the MATLAB graphics system.

subject:
MATLAB (logiciel).; Analyse numerique; Logiciels.; Numerical analysis; Data processing; Data processing.

TOC:
1: A Brief Tutorial 2: Basics 3: Distinctive Features of MATLAB 4: Arithmetic 5: Matrices 6: Operators and Flow Control 7: Program Files 8: Graphics 9: Linear Algebra 10: More on Functions 11: Numerical Methods: Part I 12: Numerical Methods: Part II 13: Input and Output 14: Troubleshooting 15: Sparse Matrices 16: More on Coding 17: Advanced Graphics 18: Other Data Types and Multidimensional Arrays 19: Object-Oriented Programming 20: The Symbolic Math Toolbox 21: Graphs 22: Large Data Sets 23: Optimizing Codes 24: Tricks and Tips 25: The Parallel Computing Toolbox 26: Case Studies

rawabstract:
MATLAB is an interactive system for numerical computation that is widely used for teaching and research in industry and academia. It provides a modern programming language and problem solving environment, with powerful data structures, customizable graphics, and easy-to-use editing and debugging tools. This third edition of MATLAB Guide completely revises and updates the best-selling second edition and is more than 25 percent longer. The book remains a lively, concise introduction to the most popular and important features of MATLAB and the Symbolic Math Toolbox. Key features are a tutorial in Chapter 1 that gives a hands-on overview of MATLAB, a thorough treatment of MATLAB mathematics, including the linear algebra and numerical analysis functions and the differential equation solvers, and a web page that provides a link to example program files, updates, and links to MATLAB resources. The new edition contains color figures throughout, includes pithy discussions of related topics in new `Asides' boxes that augment the text, has new chapters on the Parallel Computing Toolbox, object-oriented programming, graphs, and large data sets, covers important new MATLAB data types such as categorical arrays, string arrays, tall arrays, tables, and timetables, contains more on MATLAB workflow, including the Live Editor and unit tests, and fully reflects major updates to the MATLAB graphics system.

rawTOC:
1: A Brief Tutorial \\ 2: Basics \\ 3: Distinctive Features of MATLAB \\ 4: Arithmetic \\ 5: Matrices \\ 6: Operators and Flow Control \\ 7: Program Files \\ 8: Graphics \\ 9: Linear Algebra \\ 10: More on Functions \\ 11: Numerical Methods: Part I \\ 12: Numerical Methods: Part II \\ 13: Input and Output \\ 14: Troubleshooting \\ 15: Sparse Matrices \\ 16: More on Coding \\ 17: Advanced Graphics \\ 18: Other Data Types and Multidimensional Arrays \\ 19: Object-Oriented Programming \\ 20: The Symbolic Math Toolbox \\ 21: Graphs \\ 22: Large Data Sets \\ 23: Optimizing Codes \\ 24: Tricks and Tips \\ 25: The Parallel Computing Toolbox \\ 26: Case Studies

entry:
@Book{Higham:2017:MG,
  author =       "Desmond J. Higham and Nicholas J. Higham",
  title =        "{MATLAB} guide",
  publisher =    pub-SIAM,
  address =      pub-SIAM:adr,
  pages =        "xxvi + 476",
  year =         "2017",
  ISBN =         "1-61197-465-8",
  ISBN-13 =      "978-1-61197-465-2",
  MRclass =      "65-00 (00A20)",
  MRnumber =     "3601107",
  bibdate =      "Sat Aug 26 17:40:10 2017",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/numana2010.bib",
  abstract =     "MATLAB is an interactive system for numerical
                 computation that is widely used for teaching and
                 research in industry and academia. It provides a modern
                 programming language and problem solving environment,
                 with powerful data structures, customizable graphics,
                 and easy-to-use editing and debugging tools. This third
                 edition of MATLAB Guide completely revises and updates
                 the best-selling second edition and is more than 25
                 percent longer. The book remains a lively, concise
                 introduction to the most popular and important features
                 of MATLAB and the Symbolic Math Toolbox. Key features
                 are a tutorial in Chapter 1 that gives a hands-on
                 overview of MATLAB, a thorough treatment of MATLAB
                 mathematics, including the linear algebra and numerical
                 analysis functions and the differential equation
                 solvers, and a web page that provides a link to example
                 program files, updates, and links to MATLAB resources.
                 The new edition contains color figures throughout,
                 includes pithy discussions of related topics in new
                 `Asides' boxes that augment the text, has new chapters
                 on the Parallel Computing Toolbox, object-oriented
                 programming, graphs, and large data sets, covers
                 important new MATLAB data types such as categorical
                 arrays, string arrays, tall arrays, tables, and
                 timetables, contains more on MATLAB workflow, including
                 the Live Editor and unit tests, and fully reflects
                 major updates to the MATLAB graphics system.",
  acknowledgement = ack-nhfb,
  remark =       "Third edition of
                 \cite{Higham:2000:MG,Higham:2005:MG}.",
  subject =      "MATLAB (logiciel).; Analyse num{\'e}rique; Logiciels.;
                 Numerical analysis; Data processing; Data processing.",
  tableofcontents = "1: A Brief Tutorial \\
                 2: Basics \\
                 3: Distinctive Features of MATLAB \\
                 4: Arithmetic \\
                 5: Matrices \\
                 6: Operators and Flow Control \\
                 7: Program Files \\
                 8: Graphics \\
                 9: Linear Algebra \\
                 10: More on Functions \\
                 11: Numerical Methods: Part I \\
                 12: Numerical Methods: Part II \\
                 13: Input and Output \\
                 14: Troubleshooting \\
                 15: Sparse Matrices \\
                 16: More on Coding \\
                 17: Advanced Graphics \\
                 18: Other Data Types and Multidimensional Arrays \\
                 19: Object-Oriented Programming \\
                 20: The Symbolic Math Toolbox \\
                 21: Graphs \\
                 22: Large Data Sets \\
                 23: Optimizing Codes \\
                 24: Tricks and Tips \\
                 25: The Parallel Computing Toolbox \\
                 26: Case Studies",
}


bibtype: article
filename: fparith.bib
label: Higham:2017:MW
author: Nicholas J. Higham
title: A multiprecision world
journal: j-SIAM-NEWS
volume: 50
number: 8
pages: ??--??
day: 2
month: oct
monthnumber: 10
year: 2017
ISSN: 0036-1437 OR 00361437
bibdate: Wed Aug 07 15:18:43 2024
bibtimestamp: 2024.08.07 15:18:43 ???
URL: https://sinews.siam.org/Details-Page/a-multiprecision-world
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: https://sinews.siam.org/
rawauthor: Nicholas J. Higham
rawtitle: A multiprecision world
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Higham:2017:MW,
  author =       "Nicholas J. Higham",
  title =        "A multiprecision world",
  journal =      j-SIAM-NEWS,
  volume =       "50",
  number =       "8",
  pages =        "??--??",
  day =          "2",
  month =        oct,
  year =         "2017",
  ISSN =         "0036-1437",
  bibdate =      "Wed Aug 07 15:18:43 2024",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/a-multiprecision-world",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "https://sinews.siam.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Higham:2017:RMA
author: Nicholas John Higham
title: The Rise of Multiprecision Arithmetic
crossref: Burgess:2017:ISC
pages: 1--1
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.24
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Nicholas John Higham
rawtitle: The Rise of Multiprecision Arithmetic
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
There is a growing demand for and availability of multiprecision arithmetic: floating point arithmetic supporting multiple, possibly arbitrary, precisions. For an increasing body of applications, including in supernova simulations, electromagnetic scattering theory, and computational number theory, double precision arithmetic is insufficient to provide results of the required accuracy. On the other hand, for climate modelling and deep learning half precision (about four significant decimal digits) has been shown to be sufficient in some studies. We discuss a number of topics involving multiprecision arithmetic, including: The need for, availability of, and ways to exploit, higher precision arithmetic (e.g., quadruple precision arithmetic). How to derive linear algebra algorithms that will run in any precision, as opposed to be being optimized (as some key algorithms are) for double precision. For solving linear systems with the use of iterative refinement, the benefits of suitably combining three different precisions of arithmetic (say, half, single, and double). How a new form of preconditioned iterative refinement can be used to solve very ill conditioned sparse linear systems to high accuracy.

keywords:
climate modelling; Computational modeling; deep learning half precision; Digital arithmetic; double precision arithmetic; Electromagnetic scattering; floating point arithmetic; Floating-point arithmetic; iterative methods; iterative refinement; linear algebra; linear algebra algorithms; linear systems; Linear systems; Mathematical model; multiprecision arithmetic; sparse linear systems

rawabstract:
There is a growing demand for and availability of multiprecision arithmetic: floating point arithmetic supporting multiple, possibly arbitrary, precisions. For an increasing body of applications, including in supernova simulations, electromagnetic scattering theory, and computational number theory, double precision arithmetic is insufficient to provide results of the required accuracy. On the other hand, for climate modelling and deep learning half precision (about four significant decimal digits) has been shown to be sufficient in some studies. We discuss a number of topics involving multiprecision arithmetic, including: The need for, availability of, and ways to exploit, higher precision arithmetic (e.g., quadruple precision arithmetic). How to derive linear algebra algorithms that will run in any precision, as opposed to be being optimized (as some key algorithms are) for double precision. For solving linear systems with the use of iterative refinement, the benefits of suitably combining three different precisions of arithmetic (say, half, single, and double). How a new form of preconditioned iterative refinement can be used to solve very ill conditioned sparse linear systems to high accuracy.

entry:
@InProceedings{Higham:2017:RMA,
  author =       "Nicholas John Higham",
  title =        "The Rise of Multiprecision Arithmetic",
  crossref =     "Burgess:2017:ISC",
  pages =        "1--1",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.24",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "There is a growing demand for and availability of
                 multiprecision arithmetic: floating point arithmetic
                 supporting multiple, possibly arbitrary, precisions.
                 For an increasing body of applications, including in
                 supernova simulations, electromagnetic scattering
                 theory, and computational number theory, double
                 precision arithmetic is insufficient to provide results
                 of the required accuracy. On the other hand, for
                 climate modelling and deep learning half precision
                 (about four significant decimal digits) has been shown
                 to be sufficient in some studies. We discuss a number
                 of topics involving multiprecision arithmetic,
                 including: The need for, availability of, and ways to
                 exploit, higher precision arithmetic (e.g., quadruple
                 precision arithmetic). How to derive linear algebra
                 algorithms that will run in any precision, as opposed
                 to be being optimized (as some key algorithms are) for
                 double precision. For solving linear systems with the
                 use of iterative refinement, the benefits of suitably
                 combining three different precisions of arithmetic
                 (say, half, single, and double). How a new form of
                 preconditioned iterative refinement can be used to
                 solve very ill conditioned sparse linear systems to
                 high accuracy.",
  acknowledgement = ack-nhfb,
  keywords =     "climate modelling; Computational modeling; deep
                 learning half precision; Digital arithmetic; double
                 precision arithmetic; Electromagnetic scattering;
                 floating point arithmetic; Floating-point arithmetic;
                 iterative methods; iterative refinement; linear
                 algebra; linear algebra algorithms; linear systems;
                 Linear systems; Mathematical model; multiprecision
                 arithmetic; sparse linear systems",
}


bibtype: article
filename: fparith.bib
label: Hormigo:2017:ISI
title: Introduction to the Special Issue on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 1991--1993
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2761278
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Introduction to the Special Issue on Computer Arithmetic
author:
Javier Hormigo and Jean-Michel Muller and Stuart Oberman and Nathalie Revol and Arnaud Tisserand and Julio Villalba-Moreno

rawauthor:
Javier Hormigo and Jean-Michel Muller and Stuart Oberman and Nathalie Revol and Arnaud Tisserand and Julio Villalba-Moreno

entry:
@Article{Hormigo:2017:ISI,
  author =       "Javier Hormigo and Jean-Michel Muller and Stuart
                 Oberman and Nathalie Revol and Arnaud Tisserand and
                 Julio Villalba-Moreno",
  title =        "Introduction to the Special Issue on Computer
                 Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "1991--1993",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2761278",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Hou:2017:TGF
author: Junjie Hou and Yongxin Zhu and Yulan Shen and Mengjun Li and Han Wu and Han Song
title: Tackling Gaps in Floating-Point Arithmetic: Unum Arithmetic Implementation on FPGA
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 615--616
year: 2017
DOI: https://doi.org/10.1109/HPCC-SmartCity-DSS.2017.82
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Junjie Hou and Yongxin Zhu and Yulan Shen and Mengjun Li and Han Wu and Han Song
rawtitle: Tackling Gaps in Floating-Point Arithmetic: Unum Arithmetic Implementation on {FPGA}
booktitle:
2017 IEEE 19th International Conference on High Performance Computing and Communications; IEEE 15th International Conference on Smart City; IEEE 3rd International Conference on Data Science and Systems (HPCC/SmartCity/DSS)

rawbooktitle:
{2017 IEEE 19th International Conference on High Performance Computing and Communications; IEEE 15th International Conference on Smart City; IEEE 3rd International Conference on Data Science and Systems (HPCC/SmartCity/DSS)}

entry:
@InProceedings{Hou:2017:TGF,
  author =       "Junjie Hou and Yongxin Zhu and Yulan Shen and Mengjun
                 Li and Han Wu and Han Song",
  booktitle =    "{2017 IEEE 19th International Conference on High
                 Performance Computing and Communications; IEEE 15th
                 International Conference on Smart City; IEEE 3rd
                 International Conference on Data Science and Systems
                 (HPCC/SmartCity/DSS)}",
  title =        "Tackling Gaps in Floating-Point Arithmetic: Unum
                 Arithmetic Implementation on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "615--616",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/HPCC-SmartCity-DSS.2017.82",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ishii:2017:FMA
author: Masahiro Ishii and Jeremie Detrey and Pierrick Gaudry and Atsuo Inomata and Kazutoshi Fujikawa
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2019--2030
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2704082
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7927487/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
title:
Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM

rawauthor:
Masahiro Ishii and J{\'e}r{\'e}mie Detrey and Pierrick Gaudry and Atsuo Inomata and Kazutoshi Fujikawa

rawtitle:
Fast Modular Arithmetic on the {Kalray MPPA-256} Processor for an Energy-Efficient Implementation of {ECM}

entry:
@Article{Ishii:2017:FMA,
  author =       "Masahiro Ishii and J{\'e}r{\'e}mie Detrey and Pierrick
                 Gaudry and Atsuo Inomata and Kazutoshi Fujikawa",
  title =        "Fast Modular Arithmetic on the {Kalray MPPA-256}
                 Processor for an Energy-Efficient Implementation of
                 {ECM}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2019--2030",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2704082",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7927487/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Istoan:2017:FFP
author: Matei Istoan and Bogdan Pasca
title: Flexible Fixed-Point Function Generation for FPGAs
crossref: Burgess:2017:ISC
pages: 123--130
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.31
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Matei Istoan and Bogdan Pasca
rawtitle: Flexible Fixed-Point Function Generation for {FPGAs}
abstract:
Efficient fixed-point function implementation is critical in many FPGA application domains including convolutional neural networks, computer vision, and communication systems. In this work we focus on functions of the form $ x^p $, with $ p in - 1, - 1 / 2, 1 / 2 $ as part of a function generator targeting FPGAs. The generator implements architectures based on new but also existing algorithms. In this work we present three distinct methods implemented in this generator that outperform state-of-the-art implementations for certain configurations. Traditionally, fixed-point function implementation requires a normalization stage, compute and denormalization (reconstruction) of the result. The first proposed method implements the function holistically, thus saving the logic and latency required during the normalize and reconstruct stages. The second proposed method is based on a novel second order Taylor implementation. The third method is based on the cubic convergence of Halley's method, which is novel in this context. The proposed methods are compared and contrasted against state-of-the art implementations in the context of FPGA targets.

keywords:
arithmetic; communication systems; computer vision; convolutional neural networks; cubic convergence; Digital signal processing; Field programmable gate arrays; field programmable gate arrays; fixed point arithmetic; fixed-point; flexible fixed-point function generation; FPGA; FPGAs; generator; Generators; Halley method; Kernel; Memory management; reciprocal; reciprocal sqrt; second order Taylor implementation; Signal generators; sqrt

rawabstract:
Efficient fixed-point function implementation is critical in many FPGA application domains including convolutional neural networks, computer vision, and communication systems. In this work we focus on functions of the form $ x^p $, with $ p \in \{ - 1, - 1 / 2, 1 / 2 \} $ as part of a function generator targeting FPGAs. The generator implements architectures based on new but also existing algorithms. In this work we present three distinct methods implemented in this generator that outperform state-of-the-art implementations for certain configurations. Traditionally, fixed-point function implementation requires a normalization stage, compute and denormalization (reconstruction) of the result. The first proposed method implements the function holistically, thus saving the logic and latency required during the normalize and reconstruct stages. The second proposed method is based on a novel second order Taylor implementation. The third method is based on the cubic convergence of Halley's method, which is novel in this context. The proposed methods are compared and contrasted against state-of-the art implementations in the context of FPGA targets.

entry:
@InProceedings{Istoan:2017:FFP,
  author =       "Matei Istoan and Bogdan Pasca",
  title =        "Flexible Fixed-Point Function Generation for {FPGAs}",
  crossref =     "Burgess:2017:ISC",
  pages =        "123--130",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.31",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Efficient fixed-point function implementation is
                 critical in many FPGA application domains including
                 convolutional neural networks, computer vision, and
                 communication systems. In this work we focus on
                 functions of the form $ x^p $, with $ p \in \{ - 1, - 1
                 / 2, 1 / 2 \} $ as part of a function generator
                 targeting FPGAs. The generator implements architectures
                 based on new but also existing algorithms. In this work
                 we present three distinct methods implemented in this
                 generator that outperform state-of-the-art
                 implementations for certain configurations.
                 Traditionally, fixed-point function implementation
                 requires a normalization stage, compute and
                 denormalization (reconstruction) of the result. The
                 first proposed method implements the function
                 holistically, thus saving the logic and latency
                 required during the normalize and reconstruct stages.
                 The second proposed method is based on a novel second
                 order Taylor implementation. The third method is based
                 on the cubic convergence of Halley's method, which is
                 novel in this context. The proposed methods are
                 compared and contrasted against state-of-the art
                 implementations in the context of FPGA targets.",
  acknowledgement = ack-nhfb,
  keywords =     "arithmetic; communication systems; computer vision;
                 convolutional neural networks; cubic convergence;
                 Digital signal processing; Field programmable gate
                 arrays; field programmable gate arrays; fixed point
                 arithmetic; fixed-point; flexible fixed-point function
                 generation; FPGA; FPGAs; generator; Generators; Halley
                 method; Kernel; Memory management; reciprocal;
                 reciprocal sqrt; second order Taylor implementation;
                 Signal generators; sqrt",
}


bibtype: article
filename: fparith.bib
label: Jaiswal:2017:AEA
author: Manish Kumar Jaiswal and Hayden K.-H. So
title: Area-efficient Architecture for Dual-mode Double Precision Floating Point Division
journal: j-IEEE-TRANS-CIRCUITS-SYST-1
volume: 64
number: 2
pages: 386--398
month: feb
monthnumber: 2
year: 2017
DOI: https://doi.org/10.1109/TCSI.2016.2607227
ISSN: 1549-8328 (print), 1558-0806 (electronic) OR 15498328 (print), 15580806 (electronic)
ISSNL: 1549-8328 OR 15498328
bibdate: Sat Feb 08 10:59:51 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 10:59:51 ???
URL: https://ieeexplore.ieee.org/document/7590039
fjournal: IEEE Transactions on Circuits and Systems I: Regular Papers
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
rawauthor: Manish Kumar Jaiswal and Hayden K.-H. So
rawtitle: Area-efficient Architecture for Dual-mode Double Precision Floating Point Division
entry:
@Article{Jaiswal:2017:AEA,
  author =       "Manish Kumar Jaiswal and Hayden K.-H. So",
  title =        "Area-efficient Architecture for Dual-mode Double
                 Precision Floating Point Division",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "64",
  number =       "2",
  pages =        "386--398",
  month =        feb,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/TCSI.2016.2607227",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Feb 08 10:59:51 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/7590039",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}


bibtype: inproceedings
filename: fparith.bib
label: Jeannerod:2017:CRE
author: Claude-Pierre Jeannerod and Jean-Michel Muller and Antoine Plet
crossref: Burgess:2017:ISC
pages: 66--73
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.40
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Claude-Pierre Jeannerod and Jean-Michel Muller and Antoine Plet
title:
The Classical Relative Error Bounds for Computing $ sqrt (a^2 + b^2) $ and $ c / sqrt (a^2 + b^2) $ in Binary Floating-Point Arithmetic are Asymptotically Optimal

abstract:
We study the accuracy of classical algorithms for evaluating expressions of the form $ (a^2 + b^2) $ and $ c (a^2 + b^2) $ in radix-2, precision-$p$ floating-point arithmetic, assuming that the elementary arithmetic operations $ pm $, $ times $, $/$, $ sqrt $ are rounded to nearest, and assuming an unbounded exponent range. Classical analyses show that the relative error is bounded by $ 2 u + O(u^2)$ for $ (a^2 + b^2)$, and by $ 3 u + O(u^2)$ for $ c / (a^2 + b^2)$, where $ u = 2^-p$ is the unit roundoff. Recently, it was observed that for $ (a^2 + b^2)$ the $ O(u^2)$ term is in fact not needed [1]. We show here that it is not needed either for $ c / (a^2 + b^2)$. Furthermore, we show that these error bounds are asymptotically optimal. Finally, we show that both the bounds and their asymptotic optimality remain valid when an FMA instruction is used to evaluate $ a^2 + b^2$.

keywords:
Algorithm design and analysis; asymptotic optimality; binary floating-point arithmetic; classical relative error bounds; Digital arithmetic; Error analysis; floating point arithmetic; Floating-point arithmetic; FMA instruction; Force; hypotenuse function; Lips; precision-p floating-point arithmetic; relative error; rounding error analysis; unbounded exponent range; unit roundoff; Upper bound

rawabstract:
We study the accuracy of classical algorithms for evaluating expressions of the form $ (a^2 + b^2) $ and $ c (a^2 + b^2) $ in radix-2, precision-$p$ floating-point arithmetic, assuming that the elementary arithmetic operations $ \pm $, $ \times $, $/$, $ \sqrt $ are rounded to nearest, and assuming an unbounded exponent range. Classical analyses show that the relative error is bounded by $ 2 u + O(u^2)$ for $ (a^2 + b^2)$, and by $ 3 u + O(u^2)$ for $ c / (a^2 + b^2)$, where $ u = 2^{-p}$ is the unit roundoff. Recently, it was observed that for $ (a^2 + b^2)$ the $ O(u^2)$ term is in fact not needed [1]. We show here that it is not needed either for $ c / (a^2 + b^2)$. Furthermore, we show that these error bounds are asymptotically optimal. Finally, we show that both the bounds and their asymptotic optimality remain valid when an FMA instruction is used to evaluate $ a^2 + b^2$.

rawtitle:
The Classical Relative Error Bounds for Computing $ \sqrt (a^2 + b^2) $ and $ c / \sqrt (a^2 + b^2) $ in Binary Floating-Point Arithmetic are Asymptotically Optimal

entry:
@InProceedings{Jeannerod:2017:CRE,
  author =       "Claude-Pierre Jeannerod and Jean-Michel Muller and
                 Antoine Plet",
  title =        "The Classical Relative Error Bounds for Computing $
                 \sqrt (a^2 + b^2) $ and $ c / \sqrt (a^2 + b^2) $ in
                 Binary Floating-Point Arithmetic are Asymptotically
                 Optimal",
  crossref =     "Burgess:2017:ISC",
  pages =        "66--73",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.40",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We study the accuracy of classical algorithms for
                 evaluating expressions of the form $ (a^2 + b^2) $ and
                 $ c (a^2 + b^2) $ in radix-2, precision-$p$
                 floating-point arithmetic, assuming that the elementary
                 arithmetic operations $ \pm $, $ \times $, $/$, $ \sqrt
                 $ are rounded to nearest, and assuming an unbounded
                 exponent range. Classical analyses show that the
                 relative error is bounded by $ 2 u + O(u^2)$ for $ (a^2
                 + b^2)$, and by $ 3 u + O(u^2)$ for $ c / (a^2 + b^2)$,
                 where $ u = 2^{-p}$ is the unit roundoff. Recently, it
                 was observed that for $ (a^2 + b^2)$ the $ O(u^2)$ term
                 is in fact not needed [1]. We show here that it is not
                 needed either for $ c / (a^2 + b^2)$. Furthermore, we
                 show that these error bounds are asymptotically
                 optimal. Finally, we show that both the bounds and
                 their asymptotic optimality remain valid when an FMA
                 instruction is used to evaluate $ a^2 + b^2$.",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; asymptotic optimality;
                 binary floating-point arithmetic; classical relative
                 error bounds; Digital arithmetic; Error analysis;
                 floating point arithmetic; Floating-point arithmetic;
                 FMA instruction; Force; hypotenuse function; Lips;
                 precision-p floating-point arithmetic; relative error;
                 rounding error analysis; unbounded exponent range; unit
                 roundoff; Upper bound",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2017:EBC
author: Claude-Pierre Jeannerod and Peter Kornerup and Nicolas Louvet and Jean-Michel Muller
title: Error bounds on complex floating-point multiplication with an FMA
journal: j-MATH-COMPUT
volume: 86
number: 304
pages: 881--898
year: 2017
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3123
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Sat Feb 18 08:32:49 MST 2017
bibtimestamp: 2017.02.18 08:32:49 MST
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Claude-Pierre Jeannerod and Peter Kornerup and Nicolas Louvet and Jean-Michel Muller
rawtitle: Error bounds on complex floating-point multiplication with an {FMA}
bibsource:
http://www.ams.org/mcom/2017-86-304; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib

URL:
http://www.ams.org/journals/mcom/2017-86-304/S0025-5718-2016-03123-3; http://www.ams.org/journals/mcom/2017-86-304/S0025-5718-2016-03123-3/S0025-5718-2016-03123-3.pdf; http://www.ams.org/mathscinet/search/author.html?authorName=Kornerup%2C%20Peter; http://www.ams.org/mathscinet/search/author.html?authorName=Muller%2C%20Jean-Michel; http://www.ams.org/mathscinet/search/author.html?mrauthid=644190; http://www.ams.org/mathscinet/search/author.html?mrauthid=893389

entry:
@Article{Jeannerod:2017:EBC,
  author =       "Claude-Pierre Jeannerod and Peter Kornerup and Nicolas
                 Louvet and Jean-Michel Muller",
  title =        "Error bounds on complex floating-point multiplication
                 with an {FMA}",
  journal =      j-MATH-COMPUT,
  volume =       "86",
  number =       "304",
  pages =        "881--898",
  month =        "",
  year =         "2017",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3123",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Sat Feb 18 08:32:49 MST 2017",
  bibsource =    "http://www.ams.org/mcom/2017-86-304;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib",
  URL =          "http://www.ams.org/journals/mcom/2017-86-304/S0025-5718-2016-03123-3;
                 http://www.ams.org/journals/mcom/2017-86-304/S0025-5718-2016-03123-3/S0025-5718-2016-03123-3.pdf;
                 http://www.ams.org/mathscinet/search/author.html?authorName=Kornerup%2C%20Peter;
                 http://www.ams.org/mathscinet/search/author.html?authorName=Muller%2C%20Jean-Michel;
                 http://www.ams.org/mathscinet/search/author.html?mrauthid=644190;
                 http://www.ams.org/mathscinet/search/author.html?mrauthid=893389",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: inproceedings
filename: fparith.bib
label: Jeannerod:2017:REC
author: Claude-Pierre Jeannerod and Jean-Michel Muller
editor: Michael B. Matthews
title: On the relative error of computing complex square roots in floating-point arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 737--740
year: 2017
DOI: https://doi.org/10.1109/ACSSC.2017.8335442
ISBN: 1-5386-1823-0 OR 1538618230
ISBN13: 978-1-5386-1823-3 OR 9781538618233
bibdate: Fri Sep 29 10:59:32 2023
bibtimestamp: 2023.09.29 10:59:32 ???
acknowledgement: ack-nhfb
rawauthor: Claude-Pierre Jeannerod and Jean-Michel Muller
raweditor: Michael B. Matthews
rawtitle: On the relative error of computing complex square roots in floating-point arithmetic
booktitle:
2017 51st Asilomar Conference on Signals, Systems, and Computers. October 29--November 1, 2017. Pacific Grove, California

abstract:
We study the accuracy of a classical approach to computing complex square-roots in floating-point arithmetic. Our analyses are done in binary floating-point arithmetic in precision p, and we assume that the (real) arithmetic operations $+$, $-$, $ times $, $ div $, $ sqrt $ are rounded to nearest, so the unit roundoff is $ u = 2^-p $. We show that in the absence of underflow and overflow, the componentwise and normwise relative errors of this approach are at most $ 7 / 2 u $ and $ sqrt 37 / 2 u $, respectively, and this without having to neglect terms of higher order in $u$. We then provide some input examples showing that these bounds are reasonably sharp for the three basic binary interchange formats (binary32, binary64, and binary128) of the IEEE 754 standard for floating-point arithmetic.

rawabstract:
We study the accuracy of a classical approach to computing complex square-roots in floating-point arithmetic. Our analyses are done in binary floating-point arithmetic in precision p, and we assume that the (real) arithmetic operations $+$, $-$, $ \times $, $ \div $, $ \sqrt {} $ are rounded to nearest, so the unit roundoff is $ u = 2^{-p} $. We show that in the absence of underflow and overflow, the componentwise and normwise relative errors of this approach are at most $ 7 / 2 u $ and $ \sqrt {37} / 2 u $, respectively, and this without having to neglect terms of higher order in $u$. We then provide some input examples showing that these bounds are reasonably sharp for the three basic binary interchange formats (binary32, binary64, and binary128) of the IEEE 754 standard for floating-point arithmetic.

rawbooktitle:
{2017 51st Asilomar Conference on Signals, Systems, and Computers. October 29--November 1, 2017. Pacific Grove, California}

entry:
@InProceedings{Jeannerod:2017:REC,
  author =       "Claude-Pierre Jeannerod and Jean-Michel Muller",
  editor =       "Michael B. Matthews",
  booktitle =    "{2017 51st Asilomar Conference on Signals, Systems,
                 and Computers. October 29--November 1, 2017. Pacific
                 Grove, California}",
  title =        "On the relative error of computing complex square
                 roots in floating-point arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "737--740",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ACSSC.2017.8335442",
  ISBN =         "1-5386-1823-0",
  ISBN-13 =      "978-1-5386-1823-3",
  bibdate =      "Fri Sep 29 10:59:32 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We study the accuracy of a classical approach to
                 computing complex square-roots in floating-point
                 arithmetic. Our analyses are done in binary
                 floating-point arithmetic in precision p, and we assume
                 that the (real) arithmetic operations $+$, $-$, $
                 \times $, $ \div $, $ \sqrt {} $ are rounded to
                 nearest, so the unit roundoff is $ u = 2^{-p} $. We
                 show that in the absence of underflow and overflow, the
                 componentwise and normwise relative errors of this
                 approach are at most $ 7 / 2 u $ and $ \sqrt {37} / 2 u
                 $, respectively, and this without having to neglect
                 terms of higher order in $u$. We then provide some
                 input examples showing that these bounds are reasonably
                 sharp for the three basic binary interchange formats
                 (binary32, binary64, and binary128) of the IEEE 754
                 standard for floating-point arithmetic.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Johansson:2017:AEA
author: Fredrik Johansson
title: Arb: Efficient Arbitrary-Precision Midpoint--Radius Interval Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 8
pages: 1281--1292
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2690633
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 13 14:57:15 MDT 2017
bibtimestamp: 2017.07.13 14:57:15 MDT
URL: http://ieeexplore.ieee.org/document/7891956/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Fredrik Johansson
rawtitle: {Arb}: Efficient Arbitrary-Precision Midpoint--Radius Interval Arithmetic
entry:
@Article{Johansson:2017:AEA,
  author =       "Fredrik Johansson",
  title =        "{Arb}: Efficient Arbitrary-Precision Midpoint--Radius
                 Interval Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "8",
  pages =        "1281--1292",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2690633",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 13 14:57:15 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7891956/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Joldes:2017:IPE
author: Mioara Joldes and Jean-Michel Muller and Valentina Popescu
crossref: Burgess:2017:ISC
pages: 27--34
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.18
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Mioara Joldes and Jean-Michel Muller and Valentina Popescu
title:
Implementation and Performance Evaluation of an Extended Precision Floating-Point Arithmetic Library for High-Accuracy Semidefinite Programming

abstract:
Semidefinite programming (SDP) is widely used in optimization problems with many applications, however, certain SDP instances are ill-posed and need more precision than the standard double-precision available. Moreover, these problems are large-scale and could benefit from parallelization on specialized architectures such as GPUs. In this article, we implement and evaluate the performance of a floating-point expansion-based arithmetic library (CAMPARY) in the context of such numerically highly accurate SDP solvers. We plugged-in CAMPARY with the state-of-the-art SDPA solver for both CPU and GPU-tuned implementations. We compare and contrast both the numerical accuracy and performance of SDPA-GMP, -QD and -DD, which employ other multiple-precision arithmetic libraries against SDPA-CAMPARY. We show that CAMPARY is a very good trade-off for accuracy and speed when solving ill-conditioned SDP problems.

keywords:
CAMPARY; CPU; error-free transform; floating point arithmetic; floating-point arithmetic; floating-point expansion-based arithmetic library; floating-point expansions; GPGPU computing; GPU; graphics processing units; Graphics processing units; ill-posed semidefinite programming; Libraries; mathematical programming; mathematics computing; multiple precision library; multiple-precision arithmetic libraries; Optimization; Programming; SDP; SDPA-DD; SDPA-GMP; SDPA-QD; semidefinite programming; Standards; Symmetric matrices; Transforms

rawabstract:
Semidefinite programming (SDP) is widely used in optimization problems with many applications, however, certain SDP instances are ill-posed and need more precision than the standard double-precision available. Moreover, these problems are large-scale and could benefit from parallelization on specialized architectures such as GPUs. In this article, we implement and evaluate the performance of a floating-point expansion-based arithmetic library (CAMPARY) in the context of such numerically highly accurate SDP solvers. We plugged-in CAMPARY with the state-of-the-art SDPA solver for both CPU and GPU-tuned implementations. We compare and contrast both the numerical accuracy and performance of SDPA-GMP, -QD and -DD, which employ other multiple-precision arithmetic libraries against SDPA-CAMPARY. We show that CAMPARY is a very good trade-off for accuracy and speed when solving ill-conditioned SDP problems.

rawtitle:
Implementation and Performance Evaluation of an Extended Precision Floating-Point Arithmetic Library for High-Accuracy Semidefinite Programming

entry:
@InProceedings{Joldes:2017:IPE,
  author =       "Mioara Joldes and Jean-Michel Muller and Valentina
                 Popescu",
  title =        "Implementation and Performance Evaluation of an
                 Extended Precision Floating-Point Arithmetic Library
                 for High-Accuracy Semidefinite Programming",
  crossref =     "Burgess:2017:ISC",
  pages =        "27--34",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.18",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Semidefinite programming (SDP) is widely used in
                 optimization problems with many applications, however,
                 certain SDP instances are ill-posed and need more
                 precision than the standard double-precision available.
                 Moreover, these problems are large-scale and could
                 benefit from parallelization on specialized
                 architectures such as GPUs. In this article, we
                 implement and evaluate the performance of a
                 floating-point expansion-based arithmetic library
                 (CAMPARY) in the context of such numerically highly
                 accurate SDP solvers. We plugged-in CAMPARY with the
                 state-of-the-art SDPA solver for both CPU and GPU-tuned
                 implementations. We compare and contrast both the
                 numerical accuracy and performance of SDPA-GMP, -QD and
                 -DD, which employ other multiple-precision arithmetic
                 libraries against SDPA-CAMPARY. We show that CAMPARY is
                 a very good trade-off for accuracy and speed when
                 solving ill-conditioned SDP problems.",
  acknowledgement = ack-nhfb,
  keywords =     "CAMPARY; CPU; error-free transform; floating point
                 arithmetic; floating-point arithmetic; floating-point
                 expansion-based arithmetic library; floating-point
                 expansions; GPGPU computing; GPU; graphics processing
                 units; Graphics processing units; ill-posed
                 semidefinite programming; Libraries; mathematical
                 programming; mathematics computing; multiple precision
                 library; multiple-precision arithmetic libraries;
                 Optimization; Programming; SDP; SDPA-DD; SDPA-GMP;
                 SDPA-QD; semidefinite programming; Standards; Symmetric
                 matrices; Transforms",
}


bibtype: article
filename: fparith.bib
label: Joldes:2017:TRE
author: Mioara Joldes and Jean-Michel Muller and Valentina Popescu
title: Tight and Rigorous Error Bounds for Basic Building Blocks of Double-Word Arithmetic
journal: j-TOMS
volume: 44
number: 2
pages: 15res:1--15res:27
month: oct
monthnumber: 10
year: 2017
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3121432
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Oct 10 17:52:02 MDT 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2017.10.10 17:52:02 MDT
URL: https://dl.acm.org/citation.cfm?id=3121432
fjournal: ACM Transactions on Mathematical Software (TOMS)
remark: This article is erroneously assigned the same article number as the preceding one!
acknowledgement: ack-nhfb
articleno: 15res
journalURL: https://dl.acm.org/loi/toms
rawauthor: Mioara Joldes and Jean-Michel Muller and Valentina Popescu
rawtitle: Tight and Rigorous Error Bounds for Basic Building Blocks of Double-Word Arithmetic
abstract:
We analyze several classical basic building blocks of double-word arithmetic (frequently called ``double-double arithmetic'' in the literature): the addition of a double-word number and a floating-point number, the addition of two double-word numbers, the multiplication of a double-word number by a floating-point number, the multiplication of two double-word numbers, the division of a double-word number by a floating-point number, and the division of two double-word numbers. For multiplication and division we get better relative error bounds than the ones previously published. For addition of two double-word numbers, we show that the previously published bound was incorrect, and we provide a new relative error bound. We introduce new algorithms for division. We also give examples that illustrate the tightness of our bounds.

rawabstract:
We analyze several classical basic building blocks of double-word arithmetic (frequently called ``double-double arithmetic'' in the literature): the addition of a double-word number and a floating-point number, the addition of two double-word numbers, the multiplication of a double-word number by a floating-point number, the multiplication of two double-word numbers, the division of a double-word number by a floating-point number, and the division of two double-word numbers. For multiplication and division we get better relative error bounds than the ones previously published. For addition of two double-word numbers, we show that the previously published bound was incorrect, and we provide a new relative error bound. We introduce new algorithms for division. We also give examples that illustrate the tightness of our bounds.

entry:
@Article{Joldes:2017:TRE,
  author =       "Mioara Joldes and Jean-Michel Muller and Valentina
                 Popescu",
  title =        "Tight and Rigorous Error Bounds for Basic Building
                 Blocks of Double-Word Arithmetic",
  journal =      j-TOMS,
  volume =       "44",
  number =       "2",
  pages =        "15res:1--15res:27",
  month =        oct,
  year =         "2017",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3121432",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Oct 10 17:52:02 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3121432",
  abstract =     "We analyze several classical basic building blocks of
                 double-word arithmetic (frequently called
                 ``double-double arithmetic'' in the literature): the
                 addition of a double-word number and a floating-point
                 number, the addition of two double-word numbers, the
                 multiplication of a double-word number by a
                 floating-point number, the multiplication of two
                 double-word numbers, the division of a double-word
                 number by a floating-point number, and the division of
                 two double-word numbers. For multiplication and
                 division we get better relative error bounds than the
                 ones previously published. For addition of two
                 double-word numbers, we show that the previously
                 published bound was incorrect, and we provide a new
                 relative error bound. We introduce new algorithms for
                 division. We also give examples that illustrate the
                 tightness of our bounds.",
  acknowledgement = ack-nhfb,
  articleno =    "15res",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  remark =       "This article is erroneously assigned the same article
                 number as the preceding one!",
}


bibtype: misc
filename: fparith.bib
label: Jorgensen:2017:ACR
author: Alan A. Jorgensen
pages: 15res:1--15res:27
day: 14
month: nov
monthnumber: 11
year: 2017
bibdate: Fri Mar 23 19:14:44 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.23 19:14:44 ???
URL: https://patents.google.com/patent/US9817662B2/; https://tinyurl.com/y7ctbsez
acknowledgement: ack-nhfb
howpublished: US Patent 9,817,662.
rawauthor: Alan A. Jorgensen
title:
Apparatus for Calculating and Retaining a Bound on Error During Floating Point Operations and Methods Thereof

note:
This patent, filed 23 October 2016, was issued despite substantial prior art that should have resulted in its rejection: see cite Trader:2018:ICS. The inventor does not appear to have published in the area of floating-point arithmetic (apart from this entry, none by him can be found in this bibliography). The only literature references in the patent are cite Monniaux:2008:PVF,Goldberg:1991:WEC,Masotti:2012:FPN,Muller:2010:HFP.

abstract:
The apparatus and method for calculating and retaining a bound on error during floating point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, which accounts for both rounding and cancellation errors, has two parts, the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating point representation that are no longer meaningful. The bounds on the real value represented are determined from the truncated floating point value (first bound) and the addition of the error determined by the number of lost bits (second bound). The true, real value is absolutely contained by the first and second bounds. The allowed loss (optionally programmable) of significant bits provides a fail-safe, real-time notification of loss of significant bits.

rawabstract:
The apparatus and method for calculating and retaining a bound on error during floating point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, which accounts for both rounding and cancellation errors, has two parts, the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating point representation that are no longer meaningful. The bounds on the real value represented are determined from the truncated floating point value (first bound) and the addition of the error determined by the number of lost bits (second bound). The true, real value is absolutely contained by the first and second bounds. The allowed loss (optionally programmable) of significant bits provides a fail-safe, real-time notification of loss of significant bits.

rawnote:
This patent, filed 23 October 2016, was issued despite substantial prior art that should have resulted in its rejection: see \cite{Trader:2018:ICS}. The inventor does not appear to have published in the area of floating-point arithmetic (apart from this entry, none by him can be found in this bibliography). The only literature references in the patent are \cite{Monniaux:2008:PVF,Goldberg:1991:WEC,Masotti:2012:FPN,Muller:2010:HFP}.

rawtitle:
Apparatus for Calculating and Retaining a Bound on Error During Floating Point Operations and Methods Thereof

entry:
@Misc{Jorgensen:2017:ACR,
  author =       "Alan A. Jorgensen",
  title =        "Apparatus for Calculating and Retaining a Bound on
                 Error During Floating Point Operations and Methods
                 Thereof",
  howpublished = "US Patent 9,817,662.",
  day =          "14",
  month =        nov,
  year =         "2017",
  bibdate =      "Fri Mar 23 19:14:44 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This patent, filed 23 October 2016, was issued despite
                 substantial prior art that should have resulted in its
                 rejection: see \cite{Trader:2018:ICS}. The inventor
                 does not appear to have published in the area of
                 floating-point arithmetic (apart from this entry, none
                 by him can be found in this bibliography). The only
                 literature references in the patent are
                 \cite{Monniaux:2008:PVF,Goldberg:1991:WEC,Masotti:2012:FPN,Muller:2010:HFP}.",
  URL =          "https://patents.google.com/patent/US9817662B2/;
                 https://tinyurl.com/y7ctbsez",
  abstract =     "The apparatus and method for calculating and retaining
                 a bound on error during floating point operations
                 inserts an additional bounding field into the standard
                 floating-point format that records the retained
                 significant bits of the calculation with notification
                 upon insufficient retention. The bounding field, which
                 accounts for both rounding and cancellation errors, has
                 two parts, the lost bits D Field and the accumulated
                 rounding error R Field. The D Field states the number
                 of bits in the floating point representation that are
                 no longer meaningful. The bounds on the real value
                 represented are determined from the truncated floating
                 point value (first bound) and the addition of the error
                 determined by the number of lost bits (second bound).
                 The true, real value is absolutely contained by the
                 first and second bounds. The allowed loss (optionally
                 programmable) of significant bits provides a fail-safe,
                 real-time notification of loss of significant bits.",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Kneusel:2017:NC
author: Ronald T. Kneusel
title: Numbers and Computers
publisher: pub-SV
address: pub-SV:adr
edition: Second
pages: xiii + 346
year: 2017
DOI: https://doi.org/10.1007/978-3-319-50508-4
ISBN: 3-319-50507-6, 3-319-50508-4 (e-book) OR 3319505076, 3319505084 (ebook)
ISBN13: 978-3-319-50507-7, 978-3-319-50508-4 (e-book) OR 9783319505077, 9783319505084 (ebook)
bibdate: Tue Aug 22 05:58:01 MDT 2017
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.08.22 05:58:01 MDT
URL: http://link.springer.com/10.1007/978-3-319-50508-4
acknowledgement: ack-nhfb
rawauthor: Ronald T. Kneusel
rawtitle: Numbers and Computers
abstract:
This is a book about numbers and how those numbers are represented in and operated on by computers. It is crucial that developers understand this area because the numerical operations allowed by computers, and the limitations of those operations, especially in the area of floating point math, affect virtually everything people try to do with computers. This book aims to fill this gap by exploring, in sufficient but not overwhelming detail, just what it is that computers do with numbers. Divided into two parts, the first deals with standard representations of integers and floating point numbers, while the second examines several other number representations. Details are explained thoroughly, with clarity and specificity. Each chapter ends with a summary, recommendations, carefully selected references, and exercises to review the key points. Topics covered include interval arithmetic, fixed-point numbers, big integers and rational arithmetic. This new edition has three new chapters: Pitfalls of Floating-Point Numbers (and How to Avoid Them), Arbitrary Precision Floating Point, and Other Number Systems. This book is for anyone who develops software including software engineers, scientists, computer science students, engineering students and anyone who programs for fun.

subject:
Number theory; Numerals; Numeration; Computer science; Mathematics; Mathematics; Number theory; Numerals; Numeration; Arithmetic and Logic Structures; Numeric Computing; Arithmetik; Informatik; Software Engineering.

TOC:
Number Systems Integers Floating Point Pitfalls of Floating-Point Numbers (and How to Avoid Them) Big Integers and Rational Arithmetic Fixed-Point Numbers Decimal Floating Point Interval Arithmetic Arbitrary Precision Floating-Point Other Number Systems

rawabstract:
This is a book about numbers and how those numbers are represented in and operated on by computers. It is crucial that developers understand this area because the numerical operations allowed by computers, and the limitations of those operations, especially in the area of floating point math, affect virtually everything people try to do with computers. This book aims to fill this gap by exploring, in sufficient but not overwhelming detail, just what it is that computers do with numbers. Divided into two parts, the first deals with standard representations of integers and floating point numbers, while the second examines several other number representations. Details are explained thoroughly, with clarity and specificity. Each chapter ends with a summary, recommendations, carefully selected references, and exercises to review the key points. Topics covered include interval arithmetic, fixed-point numbers, big integers and rational arithmetic. This new edition has three new chapters: Pitfalls of Floating-Point Numbers (and How to Avoid Them), Arbitrary Precision Floating Point, and Other Number Systems. This book is for anyone who develops software including software engineers, scientists, computer science students, engineering students and anyone who programs for fun.

rawTOC:
Number Systems \\ Integers \\ Floating Point \\ Pitfalls of Floating-Point Numbers (and How to Avoid Them) \\ Big Integers and Rational Arithmetic \\ Fixed-Point Numbers \\ Decimal Floating Point \\ Interval Arithmetic \\ Arbitrary Precision Floating-Point \\ Other Number Systems

entry:
@Book{Kneusel:2017:NC,
  author =       "Ronald T. Kneusel",
  title =        "Numbers and Computers",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  edition =      "Second",
  pages =        "xiii + 346",
  year =         "2017",
  DOI =          "https://doi.org/10.1007/978-3-319-50508-4",
  ISBN =         "3-319-50507-6, 3-319-50508-4 (e-book)",
  ISBN-13 =      "978-3-319-50507-7, 978-3-319-50508-4 (e-book)",
  LCCN =         "????",
  bibdate =      "Tue Aug 22 05:58:01 MDT 2017",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.com/10.1007/978-3-319-50508-4",
  abstract =     "This is a book about numbers and how those numbers are
                 represented in and operated on by computers. It is
                 crucial that developers understand this area because
                 the numerical operations allowed by computers, and the
                 limitations of those operations, especially in the area
                 of floating point math, affect virtually everything
                 people try to do with computers. This book aims to fill
                 this gap by exploring, in sufficient but not
                 overwhelming detail, just what it is that computers do
                 with numbers. Divided into two parts, the first deals
                 with standard representations of integers and floating
                 point numbers, while the second examines several other
                 number representations. Details are explained
                 thoroughly, with clarity and specificity. Each chapter
                 ends with a summary, recommendations, carefully
                 selected references, and exercises to review the key
                 points. Topics covered include interval arithmetic,
                 fixed-point numbers, big integers and rational
                 arithmetic. This new edition has three new chapters:
                 Pitfalls of Floating-Point Numbers (and How to Avoid
                 Them), Arbitrary Precision Floating Point, and Other
                 Number Systems. This book is for anyone who develops
                 software including software engineers, scientists,
                 computer science students, engineering students and
                 anyone who programs for fun.",
  acknowledgement = ack-nhfb,
  subject =      "Number theory; Numerals; Numeration; Computer science;
                 Mathematics; Mathematics; Number theory; Numerals;
                 Numeration; Arithmetic and Logic Structures; Numeric
                 Computing; Arithmetik; Informatik; Software
                 Engineering.",
  tableofcontents = "Number Systems \\
                 Integers \\
                 Floating Point \\
                 Pitfalls of Floating-Point Numbers (and How to Avoid
                 Them) \\
                 Big Integers and Rational Arithmetic \\
                 Fixed-Point Numbers \\
                 Decimal Floating Point \\
                 Interval Arithmetic \\
                 Arbitrary Precision Floating-Point \\
                 Other Number Systems",
}


bibtype: inproceedings
filename: fparith.bib
label: Koenig:2017:HAC
author: Jack Koenig and David Biancolin and Jonathan Bachrach and Krste Asanovic
title: A Hardware Accelerator for Computing an Exact Dot Product
crossref: Burgess:2017:ISC
pages: 114--121
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.38
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Jack Koenig and David Biancolin and Jonathan Bachrach and Krste Asanovic
rawtitle: A Hardware Accelerator for Computing an Exact Dot Product
abstract:
We study the implementation of a hardware accelerator that computes a dot product of IEEE-754 floating-point numbers exactly. The accelerator uses a wide (640 or 4288 bits for single or double-precision respectively) fixed-point representation into which intermediate floating-point products are accumulated. We designed the accelerator as a generator in Chisel, which can synthesize various configurations of the accelerator that make different area-performance trade-offs. We integrated eight different configurations into an SoC comprised of RISC-V in-order scalar core, split L1 instruction and data caches, and unified L2 cache. In a TSMC 45 nm technology, the accelerator area ranges from 0.05 mm2 to 0.32 mm2, and all configurations could be clocked at frequencies in excess of 900MHz. The accelerator successfully saturates the SoC's memory system, achieving the same per-element efficiency (1 cycle-per-element) as Intel MKL running on an x86 machine with a similar cache configuration.

keywords:
accurate floating-point dot product; accurate floating-point summation; area-performance trade-offs; Bandwidth; cache configuration; cache storage; Chisel; Coprocessors; data caches; exact dot product; fixed point arithmetic; fixed-point representation; floating point arithmetic; Generators; Hardware; hardware accelerator; IEEE-754 floating-point numbers; Intel MKL; intermediate floating-point products; Microarchitecture; Registers; RISC-V in-order scalar core; Rockets; size 45 nm; SoC memory system; split L1 instruction; system-on-chip; TSMC technology; unified L2 cache

rawabstract:
We study the implementation of a hardware accelerator that computes a dot product of IEEE-754 floating-point numbers exactly. The accelerator uses a wide (640 or 4288 bits for single or double-precision respectively) fixed-point representation into which intermediate floating-point products are accumulated. We designed the accelerator as a generator in Chisel, which can synthesize various configurations of the accelerator that make different area-performance trade-offs. We integrated eight different configurations into an SoC comprised of RISC-V in-order scalar core, split L1 instruction and data caches, and unified L2 cache. In a TSMC 45 nm technology, the accelerator area ranges from 0.05 mm2 to 0.32 mm2, and all configurations could be clocked at frequencies in excess of 900MHz. The accelerator successfully saturates the SoC's memory system, achieving the same per-element efficiency (1 cycle-per-element) as Intel MKL running on an x86 machine with a similar cache configuration.

entry:
@InProceedings{Koenig:2017:HAC,
  author =       "Jack Koenig and David Biancolin and Jonathan Bachrach
                 and Krste Asanovic",
  title =        "A Hardware Accelerator for Computing an Exact Dot
                 Product",
  crossref =     "Burgess:2017:ISC",
  pages =        "114--121",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.38",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We study the implementation of a hardware accelerator
                 that computes a dot product of IEEE-754 floating-point
                 numbers exactly. The accelerator uses a wide (640 or
                 4288 bits for single or double-precision respectively)
                 fixed-point representation into which intermediate
                 floating-point products are accumulated. We designed
                 the accelerator as a generator in Chisel, which can
                 synthesize various configurations of the accelerator
                 that make different area-performance trade-offs. We
                 integrated eight different configurations into an SoC
                 comprised of RISC-V in-order scalar core, split L1
                 instruction and data caches, and unified L2 cache. In a
                 TSMC 45 nm technology, the accelerator area ranges from
                 0.05 mm2 to 0.32 mm2, and all configurations could be
                 clocked at frequencies in excess of 900MHz. The
                 accelerator successfully saturates the SoC's memory
                 system, achieving the same per-element efficiency (1
                 cycle-per-element) as Intel MKL running on an x86
                 machine with a similar cache configuration.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point dot product; accurate
                 floating-point summation; area-performance trade-offs;
                 Bandwidth; cache configuration; cache storage; Chisel;
                 Coprocessors; data caches; exact dot product; fixed
                 point arithmetic; fixed-point representation; floating
                 point arithmetic; Generators; Hardware; hardware
                 accelerator; IEEE-754 floating-point numbers; Intel
                 MKL; intermediate floating-point products;
                 Microarchitecture; Registers; RISC-V in-order scalar
                 core; Rockets; size 45 nm; SoC memory system; split L1
                 instruction; system-on-chip; TSMC technology; unified
                 L2 cache",
}


bibtype: inproceedings
filename: fparith.bib
label: Kohlbrenner:2017:EMA
author: David Kohlbrenner and Hovav Shacham
editor: Another
booktitle: Proceedings of the 26th Usenix Security Symposium, August 16--18, 2017, Vancouver, BC, Canada
title: On the effectiveness of mitigations against floating-point timing channels
publisher: pub-USENIX
address: pub-USENIX:adr
pages: 69--81
year: 2017
ISBN: 1-931971-40-4 OR 1931971404
ISBN13: 978-1-931971-40-9 OR 9781931971409
LCCN: QA76.9.D5 P76 2005
bibdate: Mon Aug 26 10:26:59 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.26 10:26:59 ???
keywords: libfixedtimefixedpoint
acknowledgement: ack-nhfb
rawauthor: David Kohlbrenner and Hovav Shacham
rawbooktitle: Proceedings of the {26th Usenix Security Symposium, August 16--18, 2017, Vancouver, BC, Canada}
raweditor: Another
rawtitle: On the effectiveness of mitigations against floating-point timing channels
URL:
https://github.com/kmowery/libfixedtimefixedpoint; https://www.usenix.org/system/files/conference/usenixsecurity17/sec17-kohlbrenner.pdf

abstract:
The duration of floating-point instructions is a known timing side channel that has been used to break Same-Origin Policy (SOP) privacy on Mozilla Firefox and the Fuzz differentially private database. Several defenses have been proposed to mitigate these attacks.par We present detailed benchmarking of floating point performance for various operations based on operand values. We identify families of values that induce slow and fast paths beyond the classes (normal, subnormal, etc.) considered in previous work, and note that different processors exhibit different timing behavior.par We evaluate the efficacy of the defenses deployed (or not) in Web browsers to floating point side channel attacks on SVG filters. We find that Google Chrome, Mozilla Firefox, and Apple's Safari have insufficiently addressed the floating-point side channel, and we present attacks for each that extract pixel data cross-origin on most platforms.par We evaluate the vector-operation based defensive mechanism proposed at USENIX Security 2016 by Rane, Lin and Tiwari and find that it only reduces, not eliminates, the floating-point side channel signal. Together, these measurements and attacks cause us to conclude that floating point is simply too variable to use in a timing security sensitive context.

rawabstract:
The duration of floating-point instructions is a known timing side channel that has been used to break Same-Origin Policy (SOP) privacy on Mozilla Firefox and the Fuzz differentially private database. Several defenses have been proposed to mitigate these attacks.\par We present detailed benchmarking of floating point performance for various operations based on operand values. We identify families of values that induce slow and fast paths beyond the classes (normal, subnormal, etc.) considered in previous work, and note that different processors exhibit different timing behavior.\par We evaluate the efficacy of the defenses deployed (or not) in Web browsers to floating point side channel attacks on SVG filters. We find that Google Chrome, Mozilla Firefox, and Apple's Safari have insufficiently addressed the floating-point side channel, and we present attacks for each that extract pixel data cross-origin on most platforms.\par We evaluate the vector-operation based defensive mechanism proposed at USENIX Security 2016 by Rane, Lin and Tiwari and find that it only reduces, not eliminates, the floating-point side channel signal. Together, these measurements and attacks cause us to conclude that floating point is simply too variable to use in a timing security sensitive context.

entry:
@InProceedings{Kohlbrenner:2017:EMA,
  author =       "David Kohlbrenner and Hovav Shacham",
  editor =       "Another",
  booktitle =    "Proceedings of the {26th Usenix Security Symposium,
                 August 16--18, 2017, Vancouver, BC, Canada}",
  title =        "On the effectiveness of mitigations against
                 floating-point timing channels",
  publisher =    pub-USENIX,
  address =      pub-USENIX:adr,
  pages =        "69--81",
  year =         "2017",
  ISBN =         "1-931971-40-4",
  ISBN-13 =      "978-1-931971-40-9",
  LCCN =         "QA76.9.D5 P76 2005",
  bibdate =      "Mon Aug 26 10:26:59 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://github.com/kmowery/libfixedtimefixedpoint;
                 https://www.usenix.org/system/files/conference/usenixsecurity17/sec17-kohlbrenner.pdf",
  abstract =     "The duration of floating-point instructions is a known
                 timing side channel that has been used to break
                 Same-Origin Policy (SOP) privacy on Mozilla Firefox and
                 the Fuzz differentially private database. Several
                 defenses have been proposed to mitigate these
                 attacks.\par

                 We present detailed benchmarking of floating point
                 performance for various operations based on operand
                 values. We identify families of values that induce slow
                 and fast paths beyond the classes (normal, subnormal,
                 etc.) considered in previous work, and note that
                 different processors exhibit different timing
                 behavior.\par

                 We evaluate the efficacy of the defenses deployed (or
                 not) in Web browsers to floating point side channel
                 attacks on SVG filters. We find that Google Chrome,
                 Mozilla Firefox, and Apple's Safari have insufficiently
                 addressed the floating-point side channel, and we
                 present attacks for each that extract pixel data
                 cross-origin on most platforms.\par

                 We evaluate the vector-operation based defensive
                 mechanism proposed at USENIX Security 2016 by Rane, Lin
                 and Tiwari and find that it only reduces, not
                 eliminates, the floating-point side channel signal.
                 Together, these measurements and attacks cause us to
                 conclude that floating point is simply too variable to
                 use in a timing security sensitive context.",
  acknowledgement = ack-nhfb,
  keywords =     "libfixedtimefixedpoint",
  remark-1 =     "This paper contains floating-point instruction timing
                 tables for the Intel i5-44609 CPU and Nvidia GeForce GT
                 430 GPU, with a brief table about the AMD Phenom II
                 X2-550. It demonstrates that timings can depend
                 significantly on operands, with subnormals sometimes
                 causing a slowdown of more than $ 20 \times $. The
                 scope of attacks from timing measurements is
                 surprisingly broad, including recovery of image pixels,
                 browser history, user geolocation, and browser search
                 strings. Several of the 18 references describe other
                 such attacks. One of the vulnerable graphics rendering
                 libraries, Skia, is used by multiple browsers and
                 window systems: see \url{https://skia.org/}.",
  remark-2 =     "From p. 80: ``Processor vendors have resisted calls to
                 document which of their instructions run in constant
                 time regardless of operands, even for operations as
                 basic as integer multiplication.''",
}


bibtype: article
filename: fparith.bib
label: Kumm:2017:OCM
author: Martin Kumm and Martin Hardieck and Peter Zipf
title: Optimization of Constant Matrix Multiplication with Low Power and High Throughput
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2072--2080
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2701365
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7919250/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Martin Kumm and Martin Hardieck and Peter Zipf
rawtitle: Optimization of Constant Matrix Multiplication with Low Power and High Throughput
entry:
@Article{Kumm:2017:OCM,
  author =       "Martin Kumm and Martin Hardieck and Peter Zipf",
  title =        "Optimization of Constant Matrix Multiplication with
                 Low Power and High Throughput",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2072--2080",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2701365",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7919250/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Kumm:2017:ROD
author: Martin Kumm and Johannes Kappauf and Matei Istoan and Peter Zipf
title: Resource Optimal Design of Large Multipliers for FPGAs
crossref: Burgess:2017:ISC
pages: 131--138
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.35
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Martin Kumm and Johannes Kappauf and Matei Istoan and Peter Zipf
rawtitle: Resource Optimal Design of Large Multipliers for {FPGAs}
abstract:
This work presents a resource optimal approach for the design of large multipliers for FPGAs. These are composed of smaller multipliers which can be DSP blocks or logic-based multipliers. A previously proposed multiplier tiling methodology is used to describe feasible solutions of the problem. The problem is then formulated as an integer linear programming (ILP) problem which can be solved by standard ILP solvers. It can be used to minimize the total implementation cost or to trade the LUT cost against the DSP cost. It is demonstrated that although the problem is NP-complete, optimal solutions can be found for most practical multiplier sizes up to 64x64. Synthesis experiments on relevant multiplier sizes show slice reductions of up to 47.5% compared to state-of-the-art heuristic approaches.

keywords:
Complexity theory; computational complexity; Digital arithmetic; Digital signal processing; DSP blocks; field programmable gate arrays; Field programmable gate arrays; FPGA; ILP; ILP problem; ILP solvers; integer linear programming problem; integer programming; linear programming; logic design; logic-based multipliers; LUT; multiplier; multiplier design; multiplier tiling methodology; multiplying circuits; NP-complete problem; Optimization; optimization; Shape; table lookup; Table lookup

rawabstract:
This work presents a resource optimal approach for the design of large multipliers for FPGAs. These are composed of smaller multipliers which can be DSP blocks or logic-based multipliers. A previously proposed multiplier tiling methodology is used to describe feasible solutions of the problem. The problem is then formulated as an integer linear programming (ILP) problem which can be solved by standard ILP solvers. It can be used to minimize the total implementation cost or to trade the LUT cost against the DSP cost. It is demonstrated that although the problem is NP-complete, optimal solutions can be found for most practical multiplier sizes up to 64x64. Synthesis experiments on relevant multiplier sizes show slice reductions of up to 47.5\% compared to state-of-the-art heuristic approaches.

entry:
@InProceedings{Kumm:2017:ROD,
  author =       "Martin Kumm and Johannes Kappauf and Matei Istoan and
                 Peter Zipf",
  title =        "Resource Optimal Design of Large Multipliers for
                 {FPGAs}",
  crossref =     "Burgess:2017:ISC",
  pages =        "131--138",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.35",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This work presents a resource optimal approach for the
                 design of large multipliers for FPGAs. These are
                 composed of smaller multipliers which can be DSP blocks
                 or logic-based multipliers. A previously proposed
                 multiplier tiling methodology is used to describe
                 feasible solutions of the problem. The problem is then
                 formulated as an integer linear programming (ILP)
                 problem which can be solved by standard ILP solvers. It
                 can be used to minimize the total implementation cost
                 or to trade the LUT cost against the DSP cost. It is
                 demonstrated that although the problem is NP-complete,
                 optimal solutions can be found for most practical
                 multiplier sizes up to 64x64. Synthesis experiments on
                 relevant multiplier sizes show slice reductions of up
                 to 47.5\% compared to state-of-the-art heuristic
                 approaches.",
  acknowledgement = ack-nhfb,
  keywords =     "Complexity theory; computational complexity; Digital
                 arithmetic; Digital signal processing; DSP blocks;
                 field programmable gate arrays; Field programmable gate
                 arrays; FPGA; ILP; ILP problem; ILP solvers; integer
                 linear programming problem; integer programming; linear
                 programming; logic design; logic-based multipliers;
                 LUT; multiplier; multiplier design; multiplier tiling
                 methodology; multiplying circuits; NP-complete problem;
                 Optimization; optimization; Shape; table lookup; Table
                 lookup",
}


bibtype: article
filename: fparith.bib
label: Lai:2017:DCN
author: Liangzhen Lai and Naveen Suda and Vikas Chandra
title: Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations
journal: arXiv.org
pages: 1--10
day: 8
month: mar
monthnumber: 3
year: 2017
bibdate: Fri Sep 28 06:16:02 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.09.28 06:16:02 ???
URL: https://arxiv.org/pdf/1703.03073.pdf
acknowledgement: ack-nhfb
rawauthor: Liangzhen Lai and Naveen Suda and Vikas Chandra
rawtitle: Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations
abstract:
Deep convolutional neural network (CNN) inference requires significant amount of memory and computation, which limits its deployment on embedded devices. To alleviate these problems to some extent, prior research utilize low precision fixed-point numbers to represent the CNN weights and activations. However, the minimum required data precision of fixed-point weights varies across different networks and also across different layers of the same network. In this work, we propose using floating-point numbers for representing the weights and fixed-point numbers for representing the activations. We show that using floating-point representation for weights is more efficient than fixed-point representation for the same bit-width and demonstrate it on popular large-scale CNNs such as AlexNet, SqueezeNet, GoogLeNet and VGG-16. We also show that such a representation scheme enables compact hardware multiply-and-accumulate (MAC) unit design. Experimental results show that the proposed scheme reduces the weight storage by up to 36% and power consumption of the hardware multiplier by up to 50%.

rawabstract:
Deep convolutional neural network (CNN) inference requires significant amount of memory and computation, which limits its deployment on embedded devices. To alleviate these problems to some extent, prior research utilize low precision fixed-point numbers to represent the CNN weights and activations. However, the minimum required data precision of fixed-point weights varies across different networks and also across different layers of the same network. In this work, we propose using floating-point numbers for representing the weights and fixed-point numbers for representing the activations. We show that using floating-point representation for weights is more efficient than fixed-point representation for the same bit-width and demonstrate it on popular large-scale CNNs such as AlexNet, SqueezeNet, GoogLeNet and VGG-16. We also show that such a representation scheme enables compact hardware multiply-and-accumulate (MAC) unit design. Experimental results show that the proposed scheme reduces the weight storage by up to 36\% and power consumption of the hardware multiplier by up to 50\%.

entry:
@Article{Lai:2017:DCN,
  author =       "Liangzhen Lai and Naveen Suda and Vikas Chandra",
  title =        "Deep Convolutional Neural Network Inference with
                 Floating-point Weights and Fixed-point Activations",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--10",
  day =          "8",
  month =        mar,
  year =         "2017",
  bibdate =      "Fri Sep 28 06:16:02 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/pdf/1703.03073.pdf",
  abstract =     "Deep convolutional neural network (CNN) inference
                 requires significant amount of memory and computation,
                 which limits its deployment on embedded devices. To
                 alleviate these problems to some extent, prior research
                 utilize low precision fixed-point numbers to represent
                 the CNN weights and activations. However, the minimum
                 required data precision of fixed-point weights varies
                 across different networks and also across different
                 layers of the same network. In this work, we propose
                 using floating-point numbers for representing the
                 weights and fixed-point numbers for representing the
                 activations. We show that using floating-point
                 representation for weights is more efficient than
                 fixed-point representation for the same bit-width and
                 demonstrate it on popular large-scale CNNs such as
                 AlexNet, SqueezeNet, GoogLeNet and VGG-16. We also show
                 that such a representation scheme enables compact
                 hardware multiply-and-accumulate (MAC) unit design.
                 Experimental results show that the proposed scheme
                 reduces the weight storage by up to 36\% and power
                 consumption of the hardware multiplier by up to 50\%.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Lam:2017:FPA
author: Mike Lam
title: Floating-Point Analysis Research
pages: 1--10
year: 2017
bibdate: Thu May 02 17:01:37 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.05.02 17:01:37 ???
URL: https://w3.cs.jmu.edu/lam2mo/fpanalysis.html
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Mike Lam
rawtitle: Floating-Point Analysis Research
abstract:
This page is a compilation of research efforts and software tools devoted to program analysis of floating-point code. This research area is a community of people from many different backgrounds: traditional PL, high performance computing, numerical analysis, and systems software. With this page, I am hoping to help form connections between people and projects that might previously have never encountered each other.

rawabstract:
This page is a compilation of research efforts and software tools devoted to program analysis of floating-point code. This research area is a community of people from many different backgrounds: traditional PL, high performance computing, numerical analysis, and systems software. With this page, I am hoping to help form connections between people and projects that might previously have never encountered each other.

entry:
@Misc{Lam:2017:FPA,
  author =       "Mike Lam",
  title =        "Floating-Point Analysis Research",
  howpublished = "Web site",
  year =         "2017",
  bibdate =      "Thu May 02 17:01:37 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://w3.cs.jmu.edu/lam2mo/fpanalysis.html",
  abstract =     "This page is a compilation of research efforts and
                 software tools devoted to program analysis of
                 floating-point code. This research area is a community
                 of people from many different backgrounds: traditional
                 PL, high performance computing, numerical analysis, and
                 systems software. With this page, I am hoping to help
                 form connections between people and projects that might
                 previously have never encountered each other.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Landy:2017:SAS
author: Aaron Landy and Greg Stitt
title: Serial Arithmetic Strategies for Improving FPGA Throughput
journal: j-TECS
volume: 16
number: 3
pages: 84:1--84:??
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1145/2996459
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Mon Jul 24 09:51:12 MDT 2017
bibtimestamp: 2017.07.24 09:51:12 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 84
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J840
rawauthor: Aaron Landy and Greg Stitt
rawtitle: Serial Arithmetic Strategies for Improving {FPGA} Throughput
abstract:
Serial arithmetic has been shown to offer attractive advantages in area for field-programmable gate array (FPGA) datapaths but suffers from a significant reduction in throughput compared to traditional bit-parallel designs. In this work, we perform a performance and trade-off analysis that counterintuitively shows that, despite the decreased throughput of individual serial operators, replication of serial arithmetic can provide a 2.1 $ times $ average increase in throughput compared to bit-parallel pipelines for common FPGA applications. We complement this analysis with a novel SerDes architecture that enables existing FPGA pipelines to be replaced with serial logic with potentially higher throughput. We also present a serialized sliding-window architecture that improves average throughput 2.4 $ times $ compared to existing bit-parallel work.

rawabstract:
Serial arithmetic has been shown to offer attractive advantages in area for field-programmable gate array (FPGA) datapaths but suffers from a significant reduction in throughput compared to traditional bit-parallel designs. In this work, we perform a performance and trade-off analysis that counterintuitively shows that, despite the decreased throughput of individual serial operators, replication of serial arithmetic can provide a 2.1 $ \times $ average increase in throughput compared to bit-parallel pipelines for common FPGA applications. We complement this analysis with a novel SerDes architecture that enables existing FPGA pipelines to be replaced with serial logic with potentially higher throughput. We also present a serialized sliding-window architecture that improves average throughput 2.4 $ \times $ compared to existing bit-parallel work.

entry:
@Article{Landy:2017:SAS,
  author =       "Aaron Landy and Greg Stitt",
  title =        "Serial Arithmetic Strategies for Improving {FPGA}
                 Throughput",
  journal =      j-TECS,
  volume =       "16",
  number =       "3",
  pages =        "84:1--84:??",
  month =        jul,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2996459",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Mon Jul 24 09:51:12 MDT 2017",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  abstract =     "Serial arithmetic has been shown to offer attractive
                 advantages in area for field-programmable gate array
                 (FPGA) datapaths but suffers from a significant
                 reduction in throughput compared to traditional
                 bit-parallel designs. In this work, we perform a
                 performance and trade-off analysis that
                 counterintuitively shows that, despite the decreased
                 throughput of individual serial operators, replication
                 of serial arithmetic can provide a 2.1 $ \times $
                 average increase in throughput compared to bit-parallel
                 pipelines for common FPGA applications. We complement
                 this analysis with a novel SerDes architecture that
                 enables existing FPGA pipelines to be replaced with
                 serial logic with potentially higher throughput. We
                 also present a serialized sliding-window architecture
                 that improves average throughput 2.4 $ \times $
                 compared to existing bit-parallel work.",
  acknowledgement = ack-nhfb,
  articleno =    "84",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J840",
}


bibtype: article
filename: fparith.bib
label: Lange:2017:EES
author: Marko Lange and Siegfried M. Rump
title: Error estimates for the summation of real numbers with application to floating-point summation
journal: j-BIT-NUM-MATH
volume: 57
number: 3
pages: 927--941
month: sep
monthnumber: 9
year: 2017
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-017-0658-9
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Mon Oct 2 11:20:22 MDT 2017
bibtimestamp: 2017.10.02 11:20:22 MDT
URL: https://link.springer.com/article/10.1007/s10543-017-0658-9
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: Marko Lange and Siegfried M. Rump
rawtitle: Error estimates for the summation of real numbers with application to floating-point summation
bibsource:
http://link.springer.com/journal/10543/57/3; https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Lange:2017:EES,
  author =       "Marko Lange and Siegfried M. Rump",
  title =        "Error estimates for the summation of real numbers with
                 application to floating-point summation",
  journal =      j-BIT-NUM-MATH,
  volume =       "57",
  number =       "3",
  pages =        "927--941",
  month =        sep,
  year =         "2017",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-017-0658-9",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Mon Oct 2 11:20:22 MDT 2017",
  bibsource =    "http://link.springer.com/journal/10543/57/3;
                 https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://link.springer.com/article/10.1007/s10543-017-0658-9",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: inproceedings
filename: fparith.bib
label: Langhammer:2017:FPT
author: Martin Langhammer and Bogdan Pasca
title: Floating Point Tangent Implementation for FPGAs
crossref: Burgess:2017:ISC
pages: 64--65
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.25
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Martin Langhammer and Bogdan Pasca
rawtitle: Floating Point Tangent Implementation for {FPGAs}
abstract:
This paper presents an implementation of the floating-point (FP) tangent function, optimized for an FPGA containing hard floating point (HFP) DSP Blocks. This function inputs values in the interval [- /2, /2], uses the IEEE-754 single-precision (SP) format, and has an accuracy conforming to OpenCL requirements. The presented architecture is based on a combination of mathematical identities and properties of the tangent function in FP. The resultant design outperforms generic polynomial approximation methods targeting the same resource utilization spectrum, and provides better resource trade-offs than classical CORDIC-based implementations. The presented work is widely available as part of the Intel DSP Builder Advanced Blockset.

keywords:
Approximation methods; classical CORDIC-based implementations; Digital arithmetic; Digital signal processing; digital signal processing chips; field programmable gate arrays; Field programmable gate arrays; fixed point arithmetic; floating point arithmetic; floating point tangent function; FPGAs; generic polynomial approximation methods; hard floating point DSP blocks; HFP DSP; IEEE-754 single-precision format; Intel DSP Builder Advanced Blockset; OpenCL; reconfigurable architectures; Resource management; resource utilization spectrum; Table lookup

rawabstract:
This paper presents an implementation of the floating-point (FP) tangent function, optimized for an FPGA containing hard floating point (HFP) DSP Blocks. This function inputs values in the interval [- /2, /2], uses the IEEE-754 single-precision (SP) format, and has an accuracy conforming to OpenCL requirements. The presented architecture is based on a combination of mathematical identities and properties of the tangent function in FP. The resultant design outperforms generic polynomial approximation methods targeting the same resource utilization spectrum, and provides better resource trade-offs than classical CORDIC-based implementations. The presented work is widely available as part of the Intel DSP Builder Advanced Blockset.

entry:
@InProceedings{Langhammer:2017:FPT,
  author =       "Martin Langhammer and Bogdan Pasca",
  title =        "Floating Point Tangent Implementation for {FPGAs}",
  crossref =     "Burgess:2017:ISC",
  pages =        "64--65",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.25",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents an implementation of the
                 floating-point (FP) tangent function, optimized for an
                 FPGA containing hard floating point (HFP) DSP Blocks.
                 This function inputs values in the interval [- /2, /2],
                 uses the IEEE-754 single-precision (SP) format, and has
                 an accuracy conforming to OpenCL requirements. The
                 presented architecture is based on a combination of
                 mathematical identities and properties of the tangent
                 function in FP. The resultant design outperforms
                 generic polynomial approximation methods targeting the
                 same resource utilization spectrum, and provides better
                 resource trade-offs than classical CORDIC-based
                 implementations. The presented work is widely available
                 as part of the Intel DSP Builder Advanced Blockset.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation methods; classical CORDIC-based
                 implementations; Digital arithmetic; Digital signal
                 processing; digital signal processing chips; field
                 programmable gate arrays; Field programmable gate
                 arrays; fixed point arithmetic; floating point
                 arithmetic; floating point tangent function; FPGAs;
                 generic polynomial approximation methods; hard floating
                 point DSP blocks; HFP DSP; IEEE-754 single-precision
                 format; Intel DSP Builder Advanced Blockset; OpenCL;
                 reconfigurable architectures; Resource management;
                 resource utilization spectrum; Table lookup",
}


bibtype: inproceedings
filename: fparith.bib
label: Langhammer:2017:QPA
author: Martin Langhammer
title: QRD for Parallel Arithmetic Structures
crossref: Burgess:2017:ISC
pages: 146--147
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.26
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Martin Langhammer
rawtitle: {QRD} for Parallel Arithmetic Structures
abstract:
We present a new organization of the QR decomposition (QRD), which is optimized for implementation on parallel arithmetic structures, such as found in current FPGAs. Data dependencies are hidden in the pipeline depths of the datapaths, allowing implementations to approach 100% sustained to peak throughput. The algorithm presented here is based on the Modified Gram-Schmidt (MGS) method, and is designed for floating point (FP) arithmetic, with a combination of separate dot product and multiply-add datapaths. In this short paper, we concentrate on the description of the algorithm and architecture, rather than the implementation, of the QRD.

keywords:
adders; Algorithm design and analysis; Computer architecture; data dependencies; field programmable gate arrays; Field programmable gate arrays; floating point arithmetic; FP arithmetic; FPGA; MGS method; modified Gram-Schmidt method; multiply-add datapaths; multiplying circuits; Organizations; parallel arithmetic structures; Pipelines; QR decomposition; QRD; Radar antennas; separate dot product; Throughput

rawabstract:
We present a new organization of the QR decomposition (QRD), which is optimized for implementation on parallel arithmetic structures, such as found in current FPGAs. Data dependencies are hidden in the pipeline depths of the datapaths, allowing implementations to approach 100\% sustained to peak throughput. The algorithm presented here is based on the Modified Gram-Schmidt (MGS) method, and is designed for floating point (FP) arithmetic, with a combination of separate dot product and multiply-add datapaths. In this short paper, we concentrate on the description of the algorithm and architecture, rather than the implementation, of the QRD.

entry:
@InProceedings{Langhammer:2017:QPA,
  author =       "Martin Langhammer",
  title =        "{QRD} for Parallel Arithmetic Structures",
  crossref =     "Burgess:2017:ISC",
  pages =        "146--147",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.26",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a new organization of the QR decomposition
                 (QRD), which is optimized for implementation on
                 parallel arithmetic structures, such as found in
                 current FPGAs. Data dependencies are hidden in the
                 pipeline depths of the datapaths, allowing
                 implementations to approach 100\% sustained to peak
                 throughput. The algorithm presented here is based on
                 the Modified Gram-Schmidt (MGS) method, and is designed
                 for floating point (FP) arithmetic, with a combination
                 of separate dot product and multiply-add datapaths. In
                 this short paper, we concentrate on the description of
                 the algorithm and architecture, rather than the
                 implementation, of the QRD.",
  acknowledgement = ack-nhfb,
  keywords =     "adders; Algorithm design and analysis; Computer
                 architecture; data dependencies; field programmable
                 gate arrays; Field programmable gate arrays; floating
                 point arithmetic; FP arithmetic; FPGA; MGS method;
                 modified Gram-Schmidt method; multiply-add datapaths;
                 multiplying circuits; Organizations; parallel
                 arithmetic structures; Pipelines; QR decomposition;
                 QRD; Radar antennas; separate dot product; Throughput",
}


bibtype: article
filename: fparith.bib
label: Langhammer:2017:SPL
author: Martin Langhammer and Bogdan Pasca
title: Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled FPGAs
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2031--2043
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2703923
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7927449/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Martin Langhammer and Bogdan Pasca
rawtitle: Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled {FPGAs}
entry:
@Article{Langhammer:2017:SPL,
  author =       "Martin Langhammer and Bogdan Pasca",
  title =        "Single Precision Logarithm and Exponential
                 Architectures for Hard Floating-Point Enabled {FPGAs}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2031--2043",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2703923",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7927449/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Lauter:2017:ESI
author: Christoph Lauter
crossref: Matthews:2017:CRF
pages: 452--456
year: 2017
DOI: https://doi.org/10.1109/ACSSC.2017.8335379
bibdate: Fri Feb 16 08:24:29 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.02.16 08:24:29 ???
acknowledgement: ack-nhfb
rawauthor: Christoph Lauter
title:
An Efficient Software Implementation of Correctly Rounded Operations Extending FMA: $ a + b + c $ and $ a times b + c times d $

keywords:
accurate floating-point summation; complex multiply; fused multiply-add; fused-add-add; fused-multiply-twice-and-add; three-sum

rawtitle:
An Efficient Software Implementation of Correctly Rounded Operations Extending {FMA}: $ a + b + c $ and $ a \times b + c \times d $

entry:
@InProceedings{Lauter:2017:ESI,
  author =       "Christoph Lauter",
  title =        "An Efficient Software Implementation of Correctly
                 Rounded Operations Extending {FMA}: $ a + b + c $ and $
                 a \times b + c \times d $",
  crossref =     "Matthews:2017:CRF",
  pages =        "452--456",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ACSSC.2017.8335379",
  bibdate =      "Fri Feb 16 08:24:29 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; complex multiply;
                 fused multiply-add; fused-add-add;
                 fused-multiply-twice-and-add; three-sum",
}


bibtype: article
filename: fparith.bib
label: Lee:2017:APC
author: Wonyeol Lee and Rahul Sharma and Alex Aiken
title: On automatically proving the correctness of tt math.h implementations
journal: j-PACMPL
volume: 2
number: {POPL}
pages: 1--32
month: dec
monthnumber: 12
year: 2017
DOI: https://doi.org/10.1145/3158135
ISSN: 2475-1421 OR 24751421
bibdate: Thu May 2 17:03:44 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.05.02 17:03:44 ???
fjournal: Proceedings of the ACM on Programming Languages (PACMPL)
acknowledgement: ack-nhfb
journalURL: http://pacmpl.acm.org/
rawauthor: Wonyeol Lee and Rahul Sharma and Alex Aiken
rawtitle: On automatically proving the correctness of {\tt math.h} implementations
abstract:
Industry standard implementations of tt math.h claim (often without formal proof) tight bounds on floating-point errors. We demonstrate a novel static analysis that proves these bounds and verifies the correctness of these implementations. Our key insight is a reduction of this verification task to a set of mathematical optimization problems that can be solved by off-the-shelf computer algebra systems. We use this analysis to prove the correctness of implementations in Intel's math library automatically. Prior to this work, these implementations could only be verified with significant manual effort

rawabstract:
Industry standard implementations of {\tt math.h} claim (often without formal proof) tight bounds on floating-point errors. We demonstrate a novel static analysis that proves these bounds and verifies the correctness of these implementations. Our key insight is a reduction of this verification task to a set of mathematical optimization problems that can be solved by off-the-shelf computer algebra systems. We use this analysis to prove the correctness of implementations in Intel's math library automatically. Prior to this work, these implementations could only be verified with significant manual effort

entry:
@Article{Lee:2017:APC,
  author =       "Wonyeol Lee and Rahul Sharma and Alex Aiken",
  title =        "On automatically proving the correctness of {\tt
                 math.h} implementations",
  journal =      j-PACMPL,
  volume =       "2",
  number =       "{POPL}",
  pages =        "1--32",
  month =        dec,
  year =         "2017",
  DOI =          "https://doi.org/10.1145/3158135",
  ISSN =         "2475-1421",
  bibdate =      "Thu May 2 17:03:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Industry standard implementations of {\tt math.h}
                 claim (often without formal proof) tight bounds on
                 floating-point errors. We demonstrate a novel static
                 analysis that proves these bounds and verifies the
                 correctness of these implementations. Our key insight
                 is a reduction of this verification task to a set of
                 mathematical optimization problems that can be solved
                 by off-the-shelf computer algebra systems. We use this
                 analysis to prove the correctness of implementations in
                 Intel's math library automatically. Prior to this work,
                 these implementations could only be verified with
                 significant manual effort",
  acknowledgement = ack-nhfb,
  fjournal =     "Proceedings of the ACM on Programming Languages
                 (PACMPL)",
  journal-URL =  "http://pacmpl.acm.org/",
}


bibtype: article
filename: fparith.bib
label: Lefevre:2017:CRA
author: Vincent Lefevre
title: Correctly Rounded Arbitrary-Precision Floating-Point Summation
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2111--2124
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2690632
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7891894/; https://inria.hal.science/hal-01394289
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Vincent Lef{\`e}vre
rawtitle: Correctly Rounded Arbitrary-Precision Floating-Point Summation
entry:
@Article{Lefevre:2017:CRA,
  author =       "Vincent Lef{\`e}vre",
  title =        "Correctly Rounded Arbitrary-Precision Floating-Point
                 Summation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2111--2124",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2690632",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7891894/;
                 https://inria.hal.science/hal-01394289",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Lefevre:2017:OBB
author: Vincent Lefevre and Paul Zimmermann
title: Optimized Binary64 and Binary128 Arithmetic with GNU MPFR
crossref: Burgess:2017:ISC
pages: 18--26
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.28
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/gnu.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre and Paul Zimmermann
rawtitle: Optimized {Binary64} and {Binary128} Arithmetic with {GNU MPFR}
abstract:
We describe algorithms used to optimize the GNU MPFR library when the operands fit into one or two words. On modern processors, this gives a speedup for a correctly rounded addition, subtraction, multiplication, division or square root in the standard binary64 format (resp. binary128) between 1.8 and 3.5 (resp. between 1.6 and 3.2). We also introduce a new faithful rounding mode, which enables even faster computations. Those optimizations will be available in version 4 of MPFR.

keywords:
Approximation algorithms; binary floating-point formats; binary128; binary64; correct rounding; faithful rounding; floating point arithmetic; floating-point arithmetic; GNU MPFR; GNU MPFR library; Libraries; Optimization; optimizations; Program processors; Standards; Timing

rawabstract:
We describe algorithms used to optimize the GNU MPFR library when the operands fit into one or two words. On modern processors, this gives a speedup for a correctly rounded addition, subtraction, multiplication, division or square root in the standard binary64 format (resp. binary128) between 1.8 and 3.5 (resp. between 1.6 and 3.2). We also introduce a new faithful rounding mode, which enables even faster computations. Those optimizations will be available in version 4 of MPFR.

entry:
@InProceedings{Lefevre:2017:OBB,
  author =       "Vincent Lef{\`e}vre and Paul Zimmermann",
  title =        "Optimized {Binary64} and {Binary128} Arithmetic with
                 {GNU MPFR}",
  crossref =     "Burgess:2017:ISC",
  pages =        "18--26",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.28",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib",
  abstract =     "We describe algorithms used to optimize the GNU MPFR
                 library when the operands fit into one or two words. On
                 modern processors, this gives a speedup for a correctly
                 rounded addition, subtraction, multiplication, division
                 or square root in the standard binary64 format (resp.
                 binary128) between 1.8 and 3.5 (resp. between 1.6 and
                 3.2). We also introduce a new faithful rounding mode,
                 which enables even faster computations. Those
                 optimizations will be available in version 4 of MPFR.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; binary floating-point
                 formats; binary128; binary64; correct rounding;
                 faithful rounding; floating point arithmetic;
                 floating-point arithmetic; GNU MPFR; GNU MPFR library;
                 Libraries; Optimization; optimizations; Program
                 processors; Standards; Timing",
}


bibtype: inproceedings
filename: fparith.bib
label: Lesavourey:2017:ELR
author: Andrea Lesavourey and Christophe Negre and Thomas Plantard
title: Efficient Leak Resistant Modular Exponentiation in RNS
crossref: Burgess:2017:ISC
pages: 156--163
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.39
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Andrea Lesavourey and Christophe Negre and Thomas Plantard
rawtitle: Efficient Leak Resistant Modular Exponentiation in {RNS}
abstract:
The leak resistant arithmetic in RNS was introduced in 2004 to randomize RSA modular exponentiation. This randomization is meant to protect implementations on embedded device from side channel analysis. We propose in this paper a faster version of the approach of Bajard et al. in the case of right-to-left square-and-multiply exponentiation. We show that this saves roughly 30% of the computation when the randomization is done at each loop iteration. We also show that the level of randomization of the proposed approach is better than the one of Bajard et al. after a few number of loop iterations.

keywords:
Algorithm design and analysis; Correlation; efficient leak resistant modular exponentiation; embedded device; iterative methods; leak resistant arithmetic; loop iteration; modular exponentiation; Monitoring; Public key cryptography; public key cryptography; public key cryptosystem; randomization; residue number system; residue number systems; Resistance; right-to-left square-and-multiply exponentiation; RNS; RSA; RSA cryptosystem; RSA modular exponentiation randomization; side channel analysis; Xenon

rawabstract:
The leak resistant arithmetic in RNS was introduced in 2004 to randomize RSA modular exponentiation. This randomization is meant to protect implementations on embedded device from side channel analysis. We propose in this paper a faster version of the approach of Bajard et al. in the case of right-to-left square-and-multiply exponentiation. We show that this saves roughly 30\% of the computation when the randomization is done at each loop iteration. We also show that the level of randomization of the proposed approach is better than the one of Bajard et al. after a few number of loop iterations.

entry:
@InProceedings{Lesavourey:2017:ELR,
  author =       "Andrea Lesavourey and Christophe Negre and Thomas
                 Plantard",
  title =        "Efficient Leak Resistant Modular Exponentiation in
                 {RNS}",
  crossref =     "Burgess:2017:ISC",
  pages =        "156--163",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.39",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The leak resistant arithmetic in RNS was introduced in
                 2004 to randomize RSA modular exponentiation. This
                 randomization is meant to protect implementations on
                 embedded device from side channel analysis. We propose
                 in this paper a faster version of the approach of
                 Bajard et al. in the case of right-to-left
                 square-and-multiply exponentiation. We show that this
                 saves roughly 30\% of the computation when the
                 randomization is done at each loop iteration. We also
                 show that the level of randomization of the proposed
                 approach is better than the one of Bajard et al. after
                 a few number of loop iterations.",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; Correlation; efficient
                 leak resistant modular exponentiation; embedded device;
                 iterative methods; leak resistant arithmetic; loop
                 iteration; modular exponentiation; Monitoring; Public
                 key cryptography; public key cryptography; public key
                 cryptosystem; randomization; residue number system;
                 residue number systems; Resistance; right-to-left
                 square-and-multiply exponentiation; RNS; RSA; RSA
                 cryptosystem; RSA modular exponentiation randomization;
                 side channel analysis; Xenon",
}


bibtype: article
filename: fparith.bib
label: Li:2017:MFN
author: Yin Li and Xingpo Ma and Yu Zhang and Chuanda Qi
title: Mastrovito Form of Non-Recursive Karatsuba Multiplier for All Trinomials
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 9
pages: 1573--1584
month: sep
monthnumber: 9
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2677913
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Aug 17 10:06:38 MDT 2017
bibtimestamp: 2017.08.17 10:06:38 MDT
URL: http://ieeexplore.ieee.org/document/7870679/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Yin Li and Xingpo Ma and Yu Zhang and Chuanda Qi
rawtitle: {Mastrovito} Form of Non-Recursive {Karatsuba} Multiplier for All Trinomials
entry:
@Article{Li:2017:MFN,
  author =       "Yin Li and Xingpo Ma and Yu Zhang and Chuanda Qi",
  title =        "{Mastrovito} Form of Non-Recursive {Karatsuba}
                 Multiplier for All Trinomials",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "9",
  pages =        "1573--1584",
  month =        sep,
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2677913",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Aug 17 10:06:38 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7870679/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Liu:2017:DAR
author: Weiqiang Liu and Liangyu Qian and Chenghua Wang and Honglan Jiang and Jie Han and Fabrizio Lombardi
title: Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 8
pages: 1435--1441
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2672976
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 13 14:57:15 MDT 2017
bibtimestamp: 2017.07.13 14:57:15 MDT
URL: http://ieeexplore.ieee.org/document/7862783/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Weiqiang Liu and Liangyu Qian and Chenghua Wang and Honglan Jiang and Jie Han and Fabrizio Lombardi
rawtitle: Design of Approximate Radix-4 {Booth} Multipliers for Error-Tolerant Computing
entry:
@Article{Liu:2017:DAR,
  author =       "Weiqiang Liu and Liangyu Qian and Chenghua Wang and
                 Honglan Jiang and Jie Han and Fabrizio Lombardi",
  title =        "Design of Approximate Radix-4 {Booth} Multipliers for
                 Error-Tolerant Computing",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "8",
  pages =        "1435--1441",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2672976",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 13 14:57:15 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7862783/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Liu:2017:MMA
author: Zhe Liu and Kimmo Jarvinen and Weiqiang Liu and Hwajeong Seo
title: Multiprecision Multiplication on ARMv8
crossref: Burgess:2017:ISC
pages: 10--17
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.27
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Zhe Liu and Kimmo J{\"a}rvinen and Weiqiang Liu and Hwajeong Seo
rawtitle: Multiprecision Multiplication on {ARMv8}
abstract:
Multiplication of large integers is a fundamental operation for public key cryptography. In contemporary public key cryptography, the sizes of integers are typically from more than one hundred bits to even several thousands of bits. Because these sizes exceed the bit widths of all general-purpose processors, these multiplications must be performed with a multiprecision multiplication algorithm which splits the operation into multiple partial products and accumulation steps. To ensure efficiency, multiprecision multiplication algorithms must be designed with special care and optimized for the instruction sets of specific processors. Consequently, developing efficient multiprecision multiplication algorithms and optimizing them for specific platforms has been an active research topic. In this paper, we optimize multiprecision multiplication and squaring specifically for the 64-bit ARMv8 processors which are widely used, for example, in modern smart phones and tablets. We combine the subtractive Karatsuba algorithm, operand-scanning techniques (for multiplication) and sliding-block-doubling methods (for squaring) to accelerate the performance of the 256-bit multiprecision multiplication and squaring by 7.6% and 7.0% compared to the OpenSSL implementations. We focus particularly on the multiprecision multiplications that are required in elliptic curve cryptography. Our implementation supports general elliptic curves of various sizes and all source codes are available in public domain.

keywords:
64-bit processor; ARMv8; ARMv8 processors; elliptic curve cryptography; Elliptic curve cryptography; elliptic curve cryptography; Instruction sets; Karatsuba algorithm; microprocessor chips; Multiprecision multiplication; multiprecision multiplication algorithm; OpenSSL; operand-scanning techniques; Optimization; public key cryptography; Registers; sliding-block-doubling methods

rawabstract:
Multiplication of large integers is a fundamental operation for public key cryptography. In contemporary public key cryptography, the sizes of integers are typically from more than one hundred bits to even several thousands of bits. Because these sizes exceed the bit widths of all general-purpose processors, these multiplications must be performed with a multiprecision multiplication algorithm which splits the operation into multiple partial products and accumulation steps. To ensure efficiency, multiprecision multiplication algorithms must be designed with special care and optimized for the instruction sets of specific processors. Consequently, developing efficient multiprecision multiplication algorithms and optimizing them for specific platforms has been an active research topic. In this paper, we optimize multiprecision multiplication and squaring specifically for the 64-bit ARMv8 processors which are widely used, for example, in modern smart phones and tablets. We combine the subtractive Karatsuba algorithm, operand-scanning techniques (for multiplication) and sliding-block-doubling methods (for squaring) to accelerate the performance of the 256-bit multiprecision multiplication and squaring by 7.6\% and 7.0\% compared to the OpenSSL implementations. We focus particularly on the multiprecision multiplications that are required in elliptic curve cryptography. Our implementation supports general elliptic curves of various sizes and all source codes are available in public domain.

entry:
@InProceedings{Liu:2017:MMA,
  author =       "Zhe Liu and Kimmo J{\"a}rvinen and Weiqiang Liu and
                 Hwajeong Seo",
  title =        "Multiprecision Multiplication on {ARMv8}",
  crossref =     "Burgess:2017:ISC",
  pages =        "10--17",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.27",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Multiplication of large integers is a fundamental
                 operation for public key cryptography. In contemporary
                 public key cryptography, the sizes of integers are
                 typically from more than one hundred bits to even
                 several thousands of bits. Because these sizes exceed
                 the bit widths of all general-purpose processors, these
                 multiplications must be performed with a multiprecision
                 multiplication algorithm which splits the operation
                 into multiple partial products and accumulation steps.
                 To ensure efficiency, multiprecision multiplication
                 algorithms must be designed with special care and
                 optimized for the instruction sets of specific
                 processors. Consequently, developing efficient
                 multiprecision multiplication algorithms and optimizing
                 them for specific platforms has been an active research
                 topic. In this paper, we optimize multiprecision
                 multiplication and squaring specifically for the 64-bit
                 ARMv8 processors which are widely used, for example, in
                 modern smart phones and tablets. We combine the
                 subtractive Karatsuba algorithm, operand-scanning
                 techniques (for multiplication) and
                 sliding-block-doubling methods (for squaring) to
                 accelerate the performance of the 256-bit
                 multiprecision multiplication and squaring by 7.6\% and
                 7.0\% compared to the OpenSSL implementations. We focus
                 particularly on the multiprecision multiplications that
                 are required in elliptic curve cryptography. Our
                 implementation supports general elliptic curves of
                 various sizes and all source codes are available in
                 public domain.",
  acknowledgement = ack-nhfb,
  keywords =     "64-bit processor; ARMv8; ARMv8 processors; elliptic
                 curve cryptography; Elliptic curve cryptography;
                 elliptic curve cryptography; Instruction sets;
                 Karatsuba algorithm; microprocessor chips;
                 Multiprecision multiplication; multiprecision
                 multiplication algorithm; OpenSSL; operand-scanning
                 techniques; Optimization; public key cryptography;
                 Registers; sliding-block-doubling methods",
}


bibtype: article
filename: fparith.bib
label: Liu:2017:UMF
author: S. Liu and G. Mingas and C. S. Bouganis
title: An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 5
pages: 745--758
month: may
monthnumber: 5
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2016.2630682
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Apr 6 07:46:06 2017
bibtimestamp: 2017.04.06 07:46:06 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Liu and G. Mingas and C. S. Bouganis
rawtitle: An Unbiased {MCMC} {FPGA}-Based Accelerator in the Land of Custom Precision Arithmetic
keywords:
Approximation algorithms; Bayes methods; Computational modeling; custom arithmetic precision; Field programmable gate array; Field programmable gate arrays; logistic regression; Markov chain Monte Carlo; Markov processes; MNIST database; Monte Carlo methods; Probability distribution

entry:
@Article{Liu:2017:UMF,
  author =       "S. Liu and G. Mingas and C. S. Bouganis",
  title =        "An Unbiased {MCMC} {FPGA}-Based Accelerator in the
                 Land of Custom Precision Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "5",
  pages =        "745--758",
  month =        may,
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2016.2630682",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Apr 6 07:46:06 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Approximation algorithms; Bayes methods; Computational
                 modeling; custom arithmetic precision; Field
                 programmable gate array; Field programmable gate
                 arrays; logistic regression; Markov chain Monte Carlo;
                 Markov processes; MNIST database; Monte Carlo methods;
                 Probability distribution",
}


bibtype: book
filename: fparith.bib
label: Lockhart:2017:A
author: Paul Lockhart
title: Arithmetic
publisher: The Belknap Press of Harvard University Press
address: Cambridge, MA, USA
pages: 223
year: 2017
ISBN: 0-674-97223-6 OR 0674972236
ISBN13: 978-0-674-97223-0 OR 9780674972230
LCCN: QA115 .L713 2017
bibdate: Sat Dec 22 16:04:02 MST 2018
bibtimestamp: 2018.12.22 16:04:02 MST
subject: Talteori; Arithmetic; History
acknowledgement: ack-nhfb
rawauthor: Paul Lockhart
rawtitle: Arithmetic
bibsource:
fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib

abstract:
Educator Paul Lockhart's goal is to demystify arithmetic: to bring the subject to life in a fun and accessible way, and to reveal its profound and simple beauty, as seen through the eyes of a modern research mathematician. The craft of arithmetic arises from our natural desire to count, arrange, and compare quantities. Over the centuries, humans have devised a wide variety of strategies for representing and manipulating numerical information: tally marks, rocks and beads, marked-value and place-value systems, as well as mechanical and electronic calculators. booktitle Arithmetic traces the history and development of these various number languages and calculating devices and examines their comparative advantages and disadvantages, providing readers with an opportunity to develop not only their computational skills but also their own personal tastes and preferences. The book is neither a training manual nor an authoritative history, but rather an entertaining survey of ideas and methods for the reader to enjoy and appreciate. Written in a lively conversational style, booktitle Arithmetic is a fun and engaging introduction to both practical techniques as well as the more abstract mathematical aspects of the subject.

TOC:
Dear Reader / vii Things / 1 Language / 5 Repetition / 10 Tribes / 15 Egypt / 25 Rome / 32 China and Japan / 41 India / 48 Europe / 75 Multiplication / 87 Division / 117 Machines / 136 Fractions / 151 Negative numbers / 180 The art of counting / 197 Afterword / 215 Index / 217

rawabstract:
Educator Paul Lockhart's goal is to demystify arithmetic: to bring the subject to life in a fun and accessible way, and to reveal its profound and simple beauty, as seen through the eyes of a modern research mathematician. The craft of arithmetic arises from our natural desire to count, arrange, and compare quantities. Over the centuries, humans have devised a wide variety of strategies for representing and manipulating numerical information: tally marks, rocks and beads, marked-value and place-value systems, as well as mechanical and electronic calculators. \booktitle{Arithmetic} traces the history and development of these various number languages and calculating devices and examines their comparative advantages and disadvantages, providing readers with an opportunity to develop not only their computational skills but also their own personal tastes and preferences. The book is neither a training manual nor an authoritative history, but rather an entertaining survey of ideas and methods for the reader to enjoy and appreciate. Written in a lively conversational style, \booktitle{Arithmetic} is a fun and engaging introduction to both practical techniques as well as the more abstract mathematical aspects of the subject.

rawTOC:
Dear Reader / vii \\ Things / 1 \\ Language / 5 \\ Repetition / 10 \\ Tribes / 15 \\ Egypt / 25 \\ Rome / 32 \\ China and Japan / 41 \\ India / 48 \\ Europe / 75 \\ Multiplication / 87 \\ Division / 117 \\ Machines / 136 \\ Fractions / 151 \\ Negative numbers / 180 \\ The art of counting / 197 \\ Afterword / 215 \\ Index / 217

entry:
@Book{Lockhart:2017:A,
  author =       "Paul Lockhart",
  title =        "Arithmetic",
  publisher =    "The Belknap Press of Harvard University Press",
  address =      "Cambridge, MA, USA",
  pages =        "223",
  year =         "2017",
  ISBN =         "0-674-97223-6",
  ISBN-13 =      "978-0-674-97223-0",
  LCCN =         "QA115 .L713 2017",
  bibdate =      "Sat Dec 22 16:04:02 MST 2018",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib",
  abstract =     "Educator Paul Lockhart's goal is to demystify
                 arithmetic: to bring the subject to life in a fun and
                 accessible way, and to reveal its profound and simple
                 beauty, as seen through the eyes of a modern research
                 mathematician. The craft of arithmetic arises from our
                 natural desire to count, arrange, and compare
                 quantities. Over the centuries, humans have devised a
                 wide variety of strategies for representing and
                 manipulating numerical information: tally marks, rocks
                 and beads, marked-value and place-value systems, as
                 well as mechanical and electronic calculators.
                 \booktitle{Arithmetic} traces the history and
                 development of these various number languages and
                 calculating devices and examines their comparative
                 advantages and disadvantages, providing readers with an
                 opportunity to develop not only their computational
                 skills but also their own personal tastes and
                 preferences. The book is neither a training manual nor
                 an authoritative history, but rather an entertaining
                 survey of ideas and methods for the reader to enjoy and
                 appreciate. Written in a lively conversational style,
                 \booktitle{Arithmetic} is a fun and engaging
                 introduction to both practical techniques as well as
                 the more abstract mathematical aspects of the
                 subject.",
  acknowledgement = ack-nhfb,
  subject =      "Talteori; Arithmetic; History",
  tableofcontents = "Dear Reader / vii \\
                 Things / 1 \\
                 Language / 5 \\
                 Repetition / 10 \\
                 Tribes / 15 \\
                 Egypt / 25 \\
                 Rome / 32 \\
                 China and Japan / 41 \\
                 India / 48 \\
                 Europe / 75 \\
                 Multiplication / 87 \\
                 Division / 117 \\
                 Machines / 136 \\
                 Fractions / 151 \\
                 Negative numbers / 180 \\
                 The art of counting / 197 \\
                 Afterword / 215 \\
                 Index / 217",
}


bibtype: inproceedings
filename: fparith.bib
label: Lutz:2017:HPA
author: David Raymond Lutz and Christopher Neal Hinds
title: High-Precision Anchored Accumulators for Reproducible Floating-Point Summation
crossref: Burgess:2017:ISC
pages: 98--105
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.20
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: David Raymond Lutz and Christopher Neal Hinds
rawtitle: High-Precision Anchored Accumulators for Reproducible Floating-Point Summation
abstract:
This paper introduces a new datatype that allows reproducible accumulation of floating-point (FP) numbers in a programmer-selectable range. The new datatype has a larger significand and a smaller range than existing FP formats and has much better arithmetic and computational properties. In particular, it is associative, parallelizable, reproducible and correct. For the modest ranges that will accommodate most problems, it is also much faster: 3 to 12 times faster on a single 256-bit SIMD implementation. The paper also describes a new instruction and associated datapath that support the proposed datatype, and discusses how a recently published software algorithm for reproducible FP summation could be implemented using the proposed approach.

keywords:
accurate floating-point summation; arithmetic properties; computational properties; Digital arithmetic; floating point arithmetic; Floating-point; floating-point summation; Hardware; high-precision; high-precision anchored accumulators; Indexes; Limiting; Metadata; parallel processing; programmer-selectable range; Redundancy; Registers; reproducibility; SIMD; software algorithm

rawabstract:
This paper introduces a new datatype that allows reproducible accumulation of floating-point (FP) numbers in a programmer-selectable range. The new datatype has a larger significand and a smaller range than existing FP formats and has much better arithmetic and computational properties. In particular, it is associative, parallelizable, reproducible and correct. For the modest ranges that will accommodate most problems, it is also much faster: 3 to 12 times faster on a single 256-bit SIMD implementation. The paper also describes a new instruction and associated datapath that support the proposed datatype, and discusses how a recently published software algorithm for reproducible FP summation could be implemented using the proposed approach.

entry:
@InProceedings{Lutz:2017:HPA,
  author =       "David Raymond Lutz and Christopher Neal Hinds",
  title =        "High-Precision Anchored Accumulators for Reproducible
                 Floating-Point Summation",
  crossref =     "Burgess:2017:ISC",
  pages =        "98--105",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.20",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper introduces a new datatype that allows
                 reproducible accumulation of floating-point (FP)
                 numbers in a programmer-selectable range. The new
                 datatype has a larger significand and a smaller range
                 than existing FP formats and has much better arithmetic
                 and computational properties. In particular, it is
                 associative, parallelizable, reproducible and correct.
                 For the modest ranges that will accommodate most
                 problems, it is also much faster: 3 to 12 times faster
                 on a single 256-bit SIMD implementation. The paper also
                 describes a new instruction and associated datapath
                 that support the proposed datatype, and discusses how a
                 recently published software algorithm for reproducible
                 FP summation could be implemented using the proposed
                 approach.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; arithmetic
                 properties; computational properties; Digital
                 arithmetic; floating point arithmetic; Floating-point;
                 floating-point summation; Hardware; high-precision;
                 high-precision anchored accumulators; Indexes;
                 Limiting; Metadata; parallel processing;
                 programmer-selectable range; Redundancy; Registers;
                 reproducibility; SIMD; software algorithm",
}


bibtype: article
filename: fparith.bib
label: Magron:2017:CRE
author: Victor Magron and George Constantinides and Alastair Donaldson
title: Certified Roundoff Error Bounds Using Semidefinite Programming
journal: j-TOMS
volume: 43
number: 4
pages: 34:1--34:31
month: mar
monthnumber: 3
year: 2017
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3015465
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Mar 24 08:51:05 MDT 2017
bibtimestamp: 2017.03.24 08:51:05 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 34
journalURL: https://dl.acm.org/loi/toms
rawauthor: Victor Magron and George Constantinides and Alastair Donaldson
rawtitle: Certified Roundoff Error Bounds Using Semidefinite Programming
abstract:
Roundoff errors cannot be avoided when implementing numerical programs with finite precision. The ability to reason about rounding is especially important if one wants to explore a range of potential representations, for instance, for FPGAs or custom hardware implementations. This problem becomes challenging when the program does not employ solely linear operations as non-linearities are inherent to many interesting computational problems in real-world applications. Existing solutions to reasoning possibly lead to either inaccurate bounds or high analysis time in the presence of nonlinear correlations between variables. Furthermore, while it is easy to implement a straightforward method such as interval arithmetic, sophisticated techniques are less straightforward to implement in a formal setting. Thus there is a need for methods that output certificates that can be formally validated inside a proof assistant. We present a framework to provide upper bounds on absolute roundoff errors of floating-point nonlinear programs. This framework is based on optimization techniques employing semidefinite programming and sums of squares certificates, which can be checked inside the Coq theorem prover to provide formal roundoff error bounds for polynomial programs. Our tool covers a wide range of nonlinear programs, including polynomials and transcendental operations as well as conditional statements. We illustrate the efficiency and precision of this tool on non-trivial programs coming from biology, optimization, and space control. Our tool produces more accurate error bounds for 23% of all programs and yields better performance in 66% of all programs.

rawabstract:
Roundoff errors cannot be avoided when implementing numerical programs with finite precision. The ability to reason about rounding is especially important if one wants to explore a range of potential representations, for instance, for FPGAs or custom hardware implementations. This problem becomes challenging when the program does not employ solely linear operations as non-linearities are inherent to many interesting computational problems in real-world applications. Existing solutions to reasoning possibly lead to either inaccurate bounds or high analysis time in the presence of nonlinear correlations between variables. Furthermore, while it is easy to implement a straightforward method such as interval arithmetic, sophisticated techniques are less straightforward to implement in a formal setting. Thus there is a need for methods that output certificates that can be formally validated inside a proof assistant. We present a framework to provide upper bounds on absolute roundoff errors of floating-point nonlinear programs. This framework is based on optimization techniques employing semidefinite programming and sums of squares certificates, which can be checked inside the Coq theorem prover to provide formal roundoff error bounds for polynomial programs. Our tool covers a wide range of nonlinear programs, including polynomials and transcendental operations as well as conditional statements. We illustrate the efficiency and precision of this tool on non-trivial programs coming from biology, optimization, and space control. Our tool produces more accurate error bounds for 23\% of all programs and yields better performance in 66\% of all programs.

entry:
@Article{Magron:2017:CRE,
  author =       "Victor Magron and George Constantinides and Alastair
                 Donaldson",
  title =        "Certified Roundoff Error Bounds Using Semidefinite
                 Programming",
  journal =      j-TOMS,
  volume =       "43",
  number =       "4",
  pages =        "34:1--34:31",
  month =        mar,
  year =         "2017",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3015465",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Mar 24 08:51:05 MDT 2017",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  abstract =     "Roundoff errors cannot be avoided when implementing
                 numerical programs with finite precision. The ability
                 to reason about rounding is especially important if one
                 wants to explore a range of potential representations,
                 for instance, for FPGAs or custom hardware
                 implementations. This problem becomes challenging when
                 the program does not employ solely linear operations as
                 non-linearities are inherent to many interesting
                 computational problems in real-world applications.
                 Existing solutions to reasoning possibly lead to either
                 inaccurate bounds or high analysis time in the presence
                 of nonlinear correlations between variables.
                 Furthermore, while it is easy to implement a
                 straightforward method such as interval arithmetic,
                 sophisticated techniques are less straightforward to
                 implement in a formal setting. Thus there is a need for
                 methods that output certificates that can be formally
                 validated inside a proof assistant. We present a
                 framework to provide upper bounds on absolute roundoff
                 errors of floating-point nonlinear programs. This
                 framework is based on optimization techniques employing
                 semidefinite programming and sums of squares
                 certificates, which can be checked inside the Coq
                 theorem prover to provide formal roundoff error bounds
                 for polynomial programs. Our tool covers a wide range
                 of nonlinear programs, including polynomials and
                 transcendental operations as well as conditional
                 statements. We illustrate the efficiency and precision
                 of this tool on non-trivial programs coming from
                 biology, optimization, and space control. Our tool
                 produces more accurate error bounds for 23\% of all
                 programs and yields better performance in 66\% of all
                 programs.",
  acknowledgement = ack-nhfb,
  articleno =    "34",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: inproceedings
filename: fparith.bib
label: Malaya:2017:AMP
author: Nicholas Malaya and Shuai Che and Joseph L. Greathouse and Rene van Oostrum and Michael J. Schulte
title: Accelerating Matrix Processing with GPUs
crossref: Burgess:2017:ISC
pages: 139--141
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.14
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Nicholas Malaya and Shuai Che and Joseph L. Greathouse and Rene van Oostrum and Michael J. Schulte
rawtitle: Accelerating Matrix Processing with {GPUs}
abstract:
Matrix operations are common and expensive computations in a variety of applications. They occur frequently in high-performance computing, graphics, graph processing, and machine learning applications. This paper discusses how to map a variety of important matrix computations, including sparse matrix-vector multiplication (SpMV), sparse triangle solve (SpTS), graph processing, and dense matrix-matrix multiplication, to GPUs. Since many emerging systems will use heterogeneous architectures (e.g. CPUs and GPUs) to attain the desired performance targets under strict power constraints, this paper discusses implications and future research for matrix processing with heterogeneous designs. Conclusions common to the matrix operations discussed in this paper are: (1) Future algorithms should be written to ensure that the essential computations fit into local memory, which may require direct programmer management. (2) Algorithms are needed that expose high levels of parallelism. (3) While the scale of computation is often sufficient to support algorithms with superior asymptotic order, additional considerations, such as memory capacity and bandwidth, must also be carefully managed. (4) Libraries should be used to provide portable performance.

keywords:
Algorithm design and analysis; dense matrix-matrix multiplication; exascale; GPGPU; GPU; Graph Algorithms; graph processing; graphics processing units; Graphics processing units; Libraries; Linear algebra; matrix computations; matrix multiplication; matrix processing; Matrix-matrix multiplication; Memory management; Parallel processing; Sparse matrices; sparse matrices; sparse matrix-vector multiplication; sparse triangle solve; SpMV; SpTS

rawabstract:
Matrix operations are common and expensive computations in a variety of applications. They occur frequently in high-performance computing, graphics, graph processing, and machine learning applications. This paper discusses how to map a variety of important matrix computations, including sparse matrix-vector multiplication (SpMV), sparse triangle solve (SpTS), graph processing, and dense matrix-matrix multiplication, to GPUs. Since many emerging systems will use heterogeneous architectures (e.g. CPUs and GPUs) to attain the desired performance targets under strict power constraints, this paper discusses implications and future research for matrix processing with heterogeneous designs. Conclusions common to the matrix operations discussed in this paper are: (1) Future algorithms should be written to ensure that the essential computations fit into local memory, which may require direct programmer management. (2) Algorithms are needed that expose high levels of parallelism. (3) While the scale of computation is often sufficient to support algorithms with superior asymptotic order, additional considerations, such as memory capacity and bandwidth, must also be carefully managed. (4) Libraries should be used to provide portable performance.

entry:
@InProceedings{Malaya:2017:AMP,
  author =       "Nicholas Malaya and Shuai Che and Joseph L. Greathouse
                 and Rene van Oostrum and Michael J. Schulte",
  title =        "Accelerating Matrix Processing with {GPUs}",
  crossref =     "Burgess:2017:ISC",
  pages =        "139--141",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.14",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Matrix operations are common and expensive
                 computations in a variety of applications. They occur
                 frequently in high-performance computing, graphics,
                 graph processing, and machine learning applications.
                 This paper discusses how to map a variety of important
                 matrix computations, including sparse matrix-vector
                 multiplication (SpMV), sparse triangle solve (SpTS),
                 graph processing, and dense matrix-matrix
                 multiplication, to GPUs. Since many emerging systems
                 will use heterogeneous architectures (e.g. CPUs and
                 GPUs) to attain the desired performance targets under
                 strict power constraints, this paper discusses
                 implications and future research for matrix processing
                 with heterogeneous designs. Conclusions common to the
                 matrix operations discussed in this paper are: (1)
                 Future algorithms should be written to ensure that the
                 essential computations fit into local memory, which may
                 require direct programmer management. (2) Algorithms
                 are needed that expose high levels of parallelism. (3)
                 While the scale of computation is often sufficient to
                 support algorithms with superior asymptotic order,
                 additional considerations, such as memory capacity and
                 bandwidth, must also be carefully managed. (4)
                 Libraries should be used to provide portable
                 performance.",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; dense matrix-matrix
                 multiplication; exascale; GPGPU; GPU; Graph Algorithms;
                 graph processing; graphics processing units; Graphics
                 processing units; Libraries; Linear algebra; matrix
                 computations; matrix multiplication; matrix processing;
                 Matrix-matrix multiplication; Memory management;
                 Parallel processing; Sparse matrices; sparse matrices;
                 sparse matrix-vector multiplication; sparse triangle
                 solve; SpMV; SpTS",
}


bibtype: article
filename: fparith.bib
label: Martins:2017:AIR
author: Paulo Martins and Julien Eynard and Jean-Claude Bajard and Leonel Sousa
title: Arithmetical Improvement of the Round-Off for Cryptosystems in High-Dimensional Lattices
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2005--2018
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2690420
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7891511/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Paulo Martins and Julien Eynard and Jean-Claude Bajard and Leonel Sousa
rawtitle: Arithmetical Improvement of the Round-Off for Cryptosystems in High-Dimensional Lattices
entry:
@Article{Martins:2017:AIR,
  author =       "Paulo Martins and Julien Eynard and Jean-Claude Bajard
                 and Leonel Sousa",
  title =        "Arithmetical Improvement of the Round-Off for
                 Cryptosystems in High-Dimensional Lattices",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2005--2018",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2690420",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7891511/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Mascarenhas:2017:ERE
author: Walter F. Mascarenhas and Andre Pierro de Camargo
title: The effects of rounding errors in the nodes on barycentric interpolation
journal: j-NUM-MATH
volume: 135
number: 1
pages: 113--141
month: jan
monthnumber: 1
year: 2017
CODEN: NUMMA7
DOI: https://doi.org/10.1007/s00211-016-0798-x
ISSN: 0029-599X (print), 0945-3245 (electronic) OR 0029599X (print), 09453245 (electronic)
ISSNL: 0029-599X OR 0029599X
bibdate: Sat Feb 18 08:20:07 MST 2017
bibtimestamp: 2017.02.18 08:20:07 MST
fjournal: Numerische Mathematik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/211
rawauthor: Walter F. Mascarenhas and Andr{\'e} Pierro de Camargo
rawtitle: The effects of rounding errors in the nodes on barycentric interpolation
bibsource:
http://link.springer.com/journal/211/135/1; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/nummath2010.bib

URL:
http://link.springer.com/accesspage/article/10.1007/s00211-016-0798-x; http://link.springer.com/article/10.1007/s00211-016-0798-x

entry:
@Article{Mascarenhas:2017:ERE,
  author =       "Walter F. Mascarenhas and Andr{\'e} Pierro de
                 Camargo",
  title =        "The effects of rounding errors in the nodes on
                 barycentric interpolation",
  journal =      j-NUM-MATH,
  volume =       "135",
  number =       "1",
  pages =        "113--141",
  month =        jan,
  year =         "2017",
  CODEN =        "NUMMA7",
  DOI =          "https://doi.org/10.1007/s00211-016-0798-x",
  ISSN =         "0029-599X (print), 0945-3245 (electronic)",
  ISSN-L =       "0029-599X",
  bibdate =      "Sat Feb 18 08:20:07 MST 2017",
  bibsource =    "http://link.springer.com/journal/211/135/1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/nummath2010.bib",
  URL =          "http://link.springer.com/accesspage/article/10.1007/s00211-016-0798-x;
                 http://link.springer.com/article/10.1007/s00211-016-0798-x",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerische Mathematik",
  journal-URL =  "http://link.springer.com/journal/211",
}


bibtype: article
filename: fparith.bib
label: Mazahir:2017:PEA
author: Sana Mazahir and Osman Hasan and Rehan Hafiz and Muhammad Shafique
title: Probabilistic Error Analysis of Approximate Recursive Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 11
pages: 1982--1990
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2709542
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Oct 12 06:36:58 MDT 2017
bibtimestamp: 2017.10.12 06:36:58 MDT
URL: http://ieeexplore.ieee.org/document/7935435/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sana Mazahir and Osman Hasan and Rehan Hafiz and Muhammad Shafique
rawtitle: Probabilistic Error Analysis of Approximate Recursive Multipliers
entry:
@Article{Mazahir:2017:PEA,
  author =       "Sana Mazahir and Osman Hasan and Rehan Hafiz and
                 Muhammad Shafique",
  title =        "Probabilistic Error Analysis of Approximate Recursive
                 Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "11",
  pages =        "1982--1990",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2709542",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Oct 12 06:36:58 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7935435/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Medhat:2017:MPE
title: Managing the Performance / Error Tradeoff of Floating-point Intensive Applications
journal: j-TECS
volume: 16
number: 5s
pages: 184:1--184:??
month: oct
monthnumber: 10
year: 2017
DOI: https://doi.org/10.1145/3126519
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Oct 17 18:16:33 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2019.10.17 18:16:33 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 184
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J840
rawtitle: Managing the Performance\slash Error Tradeoff of Floating-point Intensive Applications
author:
Ramy Medhat and Michael O. Lam and Barry L. Rountree and Borzoo Bonakdarpour and Sebastian Fischmeister

abstract:
Modern embedded systems are becoming more reliant on real-valued arithmetic as they employ mathematically complex vision algorithms and sensor signal processing. Double-precision floating point is the most commonly used precision in computer vision algorithm implementations. A single-precision floating point can provide a performance boost due to less memory transfers, less cache occupancy, and relatively faster mathematical operations on some architectures. However, adopting it can result in loss of accuracy. Identifying which parts of the program can run in single-precision floating point with low impact on error is a manual and tedious process. In this paper, we propose an automatic approach to identify parts of the program that have a low impact on error using shadow-value analysis. Our approach provides the user with a performance/error tradeoff, using which the user can decide how much accuracy can be sacrificed in return for performance improvement. We illustrate the impact of the approach using a well known implementation of Apriltag detection used in robotics vision. We demonstrate that an average 1.3x speedup can be achieved with no impact on tag detection, and a 1.7x speedup with only 4% false negatives.

rawabstract:
Modern embedded systems are becoming more reliant on real-valued arithmetic as they employ mathematically complex vision algorithms and sensor signal processing. Double-precision floating point is the most commonly used precision in computer vision algorithm implementations. A single-precision floating point can provide a performance boost due to less memory transfers, less cache occupancy, and relatively faster mathematical operations on some architectures. However, adopting it can result in loss of accuracy. Identifying which parts of the program can run in single-precision floating point with low impact on error is a manual and tedious process. In this paper, we propose an automatic approach to identify parts of the program that have a low impact on error using shadow-value analysis. Our approach provides the user with a performance/error tradeoff, using which the user can decide how much accuracy can be sacrificed in return for performance improvement. We illustrate the impact of the approach using a well known implementation of Apriltag detection used in robotics vision. We demonstrate that an average 1.3x speedup can be achieved with no impact on tag detection, and a 1.7x speedup with only 4\% false negatives.

rawauthor:
Ramy Medhat and Michael O. Lam and Barry L. Rountree and Borzoo Bonakdarpour and Sebastian Fischmeister

entry:
@Article{Medhat:2017:MPE,
  author =       "Ramy Medhat and Michael O. Lam and Barry L. Rountree
                 and Borzoo Bonakdarpour and Sebastian Fischmeister",
  title =        "Managing the Performance\slash Error Tradeoff of
                 Floating-point Intensive Applications",
  journal =      j-TECS,
  volume =       "16",
  number =       "5s",
  pages =        "184:1--184:??",
  month =        oct,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3126519",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Oct 17 18:16:33 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  abstract =     "Modern embedded systems are becoming more reliant on
                 real-valued arithmetic as they employ mathematically
                 complex vision algorithms and sensor signal processing.
                 Double-precision floating point is the most commonly
                 used precision in computer vision algorithm
                 implementations. A single-precision floating point can
                 provide a performance boost due to less memory
                 transfers, less cache occupancy, and relatively faster
                 mathematical operations on some architectures. However,
                 adopting it can result in loss of accuracy. Identifying
                 which parts of the program can run in single-precision
                 floating point with low impact on error is a manual and
                 tedious process. In this paper, we propose an automatic
                 approach to identify parts of the program that have a
                 low impact on error using shadow-value analysis. Our
                 approach provides the user with a performance/error
                 tradeoff, using which the user can decide how much
                 accuracy can be sacrificed in return for performance
                 improvement. We illustrate the impact of the approach
                 using a well known implementation of Apriltag detection
                 used in robotics vision. We demonstrate that an average
                 1.3x speedup can be achieved with no impact on tag
                 detection, and a 1.7x speedup with only 4\% false
                 negatives.",
  acknowledgement = ack-nhfb,
  articleno =    "184",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J840",
}


bibtype: article
filename: fparith.bib
label: Merchant:2017:ABL
author: Farhad Merchant and Anupam Chattopadhyay and Soumyendu Raha and S. K. Nandy and Ranjani Narayan
title: Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design
journal: j-PARALLEL-PROCESS-LETT
volume: 27
number: 3--4
pages: 1750006
year: 2017
CODEN: PPLTEE
DOI: https://doi.org/10.1142/S0129626417500062
ISSN: 0129-6264 (print), 1793-642X (electronic) OR 01296264 (print), 1793642X (electronic)
ISSNL: 0129-6264 OR 01296264
bibdate: Tue May 29 09:05:31 MDT 2018
bibtimestamp: 2018.05.29 09:05:31 MDT
fjournal: Parallel Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.worldscientific.com/loi/ppl
rawauthor: Farhad Merchant and Anupam Chattopadhyay and Soumyendu Raha and S. K. Nandy and Ranjani Narayan
rawtitle: Accelerating {BLAS} and {LAPACK} via Efficient Floating Point Architecture Design
bibsource:
http://ejournals.wspc.com.sg/ppl/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/parallelprocesslett.bib

entry:
@Article{Merchant:2017:ABL,
  author =       "Farhad Merchant and Anupam Chattopadhyay and Soumyendu
                 Raha and S. K. Nandy and Ranjani Narayan",
  title =        "Accelerating {BLAS} and {LAPACK} via Efficient
                 Floating Point Architecture Design",
  journal =      j-PARALLEL-PROCESS-LETT,
  volume =       "27",
  number =       "3--4",
  pages =        "1750006",
  year =         "2017",
  CODEN =        "PPLTEE",
  DOI =          "https://doi.org/10.1142/S0129626417500062",
  ISSN =         "0129-6264 (print), 1793-642X (electronic)",
  ISSN-L =       "0129-6264",
  bibdate =      "Tue May 29 09:05:31 MDT 2018",
  bibsource =    "http://ejournals.wspc.com.sg/ppl/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/parallelprocesslett.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Parallel Processing Letters",
  journal-URL =  "http://www.worldscientific.com/loi/ppl",
}


bibtype: mastersthesis
filename: fparith.bib
label: Mian:2017:HPC
author: Riaz-ul-Haque Mian
title: High precision computation of decimal logarithm
type: Master of Engineering in Information and Communication Technology
pages: 52
month: jan
monthnumber: 1
year: 2017
DOI: https://doi.org/10.13140/RG.2.2.11851.69924
bibdate: Tue Jul 06 18:24:02 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.06 18:24:02 ???
URL: https://www.researchgate.net/publication/323265326_High_precision_computation_of_decimal_logarithm
acknowledgement: ack-nhfb
rawauthor: Riaz-ul-Haque Mian
rawtitle: High precision computation of decimal logarithm
school:
Institute of Information and Communication Technology, Bangladesh University of Engineering and Technology

abstract:
his report presents the design of an efficient low power decimal logarithmic converter. The technique is based on shift operation along with a precision unit which is used to prevent unnecessary scan of full memory table. Precision level is user programmable. It does not require multiplication or division circuitry which in turn makes it low power. Proposed decimal logarithmic converter has been designed using Verilog HDL and then compiled and simulated using Altera provided Quartus II compiler and ModelSim simulator. The synthesis results show that the proposed design outperforms all the existing proposed decimal logarithmic converters by other researchers. The calculation is based on memory. Some predefined value and their log value are stored in memory and by using that value we calculate the logarithm of any value. Another feature which is called precision unit is used for controlling unnecessary scan of memory table. According to input of precision value the algorithm calculates logarithm value. Thus by increasing of precision value we can increase accuracy of the result. This algorithm does not need multiplication circuitry and required very low memory thus it makes the algorithm very low power.

rawabstract:
his report presents the design of an efficient low power decimal logarithmic converter. The technique is based on shift operation along with a precision unit which is used to prevent unnecessary scan of full memory table. Precision level is user programmable. It does not require multiplication or division circuitry which in turn makes it low power. Proposed decimal logarithmic converter has been designed using Verilog HDL and then compiled and simulated using Altera provided Quartus II compiler and ModelSim simulator. The synthesis results show that the proposed design outperforms all the existing proposed decimal logarithmic converters by other researchers. The calculation is based on memory. Some predefined value and their log value are stored in memory and by using that value we calculate the logarithm of any value. Another feature which is called precision unit is used for controlling unnecessary scan of memory table. According to input of precision value the algorithm calculates logarithm value. Thus by increasing of precision value we can increase accuracy of the result. This algorithm does not need multiplication circuitry and required very low memory thus it makes the algorithm very low power.

entry:
@MastersThesis{Mian:2017:HPC,
  author =       "Riaz-ul-Haque Mian",
  title =        "High precision computation of decimal logarithm",
  type =         "Master of Engineering in Information and Communication
                 Technology",
  school =       "Institute of Information and Communication Technology,
                 Bangladesh University of Engineering and Technology",
  pages =        "52",
  month =        jan,
  year =         "2017",
  DOI =          "https://doi.org/10.13140/RG.2.2.11851.69924",
  bibdate =      "Tue Jul 06 18:24:02 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.researchgate.net/publication/323265326_High_precision_computation_of_decimal_logarithm",
  abstract =     "his report presents the design of an efficient low
                 power decimal logarithmic converter. The technique is
                 based on shift operation along with a precision unit
                 which is used to prevent unnecessary scan of full
                 memory table. Precision level is user programmable. It
                 does not require multiplication or division circuitry
                 which in turn makes it low power. Proposed decimal
                 logarithmic converter has been designed using Verilog
                 HDL and then compiled and simulated using Altera
                 provided Quartus II compiler and ModelSim simulator.
                 The synthesis results show that the proposed design
                 outperforms all the existing proposed decimal
                 logarithmic converters by other researchers. The
                 calculation is based on memory. Some predefined value
                 and their log value are stored in memory and by using
                 that value we calculate the logarithm of any value.
                 Another feature which is called precision unit is used
                 for controlling unnecessary scan of memory table.
                 According to input of precision value the algorithm
                 calculates logarithm value. Thus by increasing of
                 precision value we can increase accuracy of the result.
                 This algorithm does not need multiplication circuitry
                 and required very low memory thus it makes the
                 algorithm very low power.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Micikevicius:2017:MPT
title: Mixed Precision Training
journal: arXiv.org
pages: 52
day: 10
month: oct
monthnumber: 10
year: 2017
bibdate: Mon Feb 10 09:21:08 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 09:21:08 ???
URL: https://arxiv.org/abs/1710.03740
acknowledgement: ack-nhfb
rawtitle: Mixed Precision Training
author:
Paulius Micikevicius and Sharan Narang and Jonah Alben and Gregory Diamos and Erich Elsen and David Garcia and Boris Ginsburg and Michael Houston and Oleksii Kuchaiev and Ganesh Venkatesh and Hao Wu

abstract:
Deep neural networks have enabled progress in a wide variety of applications. Growing the size of the neural network typically results in improved accuracy. As model sizes grow, the memory and compute requirements for training these models also increases. We introduce a technique to train deep neural networks using half precision floating point numbers. In our technique, weights, activations and gradients are stored in IEEE half-precision format. Half-precision floating numbers have limited numerical range compared to single-precision numbers. We propose two techniques to handle this loss of information. Firstly, we recommend maintaining a single-precision copy of the weights that accumulates the gradients after each optimizer step. This single-precision copy is rounded to half-precision format during training. Secondly, we propose scaling the loss appropriately to handle the loss of information with half-precision gradients. We demonstrate that this approach works for a wide variety of models including convolution neural networks, recurrent neural networks and generative adversarial networks. This technique works for large scale models with more than 100 million parameters trained on large datasets. Using this approach, we can reduce the memory consumption of deep learning models by nearly $ 2 times $. In future processors, we can also expect a significant computation speedup using half-precision hardware units.

rawabstract:
Deep neural networks have enabled progress in a wide variety of applications. Growing the size of the neural network typically results in improved accuracy. As model sizes grow, the memory and compute requirements for training these models also increases. We introduce a technique to train deep neural networks using half precision floating point numbers. In our technique, weights, activations and gradients are stored in IEEE half-precision format. Half-precision floating numbers have limited numerical range compared to single-precision numbers. We propose two techniques to handle this loss of information. Firstly, we recommend maintaining a single-precision copy of the weights that accumulates the gradients after each optimizer step. This single-precision copy is rounded to half-precision format during training. Secondly, we propose scaling the loss appropriately to handle the loss of information with half-precision gradients. We demonstrate that this approach works for a wide variety of models including convolution neural networks, recurrent neural networks and generative adversarial networks. This technique works for large scale models with more than 100 million parameters trained on large datasets. Using this approach, we can reduce the memory consumption of deep learning models by nearly $ 2 \times $. In future processors, we can also expect a significant computation speedup using half-precision hardware units.

rawauthor:
Paulius Micikevicius and Sharan Narang and Jonah Alben and Gregory Diamos and Erich Elsen and David Garcia and Boris Ginsburg and Michael Houston and Oleksii Kuchaiev and Ganesh Venkatesh and Hao Wu

entry:
@Article{Micikevicius:2017:MPT,
  author =       "Paulius Micikevicius and Sharan Narang and Jonah Alben
                 and Gregory Diamos and Erich Elsen and David Garcia and
                 Boris Ginsburg and Michael Houston and Oleksii Kuchaiev
                 and Ganesh Venkatesh and Hao Wu",
  title =        "Mixed Precision Training",
  journal =      "arXiv.org",
  day =          "10",
  month =        oct,
  year =         "2017",
  bibdate =      "Mon Feb 10 09:21:08 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1710.03740",
  abstract =     "Deep neural networks have enabled progress in a wide
                 variety of applications. Growing the size of the neural
                 network typically results in improved accuracy. As
                 model sizes grow, the memory and compute requirements
                 for training these models also increases. We introduce
                 a technique to train deep neural networks using half
                 precision floating point numbers. In our technique,
                 weights, activations and gradients are stored in IEEE
                 half-precision format. Half-precision floating numbers
                 have limited numerical range compared to
                 single-precision numbers. We propose two techniques to
                 handle this loss of information. Firstly, we recommend
                 maintaining a single-precision copy of the weights that
                 accumulates the gradients after each optimizer step.
                 This single-precision copy is rounded to half-precision
                 format during training. Secondly, we propose scaling
                 the loss appropriately to handle the loss of
                 information with half-precision gradients. We
                 demonstrate that this approach works for a wide variety
                 of models including convolution neural networks,
                 recurrent neural networks and generative adversarial
                 networks. This technique works for large scale models
                 with more than 100 million parameters trained on large
                 datasets. Using this approach, we can reduce the memory
                 consumption of deep learning models by nearly $ 2
                 \times $. In future processors, we can also expect a
                 significant computation speedup using half-precision
                 hardware units.",
  acknowledgement = ack-nhfb,
  archiveprefix = "arXiv",
  primaryclass = "cs.AI",
}


bibtype: misc
filename: fparith.bib
label: Moler:2017:CCB
author: Cleve Moler
title: Cleve's Corner: Bug in Half-Precision Floating Point Object
pages: 52
day: 20
month: dec
monthnumber: 12
year: 2017
bibdate: Sat Jan 19 18:38:12 2019
bibtimestamp: 2019.01.19 18:38:12 ???
note: See cite Moler:2017:CCH.
URL: https://blogs.mathworks.com/cleve/2017/12/20/bug-in-half-precision-floating-point-object/
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Cleve Moler
rawnote: See \cite{Moler:2017:CCH}.
rawtitle: {Cleve}'s Corner: Bug in Half-Precision Floating Point Object
entry:
@Misc{Moler:2017:CCB,
  author =       "Cleve Moler",
  title =        "{Cleve}'s Corner: Bug in Half-Precision Floating Point
                 Object",
  howpublished = "MathWorks Web site.",
  day =          "20",
  month =        dec,
  year =         "2017",
  bibdate =      "Sat Jan 19 18:38:12 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Moler:2017:CCH}.",
  URL =          "https://blogs.mathworks.com/cleve/2017/12/20/bug-in-half-precision-floating-point-object/",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Moler:2017:CCH
author: Cleve Moler
title: Cleve's Corner: ``Half Precision'' 16-bit Floating Point Arithmetic
pages: 52
day: 8
month: may
monthnumber: 5
year: 2017
bibdate: Sat Jan 19 18:38:12 2019
bibtimestamp: 2019.01.19 18:38:12 ???
note: See bug fix cite Moler:2017:CCB.
URL: https://blogs.mathworks.com/cleve/2017/05/08/half-precision-16-bit-floating-point-arithmetic/
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Cleve Moler
rawnote: See bug fix \cite{Moler:2017:CCB}.
rawtitle: {Cleve}'s Corner: {``Half} Precision'' 16-bit Floating Point Arithmetic
entry:
@Misc{Moler:2017:CCH,
  author =       "Cleve Moler",
  title =        "{Cleve}'s Corner: {``Half} Precision'' 16-bit Floating
                 Point Arithmetic",
  howpublished = "MathWorks Web site.",
  day =          "8",
  month =        may,
  year =         "2017",
  bibdate =      "Sat Jan 19 18:38:12 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See bug fix \cite{Moler:2017:CCB}.",
  URL =          "https://blogs.mathworks.com/cleve/2017/05/08/half-precision-16-bit-floating-point-arithmetic/",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Moler:2017:CCQ
author: Cleve Moler
title: Cleve's Corner: Quadruple Precision, 128-bit Floating Point Arithmetic
pages: 52
day: 22
month: may
monthnumber: 5
year: 2017
bibdate: Fri Feb 01 05:12:18 2019
bibtimestamp: 2019.02.01 05:12:18 ???
URL: https://blogs.mathworks.com/cleve/2017/05/22/quadruple-precision-128-bit-floating-point-arithmetic/
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Cleve Moler
rawtitle: {Cleve}'s Corner: Quadruple Precision, 128-bit Floating Point Arithmetic
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib

abstract:
The floating point arithmetic format that occupies 128 bits of storage is known as binary128 or quadruple precision. This blog post describes an implementation of quadruple precision programmed entirely in the MATLAB language.

rawabstract:
The floating point arithmetic format that occupies 128 bits of storage is known as binary128 or quadruple precision. This blog post describes an implementation of quadruple precision programmed entirely in the MATLAB language.

entry:
@Misc{Moler:2017:CCQ,
  author =       "Cleve Moler",
  title =        "{Cleve}'s Corner: Quadruple Precision, 128-bit
                 Floating Point Arithmetic",
  howpublished = "MathWorks Web site.",
  day =          "22",
  month =        may,
  year =         "2017",
  bibdate =      "Fri Feb 01 05:12:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  URL =          "https://blogs.mathworks.com/cleve/2017/05/22/quadruple-precision-128-bit-floating-point-arithmetic/",
  abstract =     "The floating point arithmetic format that occupies 128
                 bits of storage is known as binary128 or quadruple
                 precision. This blog post describes an implementation
                 of quadruple precision programmed entirely in the
                 MATLAB language.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Monfared:2017:NMI
author: Amin Monfared and Hayssam El-Razouk and Arash Reyhani-Masoleh
crossref: Burgess:2017:ISC
pages: 164--171
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.37
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Amin Monfared and Hayssam El-Razouk and Arash Reyhani-Masoleh
title:
A New Multiplicative Inverse Architecture in Normal Basis Using Novel Concurrent Serial Squaring and Multiplication

abstract:
Itoh and Tsujii proposed a fast algorithm for computing multiplicative inverses (inversions) over GF(2m) using normal bases by iterating single multiplications and cyclic shifts. Recently, the Itoh--Tsujii algorithm (ITA) has been modified to use two digit-level single multiplications. The improvements of the modified Itoh--Tsujii and its variant algorithms are based on reducing the computational latency at the expense of more area requirements. In this paper, we propose a new inversion architecture based on the classical IT algorithm (or improved one) utilizing a novel interleaved computations of two single multiplications and squarings at the digit-level. The new inverter outperforms previous modified Itoh--Tsujii algorithms (such as the Ternary Itoh--Tsujii and optimal 3-chain algorithms) in terms of its lower latency, higher throughput, and improved hardware efficiency. The efficiency of the proposed field inverter is demonstrated by comparisons based on application specific integrated circuits (ASIC) implementations results using the standard 65nm CMOS technology libraries.

keywords:
application specific integrated circuits; ASIC; CMOS technology; Computer architecture; concurrent serial squaring; cyclic shifts; Digit-level multiplier; field inversion; field inverter; finite field; Gaussian processes; High definition video; hybrid-double multiplication; Inverters; invertors; Itoh--Tsujii algorithm; logic design; multiplicative inverse architecture; multiplying circuits; Niobium; Standards; two digit-level single multiplications; Two dimensional displays

rawabstract:
Itoh and Tsujii proposed a fast algorithm for computing multiplicative inverses (inversions) over GF(2m) using normal bases by iterating single multiplications and cyclic shifts. Recently, the Itoh--Tsujii algorithm (ITA) has been modified to use two digit-level single multiplications. The improvements of the modified Itoh--Tsujii and its variant algorithms are based on reducing the computational latency at the expense of more area requirements. In this paper, we propose a new inversion architecture based on the classical IT algorithm (or improved one) utilizing a novel interleaved computations of two single multiplications and squarings at the digit-level. The new inverter outperforms previous modified Itoh--Tsujii algorithms (such as the Ternary Itoh--Tsujii and optimal 3-chain algorithms) in terms of its lower latency, higher throughput, and improved hardware efficiency. The efficiency of the proposed field inverter is demonstrated by comparisons based on application specific integrated circuits (ASIC) implementations results using the standard 65nm CMOS technology libraries.

rawtitle:
A New Multiplicative Inverse Architecture in Normal Basis Using Novel Concurrent Serial Squaring and Multiplication

entry:
@InProceedings{Monfared:2017:NMI,
  author =       "Amin Monfared and Hayssam El-Razouk and Arash
                 Reyhani-Masoleh",
  title =        "A New Multiplicative Inverse Architecture in Normal
                 Basis Using Novel Concurrent Serial Squaring and
                 Multiplication",
  crossref =     "Burgess:2017:ISC",
  pages =        "164--171",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.37",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Itoh and Tsujii proposed a fast algorithm for
                 computing multiplicative inverses (inversions) over
                 GF(2m) using normal bases by iterating single
                 multiplications and cyclic shifts. Recently, the
                 Itoh--Tsujii algorithm (ITA) has been modified to use
                 two digit-level single multiplications. The
                 improvements of the modified Itoh--Tsujii and its
                 variant algorithms are based on reducing the
                 computational latency at the expense of more area
                 requirements. In this paper, we propose a new inversion
                 architecture based on the classical IT algorithm (or
                 improved one) utilizing a novel interleaved
                 computations of two single multiplications and
                 squarings at the digit-level. The new inverter
                 outperforms previous modified Itoh--Tsujii algorithms
                 (such as the Ternary Itoh--Tsujii and optimal 3-chain
                 algorithms) in terms of its lower latency, higher
                 throughput, and improved hardware efficiency. The
                 efficiency of the proposed field inverter is
                 demonstrated by comparisons based on application
                 specific integrated circuits (ASIC) implementations
                 results using the standard 65nm CMOS technology
                 libraries.",
  acknowledgement = ack-nhfb,
  keywords =     "application specific integrated circuits; ASIC; CMOS
                 technology; Computer architecture; concurrent serial
                 squaring; cyclic shifts; Digit-level multiplier; field
                 inversion; field inverter; finite field; Gaussian
                 processes; High definition video; hybrid-double
                 multiplication; Inverters; invertors; Itoh--Tsujii
                 algorithm; logic design; multiplicative inverse
                 architecture; multiplying circuits; Niobium; Standards;
                 two digit-level single multiplications; Two dimensional
                 displays",
}


bibtype: article
filename: fparith.bib
label: Numahata:2017:ASN
author: Dai Numahata and Hiroshi Sekigawa
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 51
number: 1
pages: 18--20
month: mar
monthnumber: 3
year: 2017
DOI: https://doi.org/10.1145/3096730.3096734
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Tue Oct 10 16:29:29 MDT 2017
bibtimestamp: 2017.10.10 16:29:29 MDT
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: Dai Numahata and Hiroshi Sekigawa
title:
An algorithm for symbolic--numeric sparse interpolation of multivariate polynomials whose degree bounds are unknown

bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigsam.bib

abstract:
We consider the problem of sparse interpolation of a multivariate black-box polynomial in floating-point arithmetic. More specifically, we assume that we are given a black-box polynomial $ f(x_1, ldots , x_n) = sum ^t_j = 1 c_j x_1^d_j, 1 ldots x_n^d_j, n in C[x_1, ldots , x_n] (c_j neq 0) $ and the number of terms $t$, and that we can evaluate the value of $ f(x^1, ldots , x_n)$ at any point in $ C^n$ in floating-point arithmetic. The problem is to find the coefficients $ c_1, ldots , c_t$ and the exponents $ d_1, 1, ldots , d_t, n$. We propose an efficient algorithm to solve the problem.

rawabstract:
We consider the problem of sparse interpolation of a multivariate black-box polynomial in floating-point arithmetic. More specifically, we assume that we are given a black-box polynomial $ f(x_1, \ldots {}, x_n) = \sum^t_{j = 1} c_j x_1^{d_j, 1} \ldots {} x_n^{d_j, n} \in C[x_1, \ldots {}, x_n] (c_j \neq 0) $ and the number of terms $t$, and that we can evaluate the value of $ f(x^1, \ldots {}, x_n)$ at any point in $ C^n$ in floating-point arithmetic. The problem is to find the coefficients $ c_1, \ldots {}, c_t$ and the exponents $ d_{1, 1}, \ldots {}, d_{t, n}$. We propose an efficient algorithm to solve the problem.

rawtitle:
An algorithm for symbolic--numeric sparse interpolation of multivariate polynomials whose degree bounds are unknown

entry:
@Article{Numahata:2017:ASN,
  author =       "Dai Numahata and Hiroshi Sekigawa",
  title =        "An algorithm for symbolic--numeric sparse
                 interpolation of multivariate polynomials whose degree
                 bounds are unknown",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "51",
  number =       "1",
  pages =        "18--20",
  month =        mar,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3096730.3096734",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Tue Oct 10 16:29:29 MDT 2017",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigsam.bib",
  abstract =     "We consider the problem of sparse interpolation of a
                 multivariate black-box polynomial in floating-point
                 arithmetic. More specifically, we assume that we are
                 given a black-box polynomial $ f(x_1, \ldots {}, x_n) =
                 \sum^t_{j = 1} c_j x_1^{d_j, 1} \ldots {} x_n^{d_j, n}
                 \in C[x_1, \ldots {}, x_n] (c_j \neq 0) $ and the
                 number of terms $t$, and that we can evaluate the value
                 of $ f(x^1, \ldots {}, x_n)$ at any point in $ C^n$ in
                 floating-point arithmetic. The problem is to find the
                 coefficients $ c_1, \ldots {}, c_t$ and the exponents $
                 d_{1, 1}, \ldots {}, d_{t, n}$. We propose an efficient
                 algorithm to solve the problem.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Rafferty:2017:ELI
author: Ciara Rafferty and Maire O'Neill and Neil Hanley
title: Evaluation of Large Integer Multiplication Methods on Hardware
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 8
pages: 1369--1382
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2677426
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 13 14:57:15 MDT 2017
bibtimestamp: 2017.07.13 14:57:15 MDT
URL: http://ieeexplore.ieee.org/document/7869256/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Ciara Rafferty and M{\'a}ire O'Neill and Neil Hanley
rawtitle: Evaluation of Large Integer Multiplication Methods on Hardware
keywords:
Comba multiplication; Karatsuba multiplication; Karatsuba--Comba multiplier; NTT--Karatsuba--Schoolbook multiplier

entry:
@Article{Rafferty:2017:ELI,
  author =       "Ciara Rafferty and M{\'a}ire O'Neill and Neil Hanley",
  title =        "Evaluation of Large Integer Multiplication Methods on
                 Hardware",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "8",
  pages =        "1369--1382",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2677426",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 13 14:57:15 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7869256/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Comba multiplication; Karatsuba multiplication;
                 Karatsuba--Comba multiplier; NTT--Karatsuba--Schoolbook
                 multiplier",
}


bibtype: inproceedings
filename: fparith.bib
label: Rieu-Helft:2017:HGE
author: Raphael Rieu-Helft and Claude Marche and Guillaume Melquiond
editor: Andrei Paskevich and Thomas Wies
title: How to get an efficient yet verified arbitrary-precision integer library
volume: 10712
publisher: pub-SV
address: pub-SV:adr
pages: 84--101
year: 2017
DOI: https://doi.org/10.1007/978-3-319-72308-2_6
ISBN: 3-319-72308-1 OR 3319723081
ISBN13: 978-3-319-72308-2 OR 9783319723082
LCCN: QA76.758
bibdate: Sat Feb 08 09:03:15 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:03:15 ???
series: ser-LNCS
URL: https://link.springer.com/chapter/10.1007/978-3-319-72308-2_6
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-319-72308-2
bookpages: xiii + 211 + 69
rawauthor: Rapha{\"e}l Rieu-Helft and Claude March{\'e} and Guillaume Melquiond
raweditor: Andrei Paskevich and Thomas Wies
rawtitle: How to get an efficient yet verified arbitrary-precision integer library
booktitle:
Verified Software. Theories, Tools, and Experiments: 9th International Conference, VSTTE 2017, Heidelberg, Germany, July 22--23, 2017, Revised Selected Papers

rawbooktitle:
Verified Software. Theories, Tools, and Experiments: {9th International Conference, VSTTE 2017, Heidelberg, Germany, July 22--23, 2017}, Revised Selected Papers

entry:
@InProceedings{Rieu-Helft:2017:HGE,
  author =       "Rapha{\"e}l Rieu-Helft and Claude March{\'e} and
                 Guillaume Melquiond",
  editor =       "Andrei Paskevich and Thomas Wies",
  booktitle =    "Verified Software. Theories, Tools, and Experiments:
                 {9th International Conference, VSTTE 2017, Heidelberg,
                 Germany, July 22--23, 2017}, Revised Selected Papers",
  title =        "How to get an efficient yet verified
                 arbitrary-precision integer library",
  volume =       "10712",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  bookpages =    "xiii + 211 + 69",
  pages =        "84--101",
  year =         "2017",
  DOI =          "https://doi.org/10.1007/978-3-319-72308-2_6",
  ISBN =         "3-319-72308-1",
  ISBN-13 =      "978-3-319-72308-2",
  LCCN =         "QA76.758",
  bibdate =      "Sat Feb 08 09:03:15 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-LNCS,
  URL =          "https://link.springer.com/chapter/10.1007/978-3-319-72308-2_6",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-319-72308-2",
}


bibtype: inproceedings
filename: fparith.bib
label: Rioual:2017:LSN
author: Jean-Christophe Rioual
title: Large Scale Numerical Simulations of the Climate
crossref: Burgess:2017:ISC
pages: 122--122
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.21
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Jean-Christophe Rioual
rawtitle: Large Scale Numerical Simulations of the Climate
abstract:
The Met Office Hadley Centre for Climate Science and Services, based at the Met Office's Exeter HQ, provides world-class guidance on the science of climate change and is the primary focus in the UK for climate science. The Hadley Centre makes significant contributions to scientific literature and to a variety of climate science reports, including the International Panel on Climate Change (IPCC). In October 2014 the Government confirmed its investment of pounds 97 million in a new high performance computing facility for the Met Office. The new Cray XC40 located at Exeter Science Park is the largest HPC system in the world dedicated to weather and climate research. I will first give an overview of how climate numerical experiments are organised worldwide through the coupled model intercomparison project (CMIP) under the auspices of the world climate research program (WCRP). The numerical results of these simulation campaigns are submitted to intense scrutiny by the scientific community and policy makers. Numerical reproducibility is therefore of paramount importance. I will explain the parameters of what numerical reproducibility means to our community and how we aim to achieve it. I will present the use of different types of floating point arithmetic in the models. Two examples are the use double--double precision for reproducible global sums and research on single precision algorithms for computational efficiency. Finally, I will look at some of the challenges to maintain numerical reproducibility in the exascale era.

keywords:
climate change; Computational modeling; coupled model intercomparison project; Cray XC40; Digital arithmetic; floating point arithmetic; geophysics computing; Government; Investment; large scale numerical simulations; largest HPC system; Meteorology; Numerical models; Numerical simulation; parallel processing; world climate research program

rawabstract:
The Met Office Hadley Centre for Climate Science and Services, based at the Met Office's Exeter HQ, provides world-class guidance on the science of climate change and is the primary focus in the UK for climate science. The Hadley Centre makes significant contributions to scientific literature and to a variety of climate science reports, including the International Panel on Climate Change (IPCC). In October 2014 the Government confirmed its investment of \pounds 97 million in a new high performance computing facility for the Met Office. The new Cray XC40 located at Exeter Science Park is the largest HPC system in the world dedicated to weather and climate research. I will first give an overview of how climate numerical experiments are organised worldwide through the coupled model intercomparison project (CMIP) under the auspices of the world climate research program (WCRP). The numerical results of these simulation campaigns are submitted to intense scrutiny by the scientific community and policy makers. Numerical reproducibility is therefore of paramount importance. I will explain the parameters of what numerical reproducibility means to our community and how we aim to achieve it. I will present the use of different types of floating point arithmetic in the models. Two examples are the use double--double precision for reproducible global sums and research on single precision algorithms for computational efficiency. Finally, I will look at some of the challenges to maintain numerical reproducibility in the exascale era.

entry:
@InProceedings{Rioual:2017:LSN,
  author =       "Jean-Christophe Rioual",
  title =        "Large Scale Numerical Simulations of the Climate",
  crossref =     "Burgess:2017:ISC",
  pages =        "122--122",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.21",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Met Office Hadley Centre for Climate Science and
                 Services, based at the Met Office's Exeter HQ, provides
                 world-class guidance on the science of climate change
                 and is the primary focus in the UK for climate science.
                 The Hadley Centre makes significant contributions to
                 scientific literature and to a variety of climate
                 science reports, including the International Panel on
                 Climate Change (IPCC). In October 2014 the Government
                 confirmed its investment of \pounds 97 million in a new
                 high performance computing facility for the Met Office.
                 The new Cray XC40 located at Exeter Science Park is the
                 largest HPC system in the world dedicated to weather
                 and climate research. I will first give an overview of
                 how climate numerical experiments are organised
                 worldwide through the coupled model intercomparison
                 project (CMIP) under the auspices of the world climate
                 research program (WCRP). The numerical results of these
                 simulation campaigns are submitted to intense scrutiny
                 by the scientific community and policy makers.
                 Numerical reproducibility is therefore of paramount
                 importance. I will explain the parameters of what
                 numerical reproducibility means to our community and
                 how we aim to achieve it. I will present the use of
                 different types of floating point arithmetic in the
                 models. Two examples are the use double--double
                 precision for reproducible global sums and research on
                 single precision algorithms for computational
                 efficiency. Finally, I will look at some of the
                 challenges to maintain numerical reproducibility in the
                 exascale era.",
  acknowledgement = ack-nhfb,
  keywords =     "climate change; Computational modeling; coupled model
                 intercomparison project; Cray XC40; Digital arithmetic;
                 floating point arithmetic; geophysics computing;
                 Government; Investment; large scale numerical
                 simulations; largest HPC system; Meteorology; Numerical
                 models; Numerical simulation; parallel processing;
                 world climate research program",
}


bibtype: inproceedings
filename: fparith.bib
label: Risse:2017:BEG
author: Thomas Risse
booktitle: 2017 8th International Conference on Information Technology (ICIT)
title: Better is the enemy of good: Unums: An alternative to IEEE 754 floats and doubles
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 200--204
year: 2017
DOI: https://doi.org/10.1109/ICITECH.2017.8080000
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Thomas Risse
rawbooktitle: {2017 8th International Conference on Information Technology (ICIT)}
rawtitle: Better is the enemy of good: Unums: An alternative to {IEEE 754} floats and doubles
entry:
@InProceedings{Risse:2017:BEG,
  author =       "Thomas Risse",
  booktitle =    "{2017 8th International Conference on Information
                 Technology (ICIT)}",
  title =        "Better is the enemy of good: Unums: An alternative to
                 {IEEE 754} floats and doubles",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "200--204",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ICITECH.2017.8080000",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Rocca:2017:CRE
author: Alexandre Rocca and Victor Magron and Thao Dang
crossref: Burgess:2017:ISC
pages: 74--81
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.36
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Alexandre Rocca and Victor Magron and Thao Dang
title:
Certified Roundoff Error Bounds Using Bernstein Expansions and Sparse Krivine--Stengle Representations

abstract:
Floating point error is a notable drawback of embedded systems implementation. Computing rigorous upper bounds of roundoff errors is absolutely necessary for the validation of critical software. This problem of computing rigorous upper bounds is even more challenging when addressing non-linear programs. In this paper, we propose and compare two new methods based on Bernstein expansions and sparse Krivine--Stengle representations, adapted from the field of the global optimization, to compute upper bounds of roundoff errors for programs implementing polynomial functions. We release two related software package FPBern and FPKriSten, and compare them with state of the art tools. We show that these two methods achieve competitive performance, while computing accurate upper bounds by comparison with other tools.

keywords:
Algebra; Bernstein expansions; Bernstein Expansions; certified roundoff error bounds; Computational modeling; floating point arithmetic; Floating Point Arithmetic; floating point error; FPBern; FPKriSten; global optimization; Krivine-Stengle Representations; Linear Programming Relaxations; non-linear programs; nonlinear programming; Optimization; Polynomial Optimization; Roundoff Error Bounds; Roundoff errors; sparse Krivine-Stengle representations; Standards; Tools; Upper bound

rawabstract:
Floating point error is a notable drawback of embedded systems implementation. Computing rigorous upper bounds of roundoff errors is absolutely necessary for the validation of critical software. This problem of computing rigorous upper bounds is even more challenging when addressing non-linear programs. In this paper, we propose and compare two new methods based on Bernstein expansions and sparse Krivine--Stengle representations, adapted from the field of the global optimization, to compute upper bounds of roundoff errors for programs implementing polynomial functions. We release two related software package FPBern and FPKriSten, and compare them with state of the art tools. We show that these two methods achieve competitive performance, while computing accurate upper bounds by comparison with other tools.

rawtitle:
Certified Roundoff Error Bounds Using {Bernstein} Expansions and Sparse {Krivine--Stengle} Representations

entry:
@InProceedings{Rocca:2017:CRE,
  author =       "Alexandre Rocca and Victor Magron and Thao Dang",
  title =        "Certified Roundoff Error Bounds Using {Bernstein}
                 Expansions and Sparse {Krivine--Stengle}
                 Representations",
  crossref =     "Burgess:2017:ISC",
  pages =        "74--81",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.36",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating point error is a notable drawback of embedded
                 systems implementation. Computing rigorous upper bounds
                 of roundoff errors is absolutely necessary for the
                 validation of critical software. This problem of
                 computing rigorous upper bounds is even more
                 challenging when addressing non-linear programs. In
                 this paper, we propose and compare two new methods
                 based on Bernstein expansions and sparse
                 Krivine--Stengle representations, adapted from the
                 field of the global optimization, to compute upper
                 bounds of roundoff errors for programs implementing
                 polynomial functions. We release two related software
                 package FPBern and FPKriSten, and compare them with
                 state of the art tools. We show that these two methods
                 achieve competitive performance, while computing
                 accurate upper bounds by comparison with other tools.",
  acknowledgement = ack-nhfb,
  keywords =     "Algebra; Bernstein expansions; Bernstein Expansions;
                 certified roundoff error bounds; Computational
                 modeling; floating point arithmetic; Floating Point
                 Arithmetic; floating point error; FPBern; FPKriSten;
                 global optimization; Krivine-Stengle Representations;
                 Linear Programming Relaxations; non-linear programs;
                 nonlinear programming; Optimization; Polynomial
                 Optimization; Roundoff Error Bounds; Roundoff errors;
                 sparse Krivine-Stengle representations; Standards;
                 Tools; Upper bound",
}


bibtype: inproceedings
filename: fparith.bib
label: Rovers:2017:IPP
author: Kenneth C. Rovers and Sam Elliott
title: On Improving the Performance Per Area of ASTC with a Multi-output Decoder
crossref: Burgess:2017:ISC
pages: 58--59
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.32
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Kenneth C. Rovers and Sam Elliott
rawtitle: On Improving the Performance Per Area of {ASTC} with a Multi-output Decoder
abstract:
ASTC is an efficient and flexible texture compression format but it is relatively costly to implement in hardware. By outputting multiple texels from a single encoded ASTC block, we will show an performance per area improvement of 25%.

keywords:
adaptive scalable texture compression; computer graphics; data compression; Decoding; flexible texture compression format; Graphics; Hardware; Image color analysis; image texture; Indexes; Interpolation; multioutput decoder; Performance evaluation; performance per area; single encoded ASTC block; texture decompression

rawabstract:
ASTC is an efficient and flexible texture compression format but it is relatively costly to implement in hardware. By outputting multiple texels from a single encoded ASTC block, we will show an performance per area improvement of 25\%.

entry:
@InProceedings{Rovers:2017:IPP,
  author =       "Kenneth C. Rovers and Sam Elliott",
  title =        "On Improving the Performance Per Area of {ASTC} with a
                 Multi-output Decoder",
  crossref =     "Burgess:2017:ISC",
  pages =        "58--59",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.32",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "ASTC is an efficient and flexible texture compression
                 format but it is relatively costly to implement in
                 hardware. By outputting multiple texels from a single
                 encoded ASTC block, we will show an performance per
                 area improvement of 25\%.",
  acknowledgement = ack-nhfb,
  keywords =     "adaptive scalable texture compression; computer
                 graphics; data compression; Decoding; flexible texture
                 compression format; Graphics; Hardware; Image color
                 analysis; image texture; Indexes; Interpolation;
                 multioutput decoder; Performance evaluation;
                 performance per area; single encoded ASTC block;
                 texture decompression",
}


bibtype: article
filename: fparith.bib
label: Rump:2017:IPK
author: Siegfried M. Rump
journal: j-TOMS
volume: 43
number: 3
pages: 20:1--20:15
month: jan
monthnumber: 1
year: 2017
CODEN: ACMSCU
DOI: https://doi.org/10.1145/2785965
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Wed Oct 4 10:55:07 MDT 2017
bibtimestamp: 2017.10.04 10:55:07 MDT
URL: https://dl.acm.org/citation.cfm?id=2785965
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 20
journalURL: https://dl.acm.org/loi/toms
rawauthor: Siegfried M. Rump
title:
IEEE754 Precision-$k$ base-$ beta $ Arithmetic Inherited by Precision-$m$ Base-$ beta $ Arithmetic for $ k < m$

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
Suppose an $m$-digit floating-point arithmetic in base $ beta geq 2$ following the IEEE754 arithmetic standard is available. We show how a $k$-digit arithmetic with $ k < m$ can be inherited solely using $m$-digit operations. This includes the rounding into $k$ digits, the four basic operations and the square root, all for even or odd base $ beta $. In particular, we characterize the relation between $k$ and $m$ so that no double rounding occurs when computing in $m$ digits and rounding the result into $k$ digits. We discuss rounding to nearest as well as directed rounding, and our approach covers exceptional values including signed zero. For binary arithmetic, a Matlab toolbox based on binary64 including $k$-bit scalar, vector and matrix operations as well as $k$-bit interval arithmetic is part of Version 8 of INTLAB, the Matlab toolbox for reliable computing.

rawabstract:
Suppose an $m$-digit floating-point arithmetic in base $ \beta \geq 2$ following the IEEE754 arithmetic standard is available. We show how a $k$-digit arithmetic with $ k < m$ can be inherited solely using $m$-digit operations. This includes the rounding into $k$ digits, the four basic operations and the square root, all for even or odd base $ \beta $. In particular, we characterize the relation between $k$ and $m$ so that no double rounding occurs when computing in $m$ digits and rounding the result into $k$ digits. We discuss rounding to nearest as well as directed rounding, and our approach covers exceptional values including signed zero. For binary arithmetic, a Matlab toolbox based on binary64 including $k$-bit scalar, vector and matrix operations as well as $k$-bit interval arithmetic is part of Version 8 of INTLAB, the Matlab toolbox for reliable computing.

rawtitle:
{IEEE754} Precision-$k$ base-$ \beta $ Arithmetic Inherited by Precision-$m$ Base-$ \beta $ Arithmetic for $ k < m$

entry:
@Article{Rump:2017:IPK,
  author =       "Siegfried M. Rump",
  title =        "{IEEE754} Precision-$k$ base-$ \beta $ Arithmetic
                 Inherited by Precision-$m$ Base-$ \beta $ Arithmetic
                 for $ k < m$",
  journal =      j-TOMS,
  volume =       "43",
  number =       "3",
  pages =        "20:1--20:15",
  month =        jan,
  year =         "2017",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/2785965",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Wed Oct 4 10:55:07 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=2785965",
  abstract =     "Suppose an $m$-digit floating-point arithmetic in base
                 $ \beta \geq 2$ following the IEEE754 arithmetic
                 standard is available. We show how a $k$-digit
                 arithmetic with $ k < m$ can be inherited solely using
                 $m$-digit operations. This includes the rounding into
                 $k$ digits, the four basic operations and the square
                 root, all for even or odd base $ \beta $. In
                 particular, we characterize the relation between $k$
                 and $m$ so that no double rounding occurs when
                 computing in $m$ digits and rounding the result into
                 $k$ digits. We discuss rounding to nearest as well as
                 directed rounding, and our approach covers exceptional
                 values including signed zero. For binary arithmetic, a
                 Matlab toolbox based on binary64 including $k$-bit
                 scalar, vector and matrix operations as well as $k$-bit
                 interval arithmetic is part of Version 8 of INTLAB, the
                 Matlab toolbox for reliable computing.",
  acknowledgement = ack-nhfb,
  articleno =    "20",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Russell:2017:LBR
author: Brian M. Russell
title: Lost Bits Regained?
journal: Resurrection: The Journal of the Computer Conservation Society
number: 79
pages: ??--??
month: Autumn
year: 2017
ISSN: 0958-7403 OR 09587403
ISSNL: 0958-7403 OR 09587403
bibdate: Mon Jul 27 18:14:57 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.07.27 18:14:57 ???
URL: https://computerconservationsociety.org/resurrection/res79.htm#d
acknowledgement: ack-nhfb
rawauthor: Brian M. Russell
rawtitle: Lost Bits Regained?
remark:
Answers the question: ``Did the Ferranti Atlas floating point arithmetic unit standardise its operands before applying the requested arithmetic function or did it risk losing accuracy if the numbers were not standardised?''

entry:
@Article{Russell:2017:LBR,
  author =       "Brian M. Russell",
  title =        "Lost Bits Regained?",
  journal =      "Resurrection: The Journal of the Computer Conservation
                 Society",
  volume =       "??",
  number =       "79",
  pages =        "??--??",
  month =        "Autumn",
  year =         "2017",
  ISSN =         "0958-7403",
  ISSN-L =       "0958-7403",
  bibdate =      "Mon Jul 27 18:14:57 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://computerconservationsociety.org/resurrection/res79.htm#d",
  acknowledgement = ack-nhfb,
  remark =       "Answers the question: ``Did the Ferranti Atlas
                 floating point arithmetic unit standardise its operands
                 before applying the requested arithmetic function or
                 did it risk losing accuracy if the numbers were not
                 standardised?''",
}


bibtype: article
filename: fparith.bib
label: Saint-Genies:2017:ELT
author: Hugues de Lassus Saint-Genies and David Defour and Guillaume Revy
title: Exact Lookup Tables for the Evaluation of Trigonometric and Hyperbolic Functions
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2058--2071
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2703870
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7927421/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Hugues de Lassus Saint-Geni{\`e}s and David Defour and Guillaume Revy
rawtitle: Exact Lookup Tables for the Evaluation of Trigonometric and Hyperbolic Functions
entry:
@Article{Saint-Genies:2017:ELT,
  author =       "Hugues de Lassus Saint-Geni{\`e}s and David Defour and
                 Guillaume Revy",
  title =        "Exact Lookup Tables for the Evaluation of
                 Trigonometric and Hyperbolic Functions",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2058--2071",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2703870",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7927421/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Sanchez-Stern:2017:FRC
author: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
title: Finding Root Causes of Floating Point Error with Herbgrind
journal: arXiv.org
pages: 15
year: 2017
bibdate: Sat Feb 8 10:38:13 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 10:38:13 ???
URL: http://arxiv.org/abs/1705.10416
remark: Published in PLDI 18.
acknowledgement: ack-nhfb
rawauthor: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
rawtitle: Finding Root Causes of Floating Point Error with {Herbgrind}
abstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to a simplified program fragment whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries, and tracking error across function boundaries and through the heap.

rawabstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to a simplified program fragment whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries, and tracking error across function boundaries and through the heap.

entry:
@Article{Sanchez-Stern:2017:FRC,
  author =       "Alex Sanchez-Stern and Pavel Panchekha and Sorin
                 Lerner and Zachary Tatlock",
  title =        "Finding Root Causes of Floating Point Error with
                 {Herbgrind}",
  journal =      "arXiv.org",
  pages =        "15",
  year =         "2017",
  bibdate =      "Sat Feb 8 10:38:13 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1705.10416",
  abstract =     "Floating-point arithmetic plays a central role in
                 science, engineering, and finance by enabling
                 developers to approximate real arithmetic. To address
                 numerical issues in large floating-point applications,
                 developers must identify root causes, which is
                 difficult because floating-point errors are generally
                 non-local, non-compositional, and non-uniform. This
                 paper presents Herbgrind, a tool to help developers
                 identify and address root causes in numerical code
                 written in low-level C/C++ and Fortran. Herbgrind
                 dynamically tracks dependencies between operations and
                 program outputs to avoid false positives and abstracts
                 erroneous computations to a simplified program fragment
                 whose improvement can reduce output error. We perform
                 several case studies applying Herbgrind to large,
                 expert-crafted numerical programs and show that it
                 scales to applications spanning hundreds of thousands
                 of lines, correctly handling the low-level details of
                 modern floating point hardware and mathematical
                 libraries, and tracking error across function
                 boundaries and through the heap.",
  acknowledgement = ack-nhfb,
  archiveprefix = "arXiv",
  biburl =       "https://dblp.org/rec/bib/journals/corr/Sanchez-SternPL17",
  remark =       "Published in PLDI 18.",
}


bibtype: article
filename: fparith.bib
label: Sano:2017:FBS
author: Kentaro Sano and Satoru Yamamoto
title: FPGA-Based Scalable and Power-Efficient Fluid Simulation using Floating-Point DSP Blocks
journal: j-IEEE-TRANS-PAR-DIST-SYS
volume: 28
number: 10
pages: 2823--2837
month: oct
monthnumber: 10
year: 2017
CODEN: ITDSEO
DOI: https://doi.org/10.1109/TPDS.2017.2691770
ISSN: 1045-9219 (print), 1558-2183 (electronic) OR 10459219 (print), 15582183 (electronic)
ISSNL: 1045-9219 OR 10459219
bibdate: Thu Oct 12 06:58:12 MDT 2017
bibtimestamp: 2017.10.12 06:58:12 MDT
URL: https://www.computer.org/csdl/trans/td/2017/10/07893769-abs.html
fjournal: IEEE Transactions on Parallel and Distributed Systems
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/tpds/archives.htm
rawauthor: Kentaro Sano and Satoru Yamamoto
rawtitle: {FPGA}-Based Scalable and Power-Efficient Fluid Simulation using Floating-Point {DSP} Blocks
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranspardistsys.bib

entry:
@Article{Sano:2017:FBS,
  author =       "Kentaro Sano and Satoru Yamamoto",
  title =        "{FPGA}-Based Scalable and Power-Efficient Fluid
                 Simulation using Floating-Point {DSP} Blocks",
  journal =      j-IEEE-TRANS-PAR-DIST-SYS,
  volume =       "28",
  number =       "10",
  pages =        "2823--2837",
  month =        oct,
  year =         "2017",
  CODEN =        "ITDSEO",
  DOI =          "https://doi.org/10.1109/TPDS.2017.2691770",
  ISSN =         "1045-9219 (print), 1558-2183 (electronic)",
  ISSN-L =       "1045-9219",
  bibdate =      "Thu Oct 12 06:58:12 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranspardistsys.bib",
  URL =          "https://www.computer.org/csdl/trans/td/2017/10/07893769-abs.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Parallel and Distributed
                 Systems",
  journal-URL =  "http://www.computer.org/tpds/archives.htm",
}


bibtype: article
filename: fparith.bib
label: Schleicher:2017:NMP
author: Dierk Schleicher and Robin Stoll
title: Newton's method in practice: Finding all roots of polynomials of degree one million efficiently
journal: j-THEOR-COMP-SCI
volume: 681
pages: 146--166
day: 12
month: jun
monthnumber: 6
year: 2017
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Aug 9 15:42:32 MDT 2017
bibtimestamp: 2017.08.09 15:42:32 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0304397517302475
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Dierk Schleicher and Robin Stoll
rawtitle: {Newton}'s method in practice: Finding all roots of polynomials of degree one million efficiently
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tcs2015.bib

entry:
@Article{Schleicher:2017:NMP,
  author =       "Dierk Schleicher and Robin Stoll",
  title =        "{Newton}'s method in practice: Finding all roots of
                 polynomials of degree one million efficiently",
  journal =      j-THEOR-COMP-SCI,
  volume =       "681",
  number =       "??",
  pages =        "146--166",
  day =          "12",
  month =        jun,
  year =         "2017",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Aug 9 15:42:32 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tcs2015.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0304397517302475",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: inproceedings
filename: fparith.bib
label: Serre:2017:OSL
author: Francois Serre and Markus Puschel
title: Optimal Streamed Linear Permutations
crossref: Burgess:2017:ISC
pages: 60--61
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.13
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Fran{\c{c}}ois Serre and Markus Puschel
rawtitle: Optimal Streamed Linear Permutations
abstract:
We give an overview on optimal circuits to implement linear permutations on FPGAs using only RAM banks and switches. Linear means that the permutation maps linearly the bit representation of the indices, as it is the case with most permutations arising in digital signal processing algorithms including those in fast Fourier transforms, Viterbi decoders, and sorting networks. Additionally, we assume that the data to be permuted is streamed, i.e., input in chunks over several cycles. The circuits are obtained from a suitable factorization of the bit matrix representing the permutation and achieve the minimal number of switches possible.

keywords:
bit representation; Bit-reversal; Complexity; Computer science; Connection network; Data reordering; digital signal processing algorithms; fast Fourier transforms; field programmable gate arrays; Field programmable gate arrays; field programmable gate arrays; FPGA; Matrix factorization; optimal circuits; optimal streamed linear permutations; Parallel processing; Ports (Computers); Program processors; RAM banks; Random access memory; random-access storage; signal processing; Sorting; sorting networks; Streaming datapath; Stride permutation; Viterbi decoders; Viterbi decoding

rawabstract:
We give an overview on optimal circuits to implement linear permutations on FPGAs using only RAM banks and switches. Linear means that the permutation maps linearly the bit representation of the indices, as it is the case with most permutations arising in digital signal processing algorithms including those in fast Fourier transforms, Viterbi decoders, and sorting networks. Additionally, we assume that the data to be permuted is streamed, i.e., input in chunks over several cycles. The circuits are obtained from a suitable factorization of the bit matrix representing the permutation and achieve the minimal number of switches possible.

entry:
@InProceedings{Serre:2017:OSL,
  author =       "Fran{\c{c}}ois Serre and Markus Puschel",
  title =        "Optimal Streamed Linear Permutations",
  crossref =     "Burgess:2017:ISC",
  pages =        "60--61",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.13",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We give an overview on optimal circuits to implement
                 linear permutations on FPGAs using only RAM banks and
                 switches. Linear means that the permutation maps
                 linearly the bit representation of the indices, as it
                 is the case with most permutations arising in digital
                 signal processing algorithms including those in fast
                 Fourier transforms, Viterbi decoders, and sorting
                 networks. Additionally, we assume that the data to be
                 permuted is streamed, i.e., input in chunks over
                 several cycles. The circuits are obtained from a
                 suitable factorization of the bit matrix representing
                 the permutation and achieve the minimal number of
                 switches possible.",
  acknowledgement = ack-nhfb,
  keywords =     "bit representation; Bit-reversal; Complexity; Computer
                 science; Connection network; Data reordering; digital
                 signal processing algorithms; fast Fourier transforms;
                 field programmable gate arrays; Field programmable gate
                 arrays; field programmable gate arrays; FPGA; Matrix
                 factorization; optimal circuits; optimal streamed
                 linear permutations; Parallel processing; Ports
                 (Computers); Program processors; RAM banks; Random
                 access memory; random-access storage; signal
                 processing; Sorting; sorting networks; Streaming
                 datapath; Stride permutation; Viterbi decoders; Viterbi
                 decoding",
}


bibtype: article
filename: fparith.bib
label: Stoutemyer:2017:APC
author: David R. Stoutemyer
title: AskConstants proposes concise non-floats close to floats
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 51
number: 1
pages: 32--34
month: mar
monthnumber: 3
year: 2017
DOI: https://doi.org/10.1145/3096730.3096739
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Tue Oct 10 16:29:29 MDT 2017
bibtimestamp: 2017.10.10 16:29:29 MDT
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: David R. Stoutemyer
rawtitle: {AskConstants} proposes concise non-floats close to floats
abstract:
This poster presentation is an opportunity to try the downloadable AskConstants program. This copy of some posters is a sequence of images of the program in operation.

rawabstract:
This poster presentation is an opportunity to try the downloadable AskConstants program. This copy of some posters is a sequence of images of the program in operation.

entry:
@Article{Stoutemyer:2017:APC,
  author =       "David R. Stoutemyer",
  title =        "{AskConstants} proposes concise non-floats close to
                 floats",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "51",
  number =       "1",
  pages =        "32--34",
  month =        mar,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3096730.3096739",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Tue Oct 10 16:29:29 MDT 2017",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigsam.bib",
  abstract =     "This poster presentation is an opportunity to try the
                 downloadable AskConstants program. This copy of some
                 posters is a sequence of images of the program in
                 operation.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Thevenoux:2017:ASS
author: Laurent Thevenoux and Philippe Langlois and Matthieu Martel
journal: j-CCPE
volume: 29
number: 7
pages: ??--??
day: 10
month: apr
monthnumber: 4
year: 2017
CODEN: CCPEBO
DOI: https://doi.org/10.1002/cpe.3953
ISSN: 1532-0626 (print), 1532-0634 (electronic) OR 15320626 (print), 15320634 (electronic)
ISSNL: 1532-0626 OR 15320626
bibdate: Fri Mar 31 19:12:52 MDT 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/ccpe.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.03.31 19:12:52 MDT
fjournal: Concurrency and Computation: Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://www.interscience.wiley.com/jpages/1532-0626
rawauthor: Laurent Th{\'e}venoux and Philippe Langlois and Matthieu Martel
title:
Automatic source-to-source error compensation of floating-point programs: code synthesis to optimize accuracy and time

rawtitle:
Automatic source-to-source error compensation of floating-point programs: code synthesis to optimize accuracy and time

entry:
@Article{Thevenoux:2017:ASS,
  author =       "Laurent Th{\'e}venoux and Philippe Langlois and
                 Matthieu Martel",
  title =        "Automatic source-to-source error compensation of
                 floating-point programs: code synthesis to optimize
                 accuracy and time",
  journal =      j-CCPE,
  volume =       "29",
  number =       "7",
  pages =        "??--??",
  day =          "10",
  month =        apr,
  year =         "2017",
  CODEN =        "CCPEBO",
  DOI =          "https://doi.org/10.1002/cpe.3953",
  ISSN =         "1532-0626 (print), 1532-0634 (electronic)",
  ISSN-L =       "1532-0626",
  bibdate =      "Fri Mar 31 19:12:52 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ccpe.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Concurrency and Computation: Practice and Experience",
  journal-URL =  "http://www.interscience.wiley.com/jpages/1532-0626",
}


bibtype: article
filename: fparith.bib
label: Thornes:2017:USD
author: Tobias Thornes and Peter Duben and Tim Palmer
title: On the use of scale-dependent precision in Earth System modelling
journal: j-QUART-J-ROY-METEOROL-SOC
volume: 143
number: 703
pages: 897--908
month: jan
monthnumber: 1
year: 2017
CODEN: QJRMAM
DOI: https://doi.org/10.1002/qj.2974
ISSN: 0035-9009 (print), 1477-870X (electronic) OR 00359009 (print), 1477870X (electronic)
ISSNL: 0035-9009 OR 00359009
bibdate: Thu Nov 7 17:05:05 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.11.07 17:05:05 ???
fjournal: Quarterly journal of the Royal Meteorological Society
acknowledgement: ack-nhfb
journalURL: http://rmets.onlinelibrary.wiley.com/hub/journal/10.1002/(ISSN)1477-870X/issues/
rawauthor: Tobias Thornes and Peter D{\"u}ben and Tim Palmer
rawtitle: On the use of scale-dependent precision in {Earth System} modelling
keywords:
half-precision floating-point arithmetic; stochastic rounding; variable precision floating-point arithmetic

entry:
@Article{Thornes:2017:USD,
  author =       "Tobias Thornes and Peter D{\"u}ben and Tim Palmer",
  title =        "On the use of scale-dependent precision in {Earth
                 System} modelling",
  journal =      j-QUART-J-ROY-METEOROL-SOC,
  volume =       "143",
  number =       "703",
  pages =        "897--908",
  month =        jan,
  year =         "2017",
  CODEN =        "QJRMAM",
  DOI =          "https://doi.org/10.1002/qj.2974",
  ISSN =         "0035-9009 (print), 1477-870X (electronic)",
  ISSN-L =       "0035-9009",
  bibdate =      "Thu Nov 7 17:05:05 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Quarterly journal of the Royal Meteorological
                 Society",
  journal-URL =  "http://rmets.onlinelibrary.wiley.com/hub/journal/10.1002/(ISSN)1477-870X/issues/",
  keywords =     "half-precision floating-point arithmetic; stochastic
                 rounding; variable precision floating-point
                 arithmetic",
}


bibtype: incollection
filename: fparith.bib
label: Titolo:2017:AIF
author: Laura Titolo and Marco A. Feliu and Mariano Moscato and Cesar A. Munoz
editor: Isil Dillig and Jens Palsberg
title: An Abstract Interpretation Framework for the Round-Off Error Analysis of Floating-Point Programs
volume: 10747
publisher: pub-SV
address: pub-SV:adr
pages: 516--537
month: dec
monthnumber: 12
year: 2017
DOI: https://doi.org/10.1007/978-3-319-73721-8_24
ISBN: 3-319-73720-1 (print), 3-319-73721-X (e-book) OR 3319737201 (print), 331973721X (ebook)
bibdate: Mon Sep 11 07:21:11 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:21:11 ???
series: ser-LNCS
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-319-73721-8
rawauthor: Laura Titolo and Marco A. Feli{\'u} and Mariano Moscato and C{\'e}sar A. Mu{\~n}oz
raweditor: Isil Dillig and Jens Palsberg
rawtitle: An Abstract Interpretation Framework for the Round-Off Error Analysis of Floating-Point Programs
booktitle:
Verification, Model Checking, and Abstract Interpretation, 19th International Conference, VMCAI 2018, Los Angeles, CA, USA, January 7--9, 2018, Proceedings

ISBN13:
978-3-319-73720-1 (print), 978-3-319-73721-8 (e-book) OR 9783319737201 (print), 9783319737218 (ebook)

abstract:
This paper presents an abstract interpretation framework for the round-off error analysis of floating-point programs. This framework defines a parametric abstract analysis that computes, for each combination of ideal and floating-point execution path of the program, a sound over-approximation of the accumulated floating-point round-off error that may occur. In addition, a Boolean expression that characterizes the input values leading to the computed error approximation is also computed. An abstraction on the control flow of the program is proposed to mitigate the explosion of the number of elements generated by the analysis. Additionally, a widening operator is defined to ensure the convergence of recursive functions and loops. An instantiation of this framework is implemented in the prototype tool PRECiSA that generates formal proof certificates stating the correctness of the computed round-off errors.

rawabstract:
This paper presents an abstract interpretation framework for the round-off error analysis of floating-point programs. This framework defines a parametric abstract analysis that computes, for each combination of ideal and floating-point execution path of the program, a sound over-approximation of the accumulated floating-point round-off error that may occur. In addition, a Boolean expression that characterizes the input values leading to the computed error approximation is also computed. An abstraction on the control flow of the program is proposed to mitigate the explosion of the number of elements generated by the analysis. Additionally, a widening operator is defined to ensure the convergence of recursive functions and loops. An instantiation of this framework is implemented in the prototype tool PRECiSA that generates formal proof certificates stating the correctness of the computed round-off errors.

rawbooktitle:
Verification, Model Checking, and Abstract Interpretation, {19th International Conference, VMCAI 2018, Los Angeles, CA, USA, January 7--9, 2018, Proceedings}

entry:
@InCollection{Titolo:2017:AIF,
  author =       "Laura Titolo and Marco A. Feli{\'u} and Mariano
                 Moscato and C{\'e}sar A. Mu{\~n}oz",
  editor =       "Isil Dillig and Jens Palsberg",
  booktitle =    "Verification, Model Checking, and Abstract
                 Interpretation, {19th International Conference, VMCAI
                 2018, Los Angeles, CA, USA, January 7--9, 2018,
                 Proceedings}",
  title =        "An Abstract Interpretation Framework for the Round-Off
                 Error Analysis of Floating-Point Programs",
  volume =       "10747",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "516--537",
  month =        dec,
  year =         "2017",
  DOI =          "https://doi.org/10.1007/978-3-319-73721-8_24",
  ISBN =         "3-319-73720-1 (print), 3-319-73721-X (e-book)",
  ISBN-13 =      "978-3-319-73720-1 (print), 978-3-319-73721-8
                 (e-book)",
  bibdate =      "Mon Sep 11 07:21:11 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-LNCS,
  abstract =     "This paper presents an abstract interpretation
                 framework for the round-off error analysis of
                 floating-point programs. This framework defines a
                 parametric abstract analysis that computes, for each
                 combination of ideal and floating-point execution path
                 of the program, a sound over-approximation of the
                 accumulated floating-point round-off error that may
                 occur. In addition, a Boolean expression that
                 characterizes the input values leading to the computed
                 error approximation is also computed. An abstraction on
                 the control flow of the program is proposed to mitigate
                 the explosion of the number of elements generated by
                 the analysis. Additionally, a widening operator is
                 defined to ensure the convergence of recursive
                 functions and loops. An instantiation of this framework
                 is implemented in the prototype tool PRECiSA that
                 generates formal proof certificates stating the
                 correctness of the computed round-off errors.",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-319-73721-8",
}


bibtype: article
filename: fparith.bib
label: Ueno:2017:BCF
author: Tomohiro Ueno and Kentaro Sano and Satoru Yamamoto
journal: j-TRETS
volume: 10
number: 3
pages: 18:1--18:??
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1145/3053688
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Sat Dec 23 10:23:02 MST 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/trets.bib
bibtimestamp: 2017.12.23 10:23:02 MST
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
articleno: 18
journalURL: http://portal.acm.org/toc.cfm?id=J1151
rawauthor: Tomohiro Ueno and Kentaro Sano and Satoru Yamamoto
title:
Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing

abstract:
Although computational performance is often limited by insufficient bandwidth to/from an external memory, it is not easy to physically increase off-chip memory bandwidth. In this study, we propose a hardware-based bandwidth compression technique that can be applied to field-programmable gate array-- (FPGA) based high-performance computation with a logically wider effective memory bandwidth. Our proposed hardware approach can boost the performance of FPGA-based stream computations by applying a data compression technique to effectively transfer more data streams. To apply this data compression technique to bandwidth compression via hardware, several requirements must first be satisfied, including an acceptable level of compression performance and a sufficiently small hardware footprint. Our proposed hardware-based bandwidth compressor utilizes an efficient prediction-based data compression algorithm. Moreover, we propose a multichannel serializer and deserializer that enable applications to use multiple channels of computational data with the bandwidth compression. The serializer encodes compressed data blocks of multiple channels into a data stream, which is efficiently written to an external memory. Based on preliminary evaluation, we define an encoding format considering both high compression ratio and small hardware area. As a result, we demonstrate that our area saving bandwidth compressor increases performance of an FPGA-based fluid dynamics simulation by deploying more processing elements to exploit spatial parallelism with the enhanced memory bandwidth.

rawabstract:
Although computational performance is often limited by insufficient bandwidth to/from an external memory, it is not easy to physically increase off-chip memory bandwidth. In this study, we propose a hardware-based bandwidth compression technique that can be applied to field-programmable gate array-- (FPGA) based high-performance computation with a logically wider effective memory bandwidth. Our proposed hardware approach can boost the performance of FPGA-based stream computations by applying a data compression technique to effectively transfer more data streams. To apply this data compression technique to bandwidth compression via hardware, several requirements must first be satisfied, including an acceptable level of compression performance and a sufficiently small hardware footprint. Our proposed hardware-based bandwidth compressor utilizes an efficient prediction-based data compression algorithm. Moreover, we propose a multichannel serializer and deserializer that enable applications to use multiple channels of computational data with the bandwidth compression. The serializer encodes compressed data blocks of multiple channels into a data stream, which is efficiently written to an external memory. Based on preliminary evaluation, we define an encoding format considering both high compression ratio and small hardware area. As a result, we demonstrate that our area saving bandwidth compressor increases performance of an FPGA-based fluid dynamics simulation by deploying more processing elements to exploit spatial parallelism with the enhanced memory bandwidth.

rawtitle:
Bandwidth Compression of Floating-Point Numerical Data Streams for {FPGA}-Based High-Performance Computing

entry:
@Article{Ueno:2017:BCF,
  author =       "Tomohiro Ueno and Kentaro Sano and Satoru Yamamoto",
  title =        "Bandwidth Compression of Floating-Point Numerical Data
                 Streams for {FPGA}-Based High-Performance Computing",
  journal =      j-TRETS,
  volume =       "10",
  number =       "3",
  pages =        "18:1--18:??",
  month =        jul,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3053688",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Sat Dec 23 10:23:02 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  abstract =     "Although computational performance is often limited by
                 insufficient bandwidth to/from an external memory, it
                 is not easy to physically increase off-chip memory
                 bandwidth. In this study, we propose a hardware-based
                 bandwidth compression technique that can be applied to
                 field-programmable gate array-- (FPGA) based
                 high-performance computation with a logically wider
                 effective memory bandwidth. Our proposed hardware
                 approach can boost the performance of FPGA-based stream
                 computations by applying a data compression technique
                 to effectively transfer more data streams. To apply
                 this data compression technique to bandwidth
                 compression via hardware, several requirements must
                 first be satisfied, including an acceptable level of
                 compression performance and a sufficiently small
                 hardware footprint. Our proposed hardware-based
                 bandwidth compressor utilizes an efficient
                 prediction-based data compression algorithm. Moreover,
                 we propose a multichannel serializer and deserializer
                 that enable applications to use multiple channels of
                 computational data with the bandwidth compression. The
                 serializer encodes compressed data blocks of multiple
                 channels into a data stream, which is efficiently
                 written to an external memory. Based on preliminary
                 evaluation, we define an encoding format considering
                 both high compression ratio and small hardware area. As
                 a result, we demonstrate that our area saving bandwidth
                 compressor increases performance of an FPGA-based fluid
                 dynamics simulation by deploying more processing
                 elements to exploit spatial parallelism with the
                 enhanced memory bandwidth.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J1151",
}


