# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Uguen:2017:BHL
author: Yohann Uguen and Florent de Dinechin and Steven Derrien
booktitle: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--8
month: sep
monthnumber: 9
year: 2017
DOI: https://doi.org/10.23919/FPL.2017.8056792
ISSN: 1946-147X (print), 1946-1488 (electronic) OR 1946147X (print), 19461488 (electronic)
ISSNL: 1946-147X OR 1946147X
bibdate: Sat Feb 8 10:26:34 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 10:26:34 ???
acknowledgement: ack-nhfb
rawauthor: Yohann Uguen and Florent de Dinechin and Steven Derrien
rawbooktitle: {2017 27th International Conference on Field Programmable Logic and Applications (FPL)}
title:
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations

keywords:
Adders; application-specific arithmetic; C language; C-C++ dialects; C11 standards; Field programmable gate arrays; field programmable gate arrays; floating point arithmetic; floating-point additions; floating-point summations; FPGA application-specific efficiency; FPGA programming; handcrafted HDL; Hardware; high level synthesis; high-level C description; high-level C language; high-level specification; high-level synthesis; highly-customizable application-specific IP; HLS; IEEE-754 standards; logic design; microprocessor programming; nonstandard arithmetic formats; nonstandard computations; Open area test sites; Optimization; program compilers; Program processors; source-to-source compiler; Tools; ubiquitous floating-point summation-reduction pattern

rawtitle:
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations

entry:
@InProceedings{Uguen:2017:BHL,
  author =       "Yohann Uguen and Florent de Dinechin and Steven
                 Derrien",
  booktitle =    "{2017 27th International Conference on Field
                 Programmable Logic and Applications (FPL)}",
  title =        "Bridging high-level synthesis and application-specific
                 arithmetic: The case study of floating-point
                 summations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  month =        sep,
  year =         "2017",
  DOI =          "https://doi.org/10.23919/FPL.2017.8056792",
  ISSN =         "1946-147X (print), 1946-1488 (electronic)",
  ISSN-L =       "1946-147X",
  bibdate =      "Sat Feb 8 10:26:34 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; application-specific arithmetic; C language;
                 C-C++ dialects; C11 standards; Field programmable gate
                 arrays; field programmable gate arrays; floating point
                 arithmetic; floating-point additions; floating-point
                 summations; FPGA application-specific efficiency; FPGA
                 programming; handcrafted HDL; Hardware; high level
                 synthesis; high-level C description; high-level C
                 language; high-level specification; high-level
                 synthesis; highly-customizable application-specific IP;
                 HLS; IEEE-754 standards; logic design; microprocessor
                 programming; nonstandard arithmetic formats;
                 nonstandard computations; Open area test sites;
                 Optimization; program compilers; Program processors;
                 source-to-source compiler; Tools; ubiquitous
                 floating-point summation-reduction pattern",
}


bibtype: article
filename: fparith.bib
label: Ugurdag:2017:HDS
title: Hardware Division by Small Integer Constants
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 12
pages: 2097--2110
month: dec
monthnumber: 12
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2707488
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 10 08:32:25 MST 2017
bibtimestamp: 2017.11.10 08:32:25 MST
URL: http://ieeexplore.ieee.org/document/7933010/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: Hardware Division by Small Integer Constants
author:
H. Fatih Ugurdag and Florent de Dinechin and Y. Serhan Gener and Sezer Goren and Laurent-Stephane Didier

rawauthor:
H. Fatih Ugurdag and Florent de Dinechin and Y. Serhan Gener and Sezer G{\"o}ren and Laurent-St{\'e}phane Didier

entry:
@Article{Ugurdag:2017:HDS,
  author =       "H. Fatih Ugurdag and Florent de Dinechin and Y. Serhan
                 Gener and Sezer G{\"o}ren and Laurent-St{\'e}phane
                 Didier",
  title =        "Hardware Division by Small Integer Constants",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "12",
  pages =        "2097--2110",
  month =        dec,
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2707488",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 10 08:32:25 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/7933010/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: vanderHoeven:2017:MPF
author: Joris van der Hoeven
title: Multiple Precision Floating-Point Arithmetic on SIMD Processors
crossref: Burgess:2017:ISC
pages: 2--9
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.12
ISSN: 1063-6889 OR 10636889
MRclass: 65Y04, 65T50, 68W30
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Joris van der Hoeven
rawtitle: Multiple Precision Floating-Point Arithmetic on {SIMD} Processors
abstract:
Current general purpose libraries for multiple precision floating-point arithmetic such as MPFR suffer from a large performance penalty with respect to hard-wired instructions. The performance gap tends to become even larger with the advent of wider SIMD arithmetic in both CPUs and GPUs. In this paper, we present efficient algorithms for multiple precision floating-point arithmetic that are suitable for implementations on SIMD processors. A.C.M. subject classification: G.1.0 Computer-arithmetic A.M.S. subject classification: 65Y04, 65T50, 68W30.

keywords:
floating point arithmetic; floating-point arithmetic; Frequency modulation; Hardware; Indexes; Libraries; multiple precision; multiple precision floating-point arithmetic; Numerical analysis; parallel processing; Program processors; SIMD; SIMD processors; Standards

rawabstract:
Current general purpose libraries for multiple precision floating-point arithmetic such as MPFR suffer from a large performance penalty with respect to hard-wired instructions. The performance gap tends to become even larger with the advent of wider SIMD arithmetic in both CPUs and GPUs. In this paper, we present efficient algorithms for multiple precision floating-point arithmetic that are suitable for implementations on SIMD processors. A.C.M. subject classification: G.1.0 Computer-arithmetic A.M.S. subject classification: 65Y04, 65T50, 68W30.

entry:
@InProceedings{vanderHoeven:2017:MPF,
  author =       "Joris van der Hoeven",
  title =        "Multiple Precision Floating-Point Arithmetic on {SIMD}
                 Processors",
  crossref =     "Burgess:2017:ISC",
  pages =        "2--9",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.12",
  ISSN =         "1063-6889",
  MRclass =      "65Y04, 65T50, 68W30",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Current general purpose libraries for multiple
                 precision floating-point arithmetic such as MPFR suffer
                 from a large performance penalty with respect to
                 hard-wired instructions. The performance gap tends to
                 become even larger with the advent of wider SIMD
                 arithmetic in both CPUs and GPUs. In this paper, we
                 present efficient algorithms for multiple precision
                 floating-point arithmetic that are suitable for
                 implementations on SIMD processors. A.C.M. subject
                 classification: G.1.0 Computer-arithmetic A.M.S.
                 subject classification: 65Y04, 65T50, 68W30.",
  acknowledgement = ack-nhfb,
  keywords =     "floating point arithmetic; floating-point arithmetic;
                 Frequency modulation; Hardware; Indexes; Libraries;
                 multiple precision; multiple precision floating-point
                 arithmetic; Numerical analysis; parallel processing;
                 Program processors; SIMD; SIMD processors; Standards",
}


bibtype: article
filename: fparith.bib
label: VanZee:2017:IHP
author: Field G. Van Zee and Tyler M. Smith
title: Implementing High-performance Complex Matrix Multiplication via the 3m and 4m Methods
journal: j-TOMS
volume: 44
number: 1
pages: 7:1--7:36
month: jul
monthnumber: 7
year: 2017
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3086466
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Wed Oct 4 10:55:07 MDT 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2017.10.04 10:55:07 MDT
URL: https://dl.acm.org/citation.cfm?id=3086466
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 7
journalURL: https://dl.acm.org/loi/toms
rawauthor: Field G. {Van Zee} and Tyler M. Smith
rawtitle: Implementing High-performance Complex Matrix Multiplication via the 3m and 4m Methods
abstract:
In this article, we explore the implementation of complex matrix multiplication. We begin by briefly identifying various challenges associated with the conventional approach, which calls for a carefully written kernel that implements complex arithmetic at the lowest possible level (i.e., assembly language). We then set out to develop a method of complex matrix multiplication that avoids the need for complex kernels altogether. This constraint promotes code reuse and portability within libraries such as Basic Linear Algebra Subprograms and BLAS-Like Library Instantiation Software (BLIS) and allows kernel developers to focus their efforts on fewer and simpler kernels. We develop two alternative approaches --- one based on the 3m method and one that reflects the classic 4m formulation --- each with multiple variants, all of which rely only on real matrix multiplication kernels. We discuss the performance characteristics of these ``induced'' methods and observe that the assembly-level method actually resides along the 4m spectrum of algorithmic variants. Implementations are developed within the BLIS framework, and testing on modern hardware confirms that while the less numerically stable 3m method yields the fastest runtimes, the more stable (and thus widely applicable) 4m method's performance is somewhat limited due to implementation challenges that appear inherent in nature.

rawabstract:
In this article, we explore the implementation of complex matrix multiplication. We begin by briefly identifying various challenges associated with the conventional approach, which calls for a carefully written kernel that implements complex arithmetic at the lowest possible level (i.e., assembly language). We then set out to develop a method of complex matrix multiplication that avoids the need for complex kernels altogether. This constraint promotes code reuse and portability within libraries such as Basic Linear Algebra Subprograms and BLAS-Like Library Instantiation Software (BLIS) and allows kernel developers to focus their efforts on fewer and simpler kernels. We develop two alternative approaches --- one based on the 3m method and one that reflects the classic 4m formulation --- each with multiple variants, all of which rely only on real matrix multiplication kernels. We discuss the performance characteristics of these ``induced'' methods and observe that the assembly-level method actually resides along the 4m spectrum of algorithmic variants. Implementations are developed within the BLIS framework, and testing on modern hardware confirms that while the less numerically stable 3m method yields the fastest runtimes, the more stable (and thus widely applicable) 4m method's performance is somewhat limited due to implementation challenges that appear inherent in nature.

entry:
@Article{VanZee:2017:IHP,
  author =       "Field G. {Van Zee} and Tyler M. Smith",
  title =        "Implementing High-performance Complex Matrix
                 Multiplication via the 3m and 4m Methods",
  journal =      j-TOMS,
  volume =       "44",
  number =       "1",
  pages =        "7:1--7:36",
  month =        jul,
  year =         "2017",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3086466",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Wed Oct 4 10:55:07 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3086466",
  abstract =     "In this article, we explore the implementation of
                 complex matrix multiplication. We begin by briefly
                 identifying various challenges associated with the
                 conventional approach, which calls for a carefully
                 written kernel that implements complex arithmetic at
                 the lowest possible level (i.e., assembly language). We
                 then set out to develop a method of complex matrix
                 multiplication that avoids the need for complex kernels
                 altogether. This constraint promotes code reuse and
                 portability within libraries such as Basic Linear
                 Algebra Subprograms and BLAS-Like Library Instantiation
                 Software (BLIS) and allows kernel developers to focus
                 their efforts on fewer and simpler kernels. We develop
                 two alternative approaches --- one based on the 3m
                 method and one that reflects the classic 4m formulation
                 --- each with multiple variants, all of which rely only
                 on real matrix multiplication kernels. We discuss the
                 performance characteristics of these ``induced''
                 methods and observe that the assembly-level method
                 actually resides along the 4m spectrum of algorithmic
                 variants. Implementations are developed within the BLIS
                 framework, and testing on modern hardware confirms that
                 while the less numerically stable 3m method yields the
                 fastest runtimes, the more stable (and thus widely
                 applicable) 4m method's performance is somewhat limited
                 due to implementation challenges that appear inherent
                 in nature.",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2017:SED
author: Alvaro Vazquez and Elisardo Antelo
title: A Sum Error Detection Scheme for Decimal Arithmetic
crossref: Burgess:2017:ISC
pages: 172--179
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.34
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Alvaro V{\'a}zquez and Elisardo Antelo
rawtitle: A Sum Error Detection Scheme for Decimal Arithmetic
abstract:
Users of financial and e-commerce services demand a high degree of reliability and at the same time an increasing demand of speed of processing. On the other hand, soft errors are becoming more significant due to the higher densities and reduced CMOS integration technology sizes. Among the basic arithmetic operations, addition/subtraction is the most demanded. Although in the past, binary implementations were only considered, today decimal implementations are becoming important. In this context, we introduce a modular design for fast error checking of binary and decimal (BCD) addition/subtraction operations that avoids the whole replication of the arithmetic units. Unlike other error checkers based on parity prediction or residue checking, this is a separable design that lies completely off of the critical path of the protected adder without incurring in important penalties in area or performance.

keywords:
adders; Adders; arithmetic units; CMOS; CMOS integrated circuits; CMOS logic circuits; Combined decimal/binary Adders; Computer architecture; decimal arithmetic; Decimal arithmetic; Detectors; digital arithmetic; error checking; logic design; Microprocessors; parity prediction; radiation hardening (electronics); Reliability; residue checking; Residue Checking; Silicon; soft errors; sum error detection scheme; Transient analysis

rawabstract:
Users of financial and e-commerce services demand a high degree of reliability and at the same time an increasing demand of speed of processing. On the other hand, soft errors are becoming more significant due to the higher densities and reduced CMOS integration technology sizes. Among the basic arithmetic operations, addition/subtraction is the most demanded. Although in the past, binary implementations were only considered, today decimal implementations are becoming important. In this context, we introduce a modular design for fast error checking of binary and decimal (BCD) addition/subtraction operations that avoids the whole replication of the arithmetic units. Unlike other error checkers based on parity prediction or residue checking, this is a separable design that lies completely off of the critical path of the protected adder without incurring in important penalties in area or performance.

entry:
@InProceedings{Vazquez:2017:SED,
  author =       "Alvaro V{\'a}zquez and Elisardo Antelo",
  title =        "A Sum Error Detection Scheme for Decimal Arithmetic",
  crossref =     "Burgess:2017:ISC",
  pages =        "172--179",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.34",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Users of financial and e-commerce services demand a
                 high degree of reliability and at the same time an
                 increasing demand of speed of processing. On the other
                 hand, soft errors are becoming more significant due to
                 the higher densities and reduced CMOS integration
                 technology sizes. Among the basic arithmetic
                 operations, addition/subtraction is the most demanded.
                 Although in the past, binary implementations were only
                 considered, today decimal implementations are becoming
                 important. In this context, we introduce a modular
                 design for fast error checking of binary and decimal
                 (BCD) addition/subtraction operations that avoids the
                 whole replication of the arithmetic units. Unlike other
                 error checkers based on parity prediction or residue
                 checking, this is a separable design that lies
                 completely off of the critical path of the protected
                 adder without incurring in important penalties in area
                 or performance.",
  acknowledgement = ack-nhfb,
  keywords =     "adders; Adders; arithmetic units; CMOS; CMOS
                 integrated circuits; CMOS logic circuits; Combined
                 decimal/binary Adders; Computer architecture; decimal
                 arithmetic; Decimal arithmetic; Detectors; digital
                 arithmetic; error checking; logic design;
                 Microprocessors; parity prediction; radiation hardening
                 (electronics); Reliability; residue checking; Residue
                 Checking; Silicon; soft errors; sum error detection
                 scheme; Transient analysis",
}


bibtype: inproceedings
filename: fparith.bib
label: Volkova:2017:RVD
author: Anastasia Volkova and Christoph Lauter and Thibault Hilaire
title: Reliable Verification of Digital Implemented Filters Against Frequency Specifications
crossref: Burgess:2017:ISC
pages: 180--187
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.9
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Anastasia Volkova and Christoph Lauter and Thibault Hilaire
rawtitle: Reliable Verification of Digital Implemented Filters Against Frequency Specifications
abstract:
Reliable implementation of digital filters in finite precision is based on accurate error analysis. However, a small error in the time domain does not guarantee that the implemented filter verifies the initial band specifications in the frequency domain. We propose a novel certified algorithm for the verification of a filter's transfer function, or of an existing finite-precision implementation. We show that this problem boils down to the verification of bounds on a rational function, and further to the positivity of a polynomial. Our algorithm has reasonable runtime efficiency to be used as a criterion in large implementation space explorations. We ensure that there are no false positives but false negative answers may occur. For negative answers we give a tight bound on the margin of acceptable specifications. We demonstrate application of our algorithm to the comparison of various finite-precision implementations of filters already fully designed.

keywords:
Algorithm design and analysis; digital filters; digital implemented filters; eigendecomposition; filters; finite-precision implementation; fixed-point arithmetic; floating-point arithmetic; frequency specifications; Frequency-domain analysis; interval arithmetic; polynomials; Positivstellensatz; reliability; Reliability; rigorous computation; Signal processing algorithms; Software algorithms; transfer function; transfer functions; Transfer functions; Transforms

rawabstract:
Reliable implementation of digital filters in finite precision is based on accurate error analysis. However, a small error in the time domain does not guarantee that the implemented filter verifies the initial band specifications in the frequency domain. We propose a novel certified algorithm for the verification of a filter's transfer function, or of an existing finite-precision implementation. We show that this problem boils down to the verification of bounds on a rational function, and further to the positivity of a polynomial. Our algorithm has reasonable runtime efficiency to be used as a criterion in large implementation space explorations. We ensure that there are no false positives but false negative answers may occur. For negative answers we give a tight bound on the margin of acceptable specifications. We demonstrate application of our algorithm to the comparison of various finite-precision implementations of filters already fully designed.

entry:
@InProceedings{Volkova:2017:RVD,
  author =       "Anastasia Volkova and Christoph Lauter and Thibault
                 Hilaire",
  title =        "Reliable Verification of Digital Implemented Filters
                 Against Frequency Specifications",
  crossref =     "Burgess:2017:ISC",
  pages =        "180--187",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.9",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Reliable implementation of digital filters in finite
                 precision is based on accurate error analysis. However,
                 a small error in the time domain does not guarantee
                 that the implemented filter verifies the initial band
                 specifications in the frequency domain. We propose a
                 novel certified algorithm for the verification of a
                 filter's transfer function, or of an existing
                 finite-precision implementation. We show that this
                 problem boils down to the verification of bounds on a
                 rational function, and further to the positivity of a
                 polynomial. Our algorithm has reasonable runtime
                 efficiency to be used as a criterion in large
                 implementation space explorations. We ensure that there
                 are no false positives but false negative answers may
                 occur. For negative answers we give a tight bound on
                 the margin of acceptable specifications. We demonstrate
                 application of our algorithm to the comparison of
                 various finite-precision implementations of filters
                 already fully designed.",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; digital filters;
                 digital implemented filters; eigendecomposition;
                 filters; finite-precision implementation; fixed-point
                 arithmetic; floating-point arithmetic; frequency
                 specifications; Frequency-domain analysis; interval
                 arithmetic; polynomials; Positivstellensatz;
                 reliability; Reliability; rigorous computation; Signal
                 processing algorithms; Software algorithms; transfer
                 function; transfer functions; Transfer functions;
                 Transforms",
}


bibtype: inproceedings
filename: fparith.bib
label: Vzquez:2017:NSA
author: Alvaro Vazquez and Elisardo Antelo
title: A Number System Approach for Adder Topologies
crossref: Burgess:2017:ISC
pages: 50--57
month: jul
monthnumber: 7
year: 2017
DOI: https://doi.org/10.1109/ARITH.2017.33
ISSN: 1063-6889 OR 10636889
bibdate: Fri Nov 17 09:10:14 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.11.17 09:10:14 ???
acknowledgement: ack-nhfb
rawauthor: Alvaro V{\'a}zquez and Elisardo Antelo
rawtitle: A Number System Approach for Adder Topologies
abstract:
The design space exploration for fast and power efficient adders is of increasing interest for microprocessors and graphic and digital signal processors. Recently, several methods have been proposed to explore the design space of adders, where well known designs appear as possible instances. These methods are based on the identification of parameters that lead to different hardware structures. In this work, we go a step further by exploring the mathematical foundation behind the trees for carry computation. We propose an algorithm that allows to obtain any adder topology based on design decisions. The method is based on finding representations of integers in a given number system. This leads to an adder model that allows the design of any adder structure in a compact a formal way. The proposed formal model might be useful for a formal design description of adders and it can be incorporated to CAD tools.

keywords:
Adder Topologies; adder topology; Adders; adders; carry computation; carry logic; Computational modeling; design space exploration; logic design; Mathematical model; Number Systems; Prefix Adders; Solid modeling; Space exploration; Sparse Trees; Tools; Topology

rawabstract:
The design space exploration for fast and power efficient adders is of increasing interest for microprocessors and graphic and digital signal processors. Recently, several methods have been proposed to explore the design space of adders, where well known designs appear as possible instances. These methods are based on the identification of parameters that lead to different hardware structures. In this work, we go a step further by exploring the mathematical foundation behind the trees for carry computation. We propose an algorithm that allows to obtain any adder topology based on design decisions. The method is based on finding representations of integers in a given number system. This leads to an adder model that allows the design of any adder structure in a compact a formal way. The proposed formal model might be useful for a formal design description of adders and it can be incorporated to CAD tools.

entry:
@InProceedings{Vzquez:2017:NSA,
  author =       "Alvaro V{\'a}zquez and Elisardo Antelo",
  title =        "A Number System Approach for Adder Topologies",
  crossref =     "Burgess:2017:ISC",
  pages =        "50--57",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.33",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The design space exploration for fast and power
                 efficient adders is of increasing interest for
                 microprocessors and graphic and digital signal
                 processors. Recently, several methods have been
                 proposed to explore the design space of adders, where
                 well known designs appear as possible instances. These
                 methods are based on the identification of parameters
                 that lead to different hardware structures. In this
                 work, we go a step further by exploring the
                 mathematical foundation behind the trees for carry
                 computation. We propose an algorithm that allows to
                 obtain any adder topology based on design decisions.
                 The method is based on finding representations of
                 integers in a given number system. This leads to an
                 adder model that allows the design of any adder
                 structure in a compact a formal way. The proposed
                 formal model might be useful for a formal design
                 description of adders and it can be incorporated to CAD
                 tools.",
  acknowledgement = ack-nhfb,
  keywords =     "Adder Topologies; adder topology; Adders; adders;
                 carry computation; carry logic; Computational modeling;
                 design space exploration; logic design; Mathematical
                 model; Number Systems; Prefix Adders; Solid modeling;
                 Space exploration; Sparse Trees; Tools; Topology",
}


bibtype: article
filename: fparith.bib
label: Wahba:2017:AEF
author: Ahmed A. Wahba and Hossam A. H. Fahmy
title: Area Efficient and Fast Combined Binary / Decimal Floating Point Fused Multiply Add Unit
journal: j-IEEE-TRANS-COMPUT
volume: 66
number: 2
pages: 226--239
year: 2017
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2016.2584067
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jan 19 06:52:50 MST 2017
bibtimestamp: 2017.01.19 06:52:50 MST
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Ahmed A. Wahba and Hossam A. H. Fahmy
rawtitle: Area Efficient and Fast Combined Binary\slash Decimal Floating Point Fused Multiply Add Unit
entry:
@Article{Wahba:2017:AEF,
  author =       "Ahmed A. Wahba and Hossam A. H. Fahmy",
  title =        "Area Efficient and Fast Combined Binary\slash Decimal
                 Floating Point Fused Multiply Add Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "66",
  number =       "2",
  pages =        "226--239",
  month =        "????",
  year =         "2017",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2016.2584067",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jan 19 06:52:50 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Adams:2018:RFF
author: Ulf Adams
title: Ryu: fast float-to-string conversion
journal: j-SIGPLAN
volume: 53
number: 4
pages: 270--282
month: apr
monthnumber: 4
year: 2018
CODEN: SINODQ
DOI: https://doi.org/10.1145/3296979.3192369
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Wed Oct 16 14:12:57 MDT 2019
bibtimestamp: 2019.10.16 14:12:57 MDT
fjournal: ACM SIGPLAN Notices
remark: PLDI '18 proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Ulf Adams
rawtitle: {Ry{\=u}}: fast float-to-string conversion
abstract:
We present Ryu, a new routine to convert binary floating point numbers to their decimal representations using only fixed-size integer operations, and prove its correctness. Ryu is simpler and approximately three times faster than the previously fastest implementation.

keywords:
base conversion; correct rounding; floating-point arithmetic; input-output conversion; radix conversion; round-trip base conversion

rawabstract:
We present Ry{\=u}, a new routine to convert binary floating point numbers to their decimal representations using only fixed-size integer operations, and prove its correctness. Ry{\=u} is simpler and approximately three times faster than the previously fastest implementation.

entry:
@Article{Adams:2018:RFF,
  author =       "Ulf Adams",
  title =        "{Ry{\=u}}: fast float-to-string conversion",
  journal =      j-SIGPLAN,
  volume =       "53",
  number =       "4",
  pages =        "270--282",
  month =        apr,
  year =         "2018",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3296979.3192369",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Wed Oct 16 14:12:57 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "We present Ry{\=u}, a new routine to convert binary
                 floating point numbers to their decimal representations
                 using only fixed-size integer operations, and prove its
                 correctness. Ry{\=u} is simpler and approximately three
                 times faster than the previously fastest
                 implementation.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "base conversion; correct rounding; floating-point
                 arithmetic; input-output conversion; radix conversion;
                 round-trip base conversion",
  remark =       "PLDI '18 proceedings.",
}


bibtype: article
filename: fparith.bib
label: Alaghi:2018:CR
author: A. Alaghi and J. P. Hayes
title: Computing with Randomness
journal: j-IEEE-SPECTRUM
volume: 55
number: 3
pages: 46--51
month: mar
monthnumber: 3
year: 2018
CODEN: IEESAM
DOI: https://doi.org/10.1109/MSPEC.2018.8302387
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Sat Jan 18 07:02:09 2020
bibtimestamp: 2020.01.18 07:02:09 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: A. Alaghi and J. P. Hayes
rawtitle: Computing with Randomness
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib

keywords:
analog numbers; analog signal; arithmetic operations; brains-process; computer process; Computers; digital arithmetic; Digital circuits; human hearing; human nervous system; human vision; Image restoration; Implants; logic circuits; Logic gates; neural impulse sequence; Parity check codes; random binary digit stream; Retina; stochastic bitstreams; stochastic computing; stochastic processes; time 50 year

entry:
@Article{Alaghi:2018:CR,
  author =       "A. Alaghi and J. P. Hayes",
  title =        "Computing with Randomness",
  journal =      j-IEEE-SPECTRUM,
  volume =       "55",
  number =       "3",
  pages =        "46--51",
  month =        mar,
  year =         "2018",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2018.8302387",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Sat Jan 18 07:02:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "analog numbers; analog signal; arithmetic operations;
                 brains-process; computer process; Computers; digital
                 arithmetic; Digital circuits; human hearing; human
                 nervous system; human vision; Image restoration;
                 Implants; logic circuits; Logic gates; neural impulse
                 sequence; Parity check codes; random binary digit
                 stream; Retina; stochastic bitstreams; stochastic
                 computing; stochastic processes; time 50 year",
}


bibtype: article
filename: fparith.bib
label: Amanollahi:2018:ERD
author: Saba Amanollahi and Ghassem Jaberipur
title: Extended Redundant-Digit Instruction Set for Energy-Efficient Processors
journal: j-TECS
volume: 17
number: 3
pages: 70:1--70:??
month: jun
monthnumber: 6
year: 2018
DOI: https://doi.org/10.1145/3202664
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Oct 17 18:16:35 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2019.10.17 18:16:35 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 70
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J840
rawauthor: Saba Amanollahi and Ghassem Jaberipur
rawtitle: Extended Redundant-Digit Instruction Set for Energy-Efficient Processors
abstract:
The impact of extending the instruction set architecture (ISA) of a conventional binary processor by a set of redundant-digit arithmetic instructions is studied. Selected binary arithmetic instructions within a given code sequence are replaced with appropriate redundant-digit ones. The selection criteria is so enforced to lead to overall reduction of execution energy and energy-delay product (EDP). A special branch and bound algorithm is devised to modify the dataflow graph (DFG) to a new one that takes advantage of the extended redundant-digit instruction set. The DFG is obtained, via an in-house tool, from the intermediate code representation that is normally produced by the utilized compiler. The required redundant-digit arithmetic operations (including a multiplier, a multiply accumulator, and three- to four-operand redundant-digit adders specially designed for this work) have been synthesized on 45nm NanGate technology by a Synopsys Design Compiler. To evaluate the impact of the proposed ISA augmentation on actual code execution, the simulation and evaluation platform of our choice is an MIPS processor whose ISA is extended by the proposed redundant-digit instructions. Several digital signal processing benchmarks are utilized as the source of the baseline MIPS codes, which are converted (via the aforementioned algorithm) to the equivalent mixed binary/redundant-digit codes. Our experiments, as such, show up to 26% energy and 44% EDP savings.

rawabstract:
The impact of extending the instruction set architecture (ISA) of a conventional binary processor by a set of redundant-digit arithmetic instructions is studied. Selected binary arithmetic instructions within a given code sequence are replaced with appropriate redundant-digit ones. The selection criteria is so enforced to lead to overall reduction of execution energy and energy-delay product (EDP). A special branch and bound algorithm is devised to modify the dataflow graph (DFG) to a new one that takes advantage of the extended redundant-digit instruction set. The DFG is obtained, via an in-house tool, from the intermediate code representation that is normally produced by the utilized compiler. The required redundant-digit arithmetic operations (including a multiplier, a multiply accumulator, and three- to four-operand redundant-digit adders specially designed for this work) have been synthesized on 45nm NanGate technology by a Synopsys Design Compiler. To evaluate the impact of the proposed ISA augmentation on actual code execution, the simulation and evaluation platform of our choice is an MIPS processor whose ISA is extended by the proposed redundant-digit instructions. Several digital signal processing benchmarks are utilized as the source of the baseline MIPS codes, which are converted (via the aforementioned algorithm) to the equivalent mixed binary/redundant-digit codes. Our experiments, as such, show up to 26\% energy and 44\% EDP savings.

entry:
@Article{Amanollahi:2018:ERD,
  author =       "Saba Amanollahi and Ghassem Jaberipur",
  title =        "Extended Redundant-Digit Instruction Set for
                 Energy-Efficient Processors",
  journal =      j-TECS,
  volume =       "17",
  number =       "3",
  pages =        "70:1--70:??",
  month =        jun,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3202664",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Oct 17 18:16:35 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  abstract =     "The impact of extending the instruction set
                 architecture (ISA) of a conventional binary processor
                 by a set of redundant-digit arithmetic instructions is
                 studied. Selected binary arithmetic instructions within
                 a given code sequence are replaced with appropriate
                 redundant-digit ones. The selection criteria is so
                 enforced to lead to overall reduction of execution
                 energy and energy-delay product (EDP). A special branch
                 and bound algorithm is devised to modify the dataflow
                 graph (DFG) to a new one that takes advantage of the
                 extended redundant-digit instruction set. The DFG is
                 obtained, via an in-house tool, from the intermediate
                 code representation that is normally produced by the
                 utilized compiler. The required redundant-digit
                 arithmetic operations (including a multiplier, a
                 multiply accumulator, and three- to four-operand
                 redundant-digit adders specially designed for this
                 work) have been synthesized on 45nm NanGate technology
                 by a Synopsys Design Compiler. To evaluate the impact
                 of the proposed ISA augmentation on actual code
                 execution, the simulation and evaluation platform of
                 our choice is an MIPS processor whose ISA is extended
                 by the proposed redundant-digit instructions. Several
                 digital signal processing benchmarks are utilized as
                 the source of the baseline MIPS codes, which are
                 converted (via the aforementioned algorithm) to the
                 equivalent mixed binary/redundant-digit codes. Our
                 experiments, as such, show up to 26\% energy and 44\%
                 EDP savings.",
  acknowledgement = ack-nhfb,
  articleno =    "70",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J840",
}


bibtype: inproceedings
filename: fparith.bib
label: Anderson:2018:EVM
author: Cristina S. Anderson and Jingwei Zhang and Marius Cornea
title: Enhanced Vector Math Support on the Intel AVX-512 Architecture
crossref: Tenca:2018:PIS
pages: 120--124
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464794
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Cristina S. Anderson and Jingwei Zhang and Marius Cornea
rawtitle: Enhanced Vector Math Support on the {Intel AVX-512} Architecture
abstract:
The Intel AVX-512 architecture adds new capabilities such as masked execution, floating-point exception suppression and static rounding modes, as well as a small set of new instructions for mathematical library support. These new features allow for better compliance with floating-point or language standards (e.g. no spurious floating-point exceptions, and faster or more accurate code for directed rounding modes), as well as simpler, smaller footprint implementations that eliminate branches and special case paths. Performance is also improved, in particular for vector mathematical functions (which benefit from easier processing in the main path, and fast access to small lookup tables). In this paper, we describe the relevant new features and their possible applications to floating-point computation. The code examples include a few compact implementation sequences for some common vector mathematical functions.

keywords:
ARITH-25; common vector mathematical functions; directed rounding modes; enhanced vector math support; floating-point; floating-point computation; floating-point exception suppression; floating-point exceptions; Instruction sets; Intel AVX-512 architecture; Libraries; masked execution; mathematical library support; mathematics computing; Registers; SIMD; Standards; static rounding modes; Support vector machines; Table lookup; table lookup; vector mathematical function; vectors

rawabstract:
The Intel AVX-512 architecture adds new capabilities such as masked execution, floating-point exception suppression and static rounding modes, as well as a small set of new instructions for mathematical library support. These new features allow for better compliance with floating-point or language standards (e.g. no spurious floating-point exceptions, and faster or more accurate code for directed rounding modes), as well as simpler, smaller footprint implementations that eliminate branches and special case paths. Performance is also improved, in particular for vector mathematical functions (which benefit from easier processing in the main path, and fast access to small lookup tables). In this paper, we describe the relevant new features and their possible applications to floating-point computation. The code examples include a few compact implementation sequences for some common vector mathematical functions.

entry:
@InProceedings{Anderson:2018:EVM,
  author =       "Cristina S. Anderson and Jingwei Zhang and Marius
                 Cornea",
  title =        "Enhanced Vector Math Support on the {Intel AVX-512}
                 Architecture",
  crossref =     "Tenca:2018:PIS",
  pages =        "120--124",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464794",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Intel AVX-512 architecture adds new capabilities
                 such as masked execution, floating-point exception
                 suppression and static rounding modes, as well as a
                 small set of new instructions for mathematical library
                 support. These new features allow for better compliance
                 with floating-point or language standards (e.g. no
                 spurious floating-point exceptions, and faster or more
                 accurate code for directed rounding modes), as well as
                 simpler, smaller footprint implementations that
                 eliminate branches and special case paths. Performance
                 is also improved, in particular for vector mathematical
                 functions (which benefit from easier processing in the
                 main path, and fast access to small lookup tables). In
                 this paper, we describe the relevant new features and
                 their possible applications to floating-point
                 computation. The code examples include a few compact
                 implementation sequences for some common vector
                 mathematical functions.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; common vector mathematical functions;
                 directed rounding modes; enhanced vector math support;
                 floating-point; floating-point computation;
                 floating-point exception suppression; floating-point
                 exceptions; Instruction sets; Intel AVX-512
                 architecture; Libraries; masked execution; mathematical
                 library support; mathematics computing; Registers;
                 SIMD; Standards; static rounding modes; Support vector
                 machines; Table lookup; table lookup; vector
                 mathematical function; vectors",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2018:DRD
author: Anonymous
title: Driverless racecar drives straight into a wall
pages: 120--124
year: 2018
bibdate: Mon Aug 26 12:09:20 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.08.26 12:09:20 ???
URL: https://www.reddit.com/r/formula1/comments/jk9jrg/comment/gai295l/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: Driverless racecar drives straight into a wall
note:
The report describes how an unanticipated floating-point NaN caused the steering wheel to lock to its maximum right. From the report: ``the [controller] output values are transferred via control area network (CAN) to the actuators, but there is no definition for a NaN in the CAN specs, so it just transformed it into a normal number, albeit a very large one.''

rawnote:
The report describes how an unanticipated floating-point NaN caused the steering wheel to lock to its maximum right. From the report: ``the [controller] output values are transferred via control area network (CAN) to the actuators, but there is no definition for a NaN in the CAN specs, so it just transformed it into a normal number, albeit a very large one.''

entry:
@Misc{Anonymous:2018:DRD,
  author =       "Anonymous",
  title =        "Driverless racecar drives straight into a wall",
  howpublished = "Web site",
  year =         "2018",
  bibdate =      "Mon Aug 26 12:09:20 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "The report describes how an unanticipated
                 floating-point NaN caused the steering wheel to lock to
                 its maximum right. From the report: ``the [controller]
                 output values are transferred via control area network
                 (CAN) to the actuators, but there is no definition for
                 a NaN in the CAN specs, so it just transformed it into
                 a normal number, albeit a very large one.''",
  URL =          "https://www.reddit.com/r/formula1/comments/jk9jrg/comment/gai295l/",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2018:FVF
author: Anonymous
title: Formal Verification of Floating-Point Hardware with Assertion-Based VIP
pages: 120--124
year: 2018
bibdate: Fri Sep 28 06:31:32 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.09.28 06:31:32 ???
URL: https://www.onespin.com/fpu/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Anonymous
rawtitle: Formal Verification of Floating-Point Hardware with Assertion-Based {VIP}
remark:
Sections labeled ``Nicolae Tusinschi about Verification of Floating-Point Hardware Designs'' and ``Xilinx verifies Floating-Point Hardware IP with OneSpin FPU App''.

entry:
@Misc{Anonymous:2018:FVF,
  author =       "Anonymous",
  title =        "Formal Verification of Floating-Point Hardware with
                 Assertion-Based {VIP}",
  howpublished = "Web site.",
  year =         "2018",
  bibdate =      "Fri Sep 28 06:31:32 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.onespin.com/fpu/",
  acknowledgement = ack-nhfb,
  remark =       "Sections labeled ``Nicolae Tusinschi about
                 Verification of Floating-Point Hardware Designs'' and
                 ``Xilinx verifies Floating-Point Hardware IP with
                 OneSpin FPU App''.",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2018:HFF
author: Anonymous
title: Herbie: Find and fix floating-point problems
pages: 120--124
year: 2018
bibdate: Thu May 02 16:59:16 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.05.02 16:59:16 ???
URL: https://herbie.uwplse.org/
abstract: Herbie detects inaccurate expressions and finds more accurate replacements.
acknowledgement: ack-nhfb
howpublished: Web site and software source.
rawabstract: Herbie detects inaccurate expressions and finds more accurate replacements.
rawauthor: Anonymous
rawtitle: {Herbie}: Find and fix floating-point problems
entry:
@Misc{Anonymous:2018:HFF,
  author =       "Anonymous",
  title =        "{Herbie}: Find and fix floating-point problems",
  howpublished = "Web site and software source.",
  year =         "2018",
  bibdate =      "Thu May 02 16:59:16 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://herbie.uwplse.org/",
  abstract =     "Herbie detects inaccurate expressions and finds more
                 accurate replacements.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2018:OLA
author: Anonymous
pages: 120--124
day: 27
month: nov
monthnumber: 11
year: 2018
bibdate: Wed Nov 28 10:06:08 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.11.28 10:06:08 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
title:
OneSpin Launches ``App'' for Formal Verification of Floating-Point Hardware Critical for Machine Learning and Deep Learning Chips: Offers Exhaustive Coverage of Floating-Point Arithmetic Operations Compliant with IEEE 754 Standard

URL:
https://globenewswire.com/news-release/2018/11/27/1657662/0/en/OneSpin-Launches-App-for-Formal-Verification-of-Floating-Point-Hardware-Critical-for-Machine-Learning-and-Deep-Learning-Chips.html

rawtitle:
{OneSpin} Launches {``App''} for Formal Verification of Floating-Point Hardware Critical for Machine Learning and Deep Learning Chips: Offers Exhaustive Coverage of Floating-Point Arithmetic Operations Compliant with {IEEE 754 Standard}

entry:
@Misc{Anonymous:2018:OLA,
  author =       "Anonymous",
  title =        "{OneSpin} Launches {``App''} for Formal Verification
                 of Floating-Point Hardware Critical for Machine
                 Learning and Deep Learning Chips: Offers Exhaustive
                 Coverage of Floating-Point Arithmetic Operations
                 Compliant with {IEEE 754 Standard}",
  howpublished = "Web site",
  day =          "27",
  month =        nov,
  year =         "2018",
  bibdate =      "Wed Nov 28 10:06:08 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://globenewswire.com/news-release/2018/11/27/1657662/0/en/OneSpin-Launches-App-for-Formal-Verification-of-Floating-Point-Hardware-Critical-for-Machine-Learning-and-Deep-Learning-Chips.html",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Babuska:2018:REG
author: Ivo Babuska and Gustaf Soderlind
title: On Roundoff Error Growth in Elliptic Problems
journal: j-TOMS
volume: 44
number: 3
pages: 33:1--33:22
month: apr
monthnumber: 4
year: 2018
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3134444
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Oct 5 11:23:12 MDT 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2018.10.05 11:23:12 MDT
URL: https://dl.acm.org/citation.cfm?id=3134444
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 33
journalURL: https://dl.acm.org/loi/toms
rawauthor: Ivo Babuska and Gustaf S{\"o}derlind
rawtitle: On Roundoff Error Growth in Elliptic Problems
abstract:
Large-scale linear systems arise in finite-difference and finite-element discretizations of elliptic problems. With increasing computer performance, ever larger systems are solved using direct methods. How large can such systems be without roundoff compromising accuracy? Here we model roundoff dynamics in standard $ L U $ and $ L D L^T $ decompositions with respect to problem size $N$. For the one-dimensional (1D) Poisson equation with Dirichlet boundary conditions on an equidistant grid, we show that the relative error in the factorized matrix grows like $ O(epsilon sqrt N)$ if roundoffs are modeled as independent, expectation zero random variables. With bias, the growth rate changes to $ O(epsilon N)$. Subsequent back substitution results in typical error growths of $ O(epsilon > N sqrt N)$ and $ O(epsilon N^2)$, respectively. Error growth is governed by the dynamics of the computational process and by the structure of the boundary conditions rather than by the condition number. Computational results are demonstrated in several examples, including a few fourth-order 1D problems and second-order 2D problems, showing that error accumulation depends strongly on the solution method. Thus, the same $ L U$ solver may exhibit different growth rates for the same 2D Poisson problem, depending on whether the five-point or nine-point FDM operator is used.

rawabstract:
Large-scale linear systems arise in finite-difference and finite-element discretizations of elliptic problems. With increasing computer performance, ever larger systems are solved using direct methods. How large can such systems be without roundoff compromising accuracy? Here we model roundoff dynamics in standard $ L U $ and $ L D L^T $ decompositions with respect to problem size $N$. For the one-dimensional (1D) Poisson equation with Dirichlet boundary conditions on an equidistant grid, we show that the relative error in the factorized matrix grows like $ O(\epsilon \sqrt N)$ if roundoffs are modeled as independent, expectation zero random variables. With bias, the growth rate changes to $ O(\epsilon N)$. Subsequent back substitution results in typical error growths of $ O(\epsilon > N \sqrt {N})$ and $ O(\epsilon N^2)$, respectively. Error growth is governed by the dynamics of the computational process and by the structure of the boundary conditions rather than by the condition number. Computational results are demonstrated in several examples, including a few fourth-order 1D problems and second-order 2D problems, showing that error accumulation depends strongly on the solution method. Thus, the same $ L U$ solver may exhibit different growth rates for the same 2D Poisson problem, depending on whether the five-point or nine-point FDM operator is used.

entry:
@Article{Babuska:2018:REG,
  author =       "Ivo Babuska and Gustaf S{\"o}derlind",
  title =        "On Roundoff Error Growth in Elliptic Problems",
  journal =      j-TOMS,
  volume =       "44",
  number =       "3",
  pages =        "33:1--33:22",
  month =        apr,
  year =         "2018",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3134444",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Oct 5 11:23:12 MDT 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3134444",
  abstract =     "Large-scale linear systems arise in finite-difference
                 and finite-element discretizations of elliptic
                 problems. With increasing computer performance, ever
                 larger systems are solved using direct methods. How
                 large can such systems be without roundoff compromising
                 accuracy? Here we model roundoff dynamics in standard $
                 L U $ and $ L D L^T $ decompositions with respect to
                 problem size $N$. For the one-dimensional (1D) Poisson
                 equation with Dirichlet boundary conditions on an
                 equidistant grid, we show that the relative error in
                 the factorized matrix grows like $ O(\epsilon \sqrt N)$
                 if roundoffs are modeled as independent, expectation
                 zero random variables. With bias, the growth rate
                 changes to $ O(\epsilon N)$. Subsequent back
                 substitution results in typical error growths of $
                 O(\epsilon > N \sqrt {N})$ and $ O(\epsilon N^2)$,
                 respectively. Error growth is governed by the dynamics
                 of the computational process and by the structure of
                 the boundary conditions rather than by the condition
                 number. Computational results are demonstrated in
                 several examples, including a few fourth-order 1D
                 problems and second-order 2D problems, showing that
                 error accumulation depends strongly on the solution
                 method. Thus, the same $ L U$ solver may exhibit
                 different growth rates for the same 2D Poisson problem,
                 depending on whether the five-point or nine-point FDM
                 operator is used.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Bajard:2018:MRW
author: Jean-Claude Bajard and Julien Eynard and Nabil Merkiche
title: Montgomery reduction within the context of residue number system arithmetic
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 189--200
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0154-9
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0154-9
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Jean-Claude Bajard and Julien Eynard and Nabil Merkiche
rawtitle: {Montgomery} reduction within the context of residue number system arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib

entry:
@Article{Bajard:2018:MRW,
  author =       "Jean-Claude Bajard and Julien Eynard and Nabil
                 Merkiche",
  title =        "{Montgomery} reduction within the context of residue
                 number system arithmetic",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "189--200",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0154-9",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0154-9",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: inproceedings
filename: fparith.bib
label: Barthel:2018:HIB
author: Moritz Barthel and Jochen Rust and Steffen Paul
booktitle: 2018 52nd Asilomar Conference on Signals, Systems, and Computers
title: Hardware Implementation of Basic Arithmetics and Elementary Functions for Unum Computing
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 125--129
year: 2018
DOI: https://doi.org/10.1109/ACSSC.2018.8645453
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Moritz B{\"a}rthel and Jochen Rust and Steffen Paul
rawbooktitle: {2018 52nd Asilomar Conference on Signals, Systems, and Computers}
rawtitle: Hardware Implementation of Basic Arithmetics and Elementary Functions for Unum Computing
entry:
@InProceedings{Barthel:2018:HIB,
  author =       "Moritz B{\"a}rthel and Jochen Rust and Steffen Paul",
  booktitle =    "{2018 52nd Asilomar Conference on Signals, Systems,
                 and Computers}",
  title =        "Hardware Implementation of Basic Arithmetics and
                 Elementary Functions for Unum Computing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "125--129",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ACSSC.2018.8645453",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Becker:2018:NOS
author: Ruben Becker and Michael Sagraloff and Vikram Sharma and Chee Yap
journal: j-J-SYMBOLIC-COMP
volume: 86
pages: 51--96
month: may
monthnumber: 5
year: 2018
CODEN: JSYCEH
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
bibdate: Wed Nov 22 16:17:19 MST 2017
bibtimestamp: 2017.11.22 16:17:19 MST
URL: http://www.sciencedirect.com/science/article/pii/S0747717117300378
fjournal: Journal of Symbolic Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07477171
rawauthor: Ruben Becker and Michael Sagraloff and Vikram Sharma and Chee Yap
title:
A near-optimal subdivision algorithm for complex root isolation based on the Pellet test and Newton iteration

rawtitle:
A near-optimal subdivision algorithm for complex root isolation based on the {Pellet} test and {Newton} iteration

entry:
@Article{Becker:2018:NOS,
  author =       "Ruben Becker and Michael Sagraloff and Vikram Sharma
                 and Chee Yap",
  title =        "A near-optimal subdivision algorithm for complex root
                 isolation based on the {Pellet} test and {Newton}
                 iteration",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "86",
  number =       "??",
  pages =        "51--96",
  month =        may # "\slash " # jun,
  year =         "2018",
  CODEN =        "JSYCEH",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  bibdate =      "Wed Nov 22 16:17:19 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0747717117300378",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2018:FPA
author: Sylvie Boldo and Florian Faissole and Vincent Tourneur
title: A Formally-Proved Algorithm to Compute the Correct Average of Decimal Floating-Point Numbers
crossref: Tenca:2018:PIS
pages: 69--75
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464761
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Florian Faissole and Vincent Tourneur
rawtitle: A Formally-Proved Algorithm to Compute the Correct Average of Decimal Floating-Point Numbers
abstract:
Some modern processors include decimal floating-point units, with a conforming implementation of the IEEE-754 2008 standard. Unfortunately, many algorithms from the computer arithmetic literature are not correct anymore when computations are done in radix 10. This is in particular the case for the computation of the average of two floating-point numbers. Several radix-2 algorithms are available, including one that provides the correct rounding, but none hold in radix 10. This paper presents a new radix-10 algorithm that computes the correctly-rounded average. To guarantee a higher level of confidence, we also provide a Coq formal proof of our theorems, that takes gradual underflow into account. Note that our formal proof was generalized to ensure this algorithm is correct when computations are done with any even radix.

keywords:
ARITH-25; Coq formal proof; correct rounding; correctly-rounded average; decimal floating-point numbers; decimal floating-point units; Digital arithmetic; floating point arithmetic; formally-proved algorithm; Hardware; IEEE standards; IEEE-754 2008 standard; Libraries; Program processors; radix-10 algorithm; radix-2 algorithms; Software algorithms; Standards; theorem proving

rawabstract:
Some modern processors include decimal floating-point units, with a conforming implementation of the IEEE-754 2008 standard. Unfortunately, many algorithms from the computer arithmetic literature are not correct anymore when computations are done in radix 10. This is in particular the case for the computation of the average of two floating-point numbers. Several radix-2 algorithms are available, including one that provides the correct rounding, but none hold in radix 10. This paper presents a new radix-10 algorithm that computes the correctly-rounded average. To guarantee a higher level of confidence, we also provide a Coq formal proof of our theorems, that takes gradual underflow into account. Note that our formal proof was generalized to ensure this algorithm is correct when computations are done with any even radix.

entry:
@InProceedings{Boldo:2018:FPA,
  author =       "Sylvie Boldo and Florian Faissole and Vincent
                 Tourneur",
  title =        "A Formally-Proved Algorithm to Compute the Correct
                 Average of Decimal Floating-Point Numbers",
  crossref =     "Tenca:2018:PIS",
  pages =        "69--75",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464761",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Some modern processors include decimal floating-point
                 units, with a conforming implementation of the IEEE-754
                 2008 standard. Unfortunately, many algorithms from the
                 computer arithmetic literature are not correct anymore
                 when computations are done in radix 10. This is in
                 particular the case for the computation of the average
                 of two floating-point numbers. Several radix-2
                 algorithms are available, including one that provides
                 the correct rounding, but none hold in radix 10. This
                 paper presents a new radix-10 algorithm that computes
                 the correctly-rounded average. To guarantee a higher
                 level of confidence, we also provide a Coq formal proof
                 of our theorems, that takes gradual underflow into
                 account. Note that our formal proof was generalized to
                 ensure this algorithm is correct when computations are
                 done with any even radix.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; Coq formal proof; correct rounding;
                 correctly-rounded average; decimal floating-point
                 numbers; decimal floating-point units; Digital
                 arithmetic; floating point arithmetic; formally-proved
                 algorithm; Hardware; IEEE standards; IEEE-754 2008
                 standard; Libraries; Program processors; radix-10
                 algorithm; radix-2 algorithms; Software algorithms;
                 Standards; theorem proving",
}


bibtype: misc
filename: fparith.bib
label: Bradbury:2018:RSR
author: Jonathan D. Bradbury and Steven R. Carlough and Brian R. Prasky and Eric M. Schwarz
title: Reproducible stochastic rounding for out of order processors
pages: 69--75
day: 23
month: jul
monthnumber: 7
year: 2018
bibdate: Fri Sep 22 17:33:27 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib
bibtimestamp: 2023.09.22 17:33:27 ???
note: Patent granted 19 February 2019; expired (fee related)
acknowledgement: ack-nhfb
howpublished: U.S. Patent US10209958B2
rawauthor: Jonathan D. Bradbury and Steven R. Carlough and Brian R. Prasky and Eric M. Schwarz
rawnote: Patent granted 19 February 2019; expired (fee related)
rawtitle: Reproducible stochastic rounding for out of order processors
abstract:
A method for generating a random number for use in a stochastic rounding operation is provided. The method includes executing an instruction that causes at least two operands to produce an intermediate result and incrementing a state of a random number generator. The method further includes causing the random number generator to generate a random number in accordance with the state and producing a final result by utilizing the random number to determine a rounding of the intermediate result.

rawabstract:
A method for generating a random number for use in a stochastic rounding operation is provided. The method includes executing an instruction that causes at least two operands to produce an intermediate result and incrementing a state of a random number generator. The method further includes causing the random number generator to generate a random number in accordance with the state and producing a final result by utilizing the random number to determine a rounding of the intermediate result.

entry:
@Misc{Bradbury:2018:RSR,
  author =       "Jonathan D. Bradbury and Steven R. Carlough and Brian
                 R. Prasky and Eric M. Schwarz",
  title =        "Reproducible stochastic rounding for out of order
                 processors",
  howpublished = "U.S. Patent US10209958B2",
  day =          "23",
  month =        jul,
  year =         "2018",
  bibdate =      "Fri Sep 22 17:33:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  note =         "Patent granted 19 February 2019; expired (fee
                 related)",
  abstract =     "A method for generating a random number for use in a
                 stochastic rounding operation is provided. The method
                 includes executing an instruction that causes at least
                 two operands to produce an intermediate result and
                 incrementing a state of a random number generator. The
                 method further includes causing the random number
                 generator to generate a random number in accordance
                 with the state and producing a final result by
                 utilizing the random number to determine a rounding of
                 the intermediate result.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2018:HTP
title: A High Throughput Polynomial and Rational Function Approximations Evaluator
crossref: Tenca:2018:PIS
pages: 99--106
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464778
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawtitle: A High Throughput Polynomial and Rational Function Approximations Evaluator
author:
Nicolas Brisebarre and George Constantinides and Milos Ercezovac and Silviu-Ioan Filip and Matei Istoan and Jean-Michel Muller

abstract:
We present an automatic method for the evaluation of functions via polynomial or rational approximations and its hardware implementation, on FPGAs. These approximations are evaluated using Ercegovac's iterative E-method adapted for FPGA implementation. The polynomial and rational function coefficients are optimized such that they satisfy the constraints of the E-method. We present several examples of practical interest; in each case a resource-efficient approximation is proposed and comparisons are made with alternative approaches.

keywords:
Approximation algorithms; approximation theory; ARITH-25; Convergence; Electronic mail; Ercegovac iterative E-method; field programmable gate arrays; Field programmable gate arrays; FPGA implementation; function approximation; Hardware; hardware implementation; Lattices; Linear systems; polynomial function approximations evaluator; polynomials; rational function approximations evaluator; rational functions; resource-efficient approximation

rawabstract:
We present an automatic method for the evaluation of functions via polynomial or rational approximations and its hardware implementation, on FPGAs. These approximations are evaluated using Ercegovac's iterative E-method adapted for FPGA implementation. The polynomial and rational function coefficients are optimized such that they satisfy the constraints of the E-method. We present several examples of practical interest; in each case a resource-efficient approximation is proposed and comparisons are made with alternative approaches.

rawauthor:
Nicolas Brisebarre and George Constantinides and Milo{\v{s}} Ercezovac and Silviu-Ioan Filip and Matei Istoan and Jean-Michel Muller

entry:
@InProceedings{Brisebarre:2018:HTP,
  author =       "Nicolas Brisebarre and George Constantinides and
                 Milo{\v{s}} Ercezovac and Silviu-Ioan Filip and Matei
                 Istoan and Jean-Michel Muller",
  title =        "A High Throughput Polynomial and Rational Function
                 Approximations Evaluator",
  crossref =     "Tenca:2018:PIS",
  pages =        "99--106",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464778",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present an automatic method for the evaluation of
                 functions via polynomial or rational approximations and
                 its hardware implementation, on FPGAs. These
                 approximations are evaluated using Ercegovac's
                 iterative E-method adapted for FPGA implementation. The
                 polynomial and rational function coefficients are
                 optimized such that they satisfy the constraints of the
                 E-method. We present several examples of practical
                 interest; in each case a resource-efficient
                 approximation is proposed and comparisons are made with
                 alternative approaches.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; approximation theory;
                 ARITH-25; Convergence; Electronic mail; Ercegovac
                 iterative E-method; field programmable gate arrays;
                 Field programmable gate arrays; FPGA implementation;
                 function approximation; Hardware; hardware
                 implementation; Lattices; Linear systems; polynomial
                 function approximations evaluator; polynomials;
                 rational function approximations evaluator; rational
                 functions; resource-efficient approximation",
}


bibtype: inproceedings
filename: fparith.bib
label: Bruguera:2018:PII
author: J. D. Bruguera
booktitle: Proceedings of the 25th IEEE International Symposium on Computer Arithmetic
title: Radix-64 floating-point divider
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 87--94
year: 2018
bibdate: Thu Jan 30 16:14:30 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.30 16:14:30 ???
acknowledgement: ack-nhfb
rawauthor: J. D. Bruguera
rawbooktitle: Proceedings of the {25th IEEE International Symposium on Computer Arithmetic}
rawtitle: Radix-64 floating-point divider
entry:
@InProceedings{Bruguera:2018:PII,
  author =       "J. D. Bruguera",
  booktitle =    "Proceedings of the {25th IEEE International Symposium
                 on Computer Arithmetic}",
  title =        "Radix-64 floating-point divider",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "87--94",
  year =         "2018",
  bibdate =      "Thu Jan 30 16:14:30 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Bruguera:2018:RFP
author: Javier D. Bruguera
title: Radix-64 Floating-Point Divider
crossref: Tenca:2018:PIS
pages: 84--91
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464815
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Javier D. Bruguera
rawtitle: Radix-64 Floating-Point Divider
abstract:
The following topics are dealt with: floating point arithmetic; digital arithmetic; IEEE standards; field programmable gate arrays; learning (artificial intelligence); cryptography; parallel processing; table lookup; multiplying circuits; mathematics computing.

keywords:
Adders; ARITH-25; artificial intelligence; Convergence; cryptography; digital arithmetic; Digital arithmetic; field programmable gate arrays; floating point arithmetic; IEEE standards; learning; learning (artificial intelligence); Mathematical model; mathematics computing; multiplying circuits; parallel processing; Program processors; table lookup; Timing; Two dimensional displays

rawabstract:
The following topics are dealt with: floating point arithmetic; digital arithmetic; IEEE standards; field programmable gate arrays; learning (artificial intelligence); cryptography; parallel processing; table lookup; multiplying circuits; mathematics computing.

entry:
@InProceedings{Bruguera:2018:RFP,
  author =       "Javier D. Bruguera",
  title =        "Radix-64 Floating-Point Divider",
  crossref =     "Tenca:2018:PIS",
  pages =        "84--91",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464815",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The following topics are dealt with: floating point
                 arithmetic; digital arithmetic; IEEE standards; field
                 programmable gate arrays; learning (artificial
                 intelligence); cryptography; parallel processing; table
                 lookup; multiplying circuits; mathematics computing.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-25; artificial intelligence;
                 Convergence; cryptography; digital arithmetic; Digital
                 arithmetic; field programmable gate arrays; floating
                 point arithmetic; IEEE standards; learning; learning
                 (artificial intelligence); Mathematical model;
                 mathematics computing; multiplying circuits; parallel
                 processing; Program processors; table lookup; Timing;
                 Two dimensional displays",
}


bibtype: article
filename: fparith.bib
label: Cannizzo:2018:FVA
author: Fabio Cannizzo
journal: j-J-PAR-DIST-COMP
volume: 113
pages: 37--54
month: mar
monthnumber: 3
year: 2018
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Jan 13 12:26:41 MST 2018
bibtimestamp: 2018.01.13 12:26:41 MST
URL: http://www.sciencedirect.com/science/article/pii/S0743731517302836
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: Fabio Cannizzo
title:
A fast and vectorizable alternative to binary search in $ O(1) $ with wide applicability to arrays of floating point numbers

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib

rawtitle:
A fast and vectorizable alternative to binary search in {$ O(1) $} with wide applicability to arrays of floating point numbers

entry:
@Article{Cannizzo:2018:FVA,
  author =       "Fabio Cannizzo",
  title =        "A fast and vectorizable alternative to binary search
                 in {$ O(1) $} with wide applicability to arrays of
                 floating point numbers",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "113",
  number =       "??",
  pages =        "37--54",
  month =        mar,
  year =         "2018",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Jan 13 12:26:41 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0743731517302836",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: article
filename: fparith.bib
label: Canto-Navarro:2018:FPA
author: E. Canto-Navarro and M. Lopez-Garcia and R. Ramos-Lara
title: Floating-point accelerator for biometric recognition on FPGA embedded systems
journal: j-J-PAR-DIST-COMP
volume: 112 (part 1)
pages: 20--34
month: feb
monthnumber: 2
year: 2018
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Fri Nov 24 17:01:13 MST 2017
bibtimestamp: 2017.11.24 17:01:13 MST
URL: http://www.sciencedirect.com/science/article/pii/S0743731517302642
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: E. Cant{\'o}-Navarro and M. L{\'o}pez-Garc{\'\i}a and R. Ramos-Lara
rawtitle: Floating-point accelerator for biometric recognition on {FPGA} embedded systems
entry:
@Article{Canto-Navarro:2018:FPA,
  author =       "E. Cant{\'o}-Navarro and M. L{\'o}pez-Garc{\'\i}a and
                 R. Ramos-Lara",
  title =        "Floating-point accelerator for biometric recognition
                 on {FPGA} embedded systems",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "112 (part 1)",
  number =       "??",
  pages =        "20--34",
  month =        feb,
  year =         "2018",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Fri Nov 24 17:01:13 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0743731517302642",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: inproceedings
filename: fparith.bib
label: Chatelain:2018:VCE
title: VeriTracer: Context-enriched tracer for floating-point arithmetic analysis
crossref: Tenca:2018:PIS
pages: 61--68
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464687
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawtitle: {VeriTracer}: Context-enriched tracer for floating-point arithmetic analysis
author:
Yohan Chatelain and Pablo De Oliveira Castro and Eric Petit and David Defour and Jordan Bieder and Marc Torrent

abstract:
VeriTracer automatically instruments a code and traces the accuracy of floating-point variables over time. VeriTracer enriches the visual traces with contextual information such as the call site path in which a value was modified. Contextual information is important to understand how the floating-point errors propagate in complex codes. VeriTracer is implemented as an LLVM compiler tool on top of Verificarlo. We demonstrate how VeriTracer can detect accuracy loss and quantify the impact of using a compensated algorithm on ABINIT, an industrial HPC application for Ab Initio quantum computation.

keywords:
ab initio calculations; Ab Initio quantum computation; ABINIT; ARITH-25; complex codes; Computational modeling; Computer bugs; Context-enriched tracer; contextual information; floating point arithmetic; floating-point arithmetic analysis; floating-point errors; floating-point variables; industrial HPC application; LLVM compiler; Numerical models; parallel processing; Probes; program compilers; quantum computing; Tools; Verificarlo; VeriTracer; visual traces; Visualization

rawabstract:
VeriTracer automatically instruments a code and traces the accuracy of floating-point variables over time. VeriTracer enriches the visual traces with contextual information such as the call site path in which a value was modified. Contextual information is important to understand how the floating-point errors propagate in complex codes. VeriTracer is implemented as an LLVM compiler tool on top of Verificarlo. We demonstrate how VeriTracer can detect accuracy loss and quantify the impact of using a compensated algorithm on ABINIT, an industrial HPC application for Ab Initio quantum computation.

rawauthor:
Yohan Chatelain and Pablo {De Oliveira Castro} and Eric Petit and David Defour and Jordan Bieder and Marc Torrent

entry:
@InProceedings{Chatelain:2018:VCE,
  author =       "Yohan Chatelain and Pablo {De Oliveira Castro} and
                 Eric Petit and David Defour and Jordan Bieder and Marc
                 Torrent",
  title =        "{VeriTracer}: Context-enriched tracer for
                 floating-point arithmetic analysis",
  crossref =     "Tenca:2018:PIS",
  pages =        "61--68",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464687",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "VeriTracer automatically instruments a code and traces
                 the accuracy of floating-point variables over time.
                 VeriTracer enriches the visual traces with contextual
                 information such as the call site path in which a value
                 was modified. Contextual information is important to
                 understand how the floating-point errors propagate in
                 complex codes. VeriTracer is implemented as an LLVM
                 compiler tool on top of Verificarlo. We demonstrate how
                 VeriTracer can detect accuracy loss and quantify the
                 impact of using a compensated algorithm on ABINIT, an
                 industrial HPC application for Ab Initio quantum
                 computation.",
  acknowledgement = ack-nhfb,
  keywords =     "ab initio calculations; Ab Initio quantum computation;
                 ABINIT; ARITH-25; complex codes; Computational
                 modeling; Computer bugs; Context-enriched tracer;
                 contextual information; floating point arithmetic;
                 floating-point arithmetic analysis; floating-point
                 errors; floating-point variables; industrial HPC
                 application; LLVM compiler; Numerical models; parallel
                 processing; Probes; program compilers; quantum
                 computing; Tools; Verificarlo; VeriTracer; visual
                 traces; Visualization",
}


bibtype: inproceedings
filename: fparith.bib
label: Chaurasiya:2018:PPA
editor: IEEE
booktitle: 2018 IEEE 36th International Conference on Computer Design (ICCD)
title: Parameterized Posit Arithmetic Hardware Generator
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 334--341
year: 2018
DOI: https://doi.org/10.1109/ICCD.2018.00057
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2018 IEEE 36th International Conference on Computer Design (ICCD)}
raweditor: {IEEE}
rawtitle: Parameterized Posit Arithmetic Hardware Generator
author:
Rohit Chaurasiya and John Gustafson and Rahul Shrestha and Jonathan Neudorfer and Sangeeth Nambiar and Kaustav Niyogi and Farhad Merchant and Rainer Leupers

rawauthor:
Rohit Chaurasiya and John Gustafson and Rahul Shrestha and Jonathan Neudorfer and Sangeeth Nambiar and Kaustav Niyogi and Farhad Merchant and Rainer Leupers

entry:
@InProceedings{Chaurasiya:2018:PPA,
  author =       "Rohit Chaurasiya and John Gustafson and Rahul Shrestha
                 and Jonathan Neudorfer and Sangeeth Nambiar and Kaustav
                 Niyogi and Farhad Merchant and Rainer Leupers",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE 36th International Conference on Computer
                 Design (ICCD)}",
  title =        "Parameterized Posit Arithmetic Hardware Generator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "334--341",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ICCD.2018.00057",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2018:MMU
author: Jianyu Chen and Zaid Al-Ars
title: A Matrix-Multiply Unit for Posits in Reconfigurable Logic Using (OPEN)CAPI
crossref: ACM:2018:CNG
pages: 1--5
year: 2018
DOI: https://doi.org/10.1145/3190339.3190340
bibdate: Mon Dec 11 08:58:21 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 08:58:21 ???
keywords: posit arithmetic; universal number (unum) arithmetic
acknowledgement: ack-nhfb
articleno: 1
rawauthor: Jianyu Chen and Zaid Al-Ars
rawtitle: A Matrix-Multiply Unit for Posits in Reconfigurable Logic Using {(OPEN)CAPI}
entry:
@InProceedings{Chen:2018:MMU,
  author =       "Jianyu Chen and Zaid Al-Ars",
  title =        "A Matrix-Multiply Unit for Posits in Reconfigurable
                 Logic Using {(OPEN)CAPI}",
  crossref =     "ACM:2018:CNG",
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190340",
  bibdate =      "Mon Dec 11 08:58:21 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  keywords =     "posit arithmetic; universal number (unum) arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Cherkaev:2018:SLN
author: Annie Cherkaev
title: The secret life of NaN
pages: 1--5
month: mar
monthnumber: 3
year: 2018
bibdate: Fri Dec 01 14:21:50 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.01 14:21:50 ???
URL: https://anniecherkaev.com/the-secret-life-of-nan
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Annie Cherkaev
rawtitle: The secret life of {NaN}
remark:
The site discusses IEEE 754 number encoding, and how NaN payloads can be used to hold other things, like data type codes, integers, and pointers, hidden inside binary64 values.

entry:
@Misc{Cherkaev:2018:SLN,
  author =       "Annie Cherkaev",
  title =        "The secret life of {NaN}",
  howpublished = "Web site",
  month =        mar,
  year =         "2018",
  bibdate =      "Fri Dec 01 14:21:50 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://anniecherkaev.com/the-secret-life-of-nan",
  acknowledgement = ack-nhfb,
  remark =       "The site discusses IEEE 754 number encoding, and how
                 NaN payloads can be used to hold other things, like
                 data type codes, integers, and pointers, hidden inside
                 binary64 values.",
}


bibtype: inproceedings
filename: fparith.bib
label: Chung:2018:PCP
author: Shin Yee Chung
title: Provably Correct Posit Arithmetic with Fixed-Point Big Integer
crossref: ACM:2018:CNG
pages: 1--5
year: 2018
DOI: https://doi.org/10.1145/3190339.3190341
bibdate: Mon Dec 11 09:00:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 09:00:40 ???
keywords: posit arithmetic; universal number (unum) arithmetic
acknowledgement: ack-nhfb
articleno: 2
rawauthor: Shin Yee Chung
rawtitle: Provably Correct Posit Arithmetic with Fixed-Point Big Integer
entry:
@InProceedings{Chung:2018:PCP,
  author =       "Shin Yee Chung",
  title =        "Provably Correct Posit Arithmetic with Fixed-Point Big
                 Integer",
  crossref =     "ACM:2018:CNG",
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190341",
  bibdate =      "Mon Dec 11 09:00:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  keywords =     "posit arithmetic; universal number (unum) arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Cococcioni:2018:EPA
author: Marco Cococcioni and Emanuele Ruffaldi and Sergio Saponara
editor: IEEE
booktitle: 2018 International Conference of Electrical and Electronic Technologies for Automotive
title: Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2018
DOI: https://doi.org/10.23919/EETA.2018.8493233
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Emanuele Ruffaldi and Sergio Saponara
rawbooktitle: {2018 International Conference of Electrical and Electronic Technologies for Automotive}
raweditor: {IEEE}
rawtitle: Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications
entry:
@InProceedings{Cococcioni:2018:EPA,
  author =       "Marco Cococcioni and Emanuele Ruffaldi and Sergio
                 Saponara",
  editor =       "{IEEE}",
  booktitle =    "{2018 International Conference of Electrical and
                 Electronic Technologies for Automotive}",
  title =        "Exploiting Posit Arithmetic for Deep Neural Networks
                 in Autonomous Driving Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2018",
  DOI =          "https://doi.org/10.23919/EETA.2018.8493233",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Costello:2018:MCT
author: Craig Costello and Benjamin Smith
title: Montgomery curves and their arithmetic
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 227--240
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0157-6
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0157-6
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Craig Costello and Benjamin Smith
rawtitle: {Montgomery} curves and their arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib

entry:
@Article{Costello:2018:MCT,
  author =       "Craig Costello and Benjamin Smith",
  title =        "{Montgomery} curves and their arithmetic",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "227--240",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0157-6",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0157-6",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Dai:2018:FBM
author: Wangchen Dai and Donglong Chen and Ray C. C. Cheung and Cetin Kaya Koc
title: FFT-Based McLaughlin's Montgomery Exponentiation without Conditional Selections
journal: j-IEEE-TRANS-COMPUT
volume: 67
number: 9
pages: 1301--1314
month: sep
monthnumber: 9
year: 2018
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2811466
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Mar 15 08:10:13 2019
bibtimestamp: 2019.03.15 08:10:13 ???
URL: https://ieeexplore.ieee.org/document/8307235/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Wangchen Dai and Donglong Chen and Ray C. C. Cheung and {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: {FFT}-Based {McLaughlin}'s {Montgomery} Exponentiation without Conditional Selections
entry:
@Article{Dai:2018:FBM,
  author =       "Wangchen Dai and Donglong Chen and Ray C. C. Cheung
                 and {\c{C}}etin Kaya Ko{\c{c}}",
  title =        "{FFT}-Based {McLaughlin}'s {Montgomery} Exponentiation
                 without Conditional Selections",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "67",
  number =       "9",
  pages =        "1301--1314",
  month =        sep,
  year =         "2018",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2811466",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Mar 15 08:10:13 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://ieeexplore.ieee.org/document/8307235/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Dai:2018:SAM
author: Wangchen Dai and Ray C. C. Cheung
title: Spectral arithmetic in Montgomery modular multiplication
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 211--226
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0151-z
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0151-z
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Wangchen Dai and Ray C. C. Cheung
rawtitle: Spectral arithmetic in {Montgomery} modular multiplication
entry:
@Article{Dai:2018:SAM,
  author =       "Wangchen Dai and Ray C. C. Cheung",
  title =        "Spectral arithmetic in {Montgomery} modular
                 multiplication",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "211--226",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0151-z",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0151-z",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Das:2018:MPT
title: Mixed Precision Training of Convolutional Neural Networks using Integer Operations
journal: arXiv.org
pages: 11
day: 3
month: feb
monthnumber: 2
year: 2018
bibdate: Mon Feb 10 09:24:48 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 09:24:48 ???
URL: https://arxiv.org/abs/1802.00930
acknowledgement: ack-nhfb
rawtitle: Mixed Precision Training of Convolutional Neural Networks using Integer Operations
author:
Dipankar Das and Naveen Mellempudi and Dheevatsa Mudigere and Dhiraj Kalamkar and Sasikanth Avancha and Kunal Banerjee and Srinivas Sridharan and Karthik Vaidyanathan and Bharat Kaul and Evangelos Georganas and Alexander Heinecke and Pradeep Dubey and Jesus Corbal and Nikita Shustrov and Roma Dubtsov and Evarist Fomenko and Vadim Pirogov

abstract:
The state-of-the-art (SOTA) for mixed precision training is dominated by variants of low precision floating point operations, and in particular, FP16 accumulating into FP32 Micikevicius et al. (2017). On the other hand, while a lot of research has also happened in the domain of low and mixed-precision Integer training, these works either present results for non-SOTA networks (for instance only AlexNet for ImageNet-1K), or relatively small datasets (like CIFAR-10). In this work, we train state-of-the-art visual understanding neural networks on the ImageNet-1K dataset, with Integer operations on General Purpose (GP) hardware. In particular, we focus on Integer Fused-Multiply-and-Accumulate (FMA) operations which take two pairs of INT16 operands and accumulate results into an INT32 output.We propose a shared exponent representation of tensors and develop a Dynamic Fixed Point (DFP) scheme suitable for common neural network operations. The nuances of developing an efficient integer convolution kernel is examined, including methods to handle overflow of the INT32 accumulator. We implement CNN training for ResNet-50, GoogLeNet-v1, VGG-16 and AlexNet; and these networks achieve or exceed SOTA accuracy within the same number of iterations as their FP32 counterparts without any change in hyper-parameters and with a 1.8X improvement in end-to-end training throughput. To the best of our knowledge these results represent the first INT16 training results on GP hardware for ImageNet-1K dataset using SOTA CNNs and achieve highest reported accuracy using half-precision

rawabstract:
The state-of-the-art (SOTA) for mixed precision training is dominated by variants of low precision floating point operations, and in particular, FP16 accumulating into FP32 Micikevicius et al. (2017). On the other hand, while a lot of research has also happened in the domain of low and mixed-precision Integer training, these works either present results for non-SOTA networks (for instance only AlexNet for ImageNet-1K), or relatively small datasets (like CIFAR-10). In this work, we train state-of-the-art visual understanding neural networks on the ImageNet-1K dataset, with Integer operations on General Purpose (GP) hardware. In particular, we focus on Integer Fused-Multiply-and-Accumulate (FMA) operations which take two pairs of INT16 operands and accumulate results into an INT32 output.We propose a shared exponent representation of tensors and develop a Dynamic Fixed Point (DFP) scheme suitable for common neural network operations. The nuances of developing an efficient integer convolution kernel is examined, including methods to handle overflow of the INT32 accumulator. We implement CNN training for ResNet-50, GoogLeNet-v1, VGG-16 and AlexNet; and these networks achieve or exceed SOTA accuracy within the same number of iterations as their FP32 counterparts without any change in hyper-parameters and with a 1.8X improvement in end-to-end training throughput. To the best of our knowledge these results represent the first INT16 training results on GP hardware for ImageNet-1K dataset using SOTA CNNs and achieve highest reported accuracy using half-precision

rawauthor:
Dipankar Das and Naveen Mellempudi and Dheevatsa Mudigere and Dhiraj Kalamkar and Sasikanth Avancha and Kunal Banerjee and Srinivas Sridharan and Karthik Vaidyanathan and Bharat Kaul and Evangelos Georganas and Alexander Heinecke and Pradeep Dubey and Jesus Corbal and Nikita Shustrov and Roma Dubtsov and Evarist Fomenko and Vadim Pirogov

entry:
@Article{Das:2018:MPT,
  author =       "Dipankar Das and Naveen Mellempudi and Dheevatsa
                 Mudigere and Dhiraj Kalamkar and Sasikanth Avancha and
                 Kunal Banerjee and Srinivas Sridharan and Karthik
                 Vaidyanathan and Bharat Kaul and Evangelos Georganas
                 and Alexander Heinecke and Pradeep Dubey and Jesus
                 Corbal and Nikita Shustrov and Roma Dubtsov and Evarist
                 Fomenko and Vadim Pirogov",
  title =        "Mixed Precision Training of Convolutional Neural
                 Networks using Integer Operations",
  journal =      "arXiv.org",
  pages =        "11",
  day =          "3",
  month =        feb,
  year =         "2018",
  bibdate =      "Mon Feb 10 09:24:48 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1802.00930",
  abstract =     "The state-of-the-art (SOTA) for mixed precision
                 training is dominated by variants of low precision
                 floating point operations, and in particular, FP16
                 accumulating into FP32 Micikevicius et al. (2017). On
                 the other hand, while a lot of research has also
                 happened in the domain of low and mixed-precision
                 Integer training, these works either present results
                 for non-SOTA networks (for instance only AlexNet for
                 ImageNet-1K), or relatively small datasets (like
                 CIFAR-10). In this work, we train state-of-the-art
                 visual understanding neural networks on the ImageNet-1K
                 dataset, with Integer operations on General Purpose
                 (GP) hardware. In particular, we focus on Integer
                 Fused-Multiply-and-Accumulate (FMA) operations which
                 take two pairs of INT16 operands and accumulate results
                 into an INT32 output.We propose a shared exponent
                 representation of tensors and develop a Dynamic Fixed
                 Point (DFP) scheme suitable for common neural network
                 operations. The nuances of developing an efficient
                 integer convolution kernel is examined, including
                 methods to handle overflow of the INT32 accumulator. We
                 implement CNN training for ResNet-50, GoogLeNet-v1,
                 VGG-16 and AlexNet; and these networks achieve or
                 exceed SOTA accuracy within the same number of
                 iterations as their FP32 counterparts without any
                 change in hyper-parameters and with a 1.8X improvement
                 in end-to-end training throughput. To the best of our
                 knowledge these results represent the first INT16
                 training results on GP hardware for ImageNet-1K dataset
                 using SOTA CNNs and achieve highest reported accuracy
                 using half-precision",
  acknowledgement = ack-nhfb,
  primaryclass = "cs.NE",
}


bibtype: inproceedings
filename: fparith.bib
label: Defour:2018:FAR
author: David Defour
title: FP-ANR: A representation format to handle floating-point cancellation at run-time
crossref: Tenca:2018:PIS
pages: 76--83
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464784
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: David Defour
rawtitle: {FP-ANR}: A representation format to handle floating-point cancellation at run-time
abstract:
When dealing with floating-point numbers, there are several sources of error which can drastically reduce the numerical quality of computed results. One of those error sources is the loss of significance or cancellation, which occurs during for example, the subtraction of two nearly equal numbers. In this article, we propose a representation format named Floating-Point Adaptive Noise Reduction (FP-ANR). This format embeds cancellation information directly into the floating-point representation format thanks to a dedicated pattern. With this format, insignificant trailing bits lost during cancellation are removed from every manipulated floating-point number. The immediate consequence is that it increases the numerical confidence of computed values. The proposed representation format corresponds to a simple and efficient implementation of significance arithmetic based and compatible with the IEEE Standard 754 standard.

keywords:
adaptive signal processing; ARITH-25; cancellation information; Computers; Encoding; floating point arithmetic; Floating-Point Adaptive Noise Reduction; floating-point cancellation; floating-point numbers; floating-point representation format; FP-ANR; IEEE Standard 754 standard; IEEE standards; IEEE Standards; interference suppression; Noise reduction; numerical quality; signal denoising; Software; Uncertainty

rawabstract:
When dealing with floating-point numbers, there are several sources of error which can drastically reduce the numerical quality of computed results. One of those error sources is the loss of significance or cancellation, which occurs during for example, the subtraction of two nearly equal numbers. In this article, we propose a representation format named Floating-Point Adaptive Noise Reduction (FP-ANR). This format embeds cancellation information directly into the floating-point representation format thanks to a dedicated pattern. With this format, insignificant trailing bits lost during cancellation are removed from every manipulated floating-point number. The immediate consequence is that it increases the numerical confidence of computed values. The proposed representation format corresponds to a simple and efficient implementation of significance arithmetic based and compatible with the IEEE Standard 754 standard.

entry:
@InProceedings{Defour:2018:FAR,
  author =       "David Defour",
  title =        "{FP-ANR}: A representation format to handle
                 floating-point cancellation at run-time",
  crossref =     "Tenca:2018:PIS",
  pages =        "76--83",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464784",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "When dealing with floating-point numbers, there are
                 several sources of error which can drastically reduce
                 the numerical quality of computed results. One of those
                 error sources is the loss of significance or
                 cancellation, which occurs during for example, the
                 subtraction of two nearly equal numbers. In this
                 article, we propose a representation format named
                 Floating-Point Adaptive Noise Reduction (FP-ANR). This
                 format embeds cancellation information directly into
                 the floating-point representation format thanks to a
                 dedicated pattern. With this format, insignificant
                 trailing bits lost during cancellation are removed from
                 every manipulated floating-point number. The immediate
                 consequence is that it increases the numerical
                 confidence of computed values. The proposed
                 representation format corresponds to a simple and
                 efficient implementation of significance arithmetic
                 based and compatible with the IEEE Standard 754
                 standard.",
  acknowledgement = ack-nhfb,
  keywords =     "adaptive signal processing; ARITH-25; cancellation
                 information; Computers; Encoding; floating point
                 arithmetic; Floating-Point Adaptive Noise Reduction;
                 floating-point cancellation; floating-point numbers;
                 floating-point representation format; FP-ANR; IEEE
                 Standard 754 standard; IEEE standards; IEEE Standards;
                 interference suppression; Noise reduction; numerical
                 quality; signal denoising; Software; Uncertainty",
}


bibtype: article
filename: fparith.bib
label: Demmel:2018:RBM
author: James Demmel and Jason Riedy and Peter Ahrens
title: Reproducible BLAS: Make Addition Associative Again!
journal: j-SIAM-NEWS
volume: 51
number: 8
pages: ??--??
month: oct
monthnumber: 10
year: 2018
ISSN: 0036-1437 OR 00361437
ISSNL: 0036-1437 OR 00361437
bibdate: Sat Oct 06 08:42:06 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.10.06 08:42:06 ???
URL: https://sinews.siam.org/Details-Page/reproducible-blas-make-addition-associative-again
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: http://www.siam.org/news/
rawauthor: James Demmel and Jason Riedy and Peter Ahrens
rawtitle: {Reproducible BLAS}: Make Addition Associative Again!
entry:
@Article{Demmel:2018:RBM,
  author =       "James Demmel and Jason Riedy and Peter Ahrens",
  title =        "{Reproducible BLAS}: Make Addition Associative
                 Again!",
  journal =      j-SIAM-NEWS,
  volume =       "51",
  number =       "8",
  pages =        "??--??",
  month =        oct,
  year =         "2018",
  ISSN =         "0036-1437",
  ISSN-L =       "0036-1437",
  bibdate =      "Sat Oct 06 08:42:06 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/reproducible-blas-make-addition-associative-again",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "http://www.siam.org/news/",
}


bibtype: article
filename: fparith.bib
label: Dolbeau:2018:TPF
author: Romain Dolbeau
title: Theoretical peak FLOPS per instruction set: a tutorial
journal: j-J-SUPERCOMPUTING
volume: 74
number: 3
pages: 1341--1377
month: mar
monthnumber: 3
year: 2018
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-017-2177-5
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Fri Mar 2 12:22:02 MST 2018
bibtimestamp: 2018.03.02 12:22:02 MST
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: Romain Dolbeau
rawtitle: Theoretical peak {FLOPS} per instruction set: a tutorial
bibsource:
http://link.springer.com/journal/11227/74/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper2010.bib; https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib

entry:
@Article{Dolbeau:2018:TPF,
  author =       "Romain Dolbeau",
  title =        "Theoretical peak {FLOPS} per instruction set: a
                 tutorial",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "74",
  number =       "3",
  pages =        "1341--1377",
  month =        mar,
  year =         "2018",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-017-2177-5",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Fri Mar 2 12:22:02 MST 2018",
  bibsource =    "http://link.springer.com/journal/11227/74/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: article
filename: fparith.bib
label: Doliskani:2018:SCR
author: Javad Doliskani and Pascal Giorgi and Romain Lebreton and Eric Schost
title: Simultaneous Conversions with the Residue Number System Using Linear Algebra
journal: j-TOMS
volume: 44
number: 3
pages: 27:1--27:21
month: apr
monthnumber: 4
year: 2018
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3145573
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon Jan 22 17:49:32 MST 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2018.01.22 17:49:32 MST
URL: https://dl.acm.org/citation.cfm?id=3145573
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 27
journalURL: https://dl.acm.org/loi/toms
rawauthor: Javad Doliskani and Pascal Giorgi and Romain Lebreton and Eric Schost
rawtitle: Simultaneous Conversions with the Residue Number System Using Linear Algebra
abstract:
We present an algorithm for simultaneous conversions between a given set of integers and their Residue Number System representations based on linear algebra. We provide a highly optimized implementation of the algorithm that exploits the computational features of modern processors. The main application of our algorithm is matrix multiplication over integers. Our speed-up of the conversions to and from the Residue Number System significantly improves the overall running time of matrix multiplication.

rawabstract:
We present an algorithm for simultaneous conversions between a given set of integers and their Residue Number System representations based on linear algebra. We provide a highly optimized implementation of the algorithm that exploits the computational features of modern processors. The main application of our algorithm is matrix multiplication over integers. Our speed-up of the conversions to and from the Residue Number System significantly improves the overall running time of matrix multiplication.

entry:
@Article{Doliskani:2018:SCR,
  author =       "Javad Doliskani and Pascal Giorgi and Romain Lebreton
                 and Eric Schost",
  title =        "Simultaneous Conversions with the Residue Number
                 System Using Linear Algebra",
  journal =      j-TOMS,
  volume =       "44",
  number =       "3",
  pages =        "27:1--27:21",
  month =        apr,
  year =         "2018",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3145573",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon Jan 22 17:49:32 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3145573",
  abstract =     "We present an algorithm for simultaneous conversions
                 between a given set of integers and their Residue
                 Number System representations based on linear algebra.
                 We provide a highly optimized implementation of the
                 algorithm that exploits the computational features of
                 modern processors. The main application of our
                 algorithm is matrix multiplication over integers. Our
                 speed-up of the conversions to and from the Residue
                 Number System significantly improves the overall
                 running time of matrix multiplication.",
  acknowledgement = ack-nhfb,
  articleno =    "27",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Dosso:2018:EAC
author: Yssouf Dosso and Fabien Herbaut and Nicolas Meloni and Pascal Veron
title: Euclidean addition chains scalar multiplication on curves with efficient endomorphism
journal: j-J-CRYPTO-ENG
volume: 8
number: 4
pages: 351--367
month: nov
monthnumber: 11
year: 2018
DOI: https://doi.org/10.1007/s13389-018-0190-0
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-018-0190-0
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Yssouf Dosso and Fabien Herbaut and Nicolas M{\'e}loni and Pascal V{\'e}ron
rawtitle: {Euclidean} addition chains scalar multiplication on curves with efficient endomorphism
entry:
@Article{Dosso:2018:EAC,
  author =       "Yssouf Dosso and Fabien Herbaut and Nicolas M{\'e}loni
                 and Pascal V{\'e}ron",
  title =        "{Euclidean} addition chains scalar multiplication on
                 curves with efficient endomorphism",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "4",
  pages =        "351--367",
  month =        nov,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-018-0190-0",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-018-0190-0",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: inproceedings
filename: fparith.bib
label: Drucker:2018:CRS
author: Nir Drucker and Shay Gueron and Vlad Krasnov
title: The Comeback of Reed--Solomon Codes
crossref: Tenca:2018:PIS
pages: 125--129
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464690
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Nir Drucker and Shay Gueron and Vlad Krasnov
rawtitle: The Comeback of {Reed--Solomon} Codes
abstract:
Distributed storage systems utilize erasure codes to reduce their storage costs while efficiently handling failures. Many of these codes (e.g., Reed-Solomon (RS) codes) rely on Galois Field (GF) arithmetic, which is considered to be fast when the field characteristic is 2. Nevertheless, some developments in the field of erasure codes offer new efficient techniques that require mostly XOR operations, and are thus faster than GF operations. Recently, Intel announced [1] that its future architecture (codename Ice Lake) will introduce new set of instructions called Galois Field New Instruction (GF-NI). These instructions allow software flows to perform vector and matrix multiplications over GF ($ 2^8$) on the wide registers that are available on the AVX512 architectures. In this paper, we explain the functionality of these instructions, and demonstrate their usage for some fast computations in GF($ 2^8$). We also use the Intel Intelligent Storage Acceleration Library (ISA-L) in order to estimate potential future improvement for erasure codes that are based on RS codes. Our results predict $ 1.4 times $ speedup for vectorized multiplication, and $ 1.83 times $ speedup for the actual encoding.

keywords:
Acceleration; ARITH-25; AVX512 architectures; codename Ice Lake; Computer architecture; distributed storage systems; Encoding; erasure codes; field characteristic; Galois Field arithmetic; Galois fields; GF operations; GF-NI; Intel; Intelligent Storage Acceleration Library; matrix multiplication; matrix multiplications; Reed-Solomon codes; Registers; RS codes; storage costs; vector; vectors; Web services; XOR operations

rawabstract:
Distributed storage systems utilize erasure codes to reduce their storage costs while efficiently handling failures. Many of these codes (e.g., Reed-Solomon (RS) codes) rely on Galois Field (GF) arithmetic, which is considered to be fast when the field characteristic is 2. Nevertheless, some developments in the field of erasure codes offer new efficient techniques that require mostly XOR operations, and are thus faster than GF operations. Recently, Intel announced [1] that its future architecture (codename Ice Lake) will introduce new set of instructions called Galois Field New Instruction (GF-NI). These instructions allow software flows to perform vector and matrix multiplications over GF ($ 2^8$) on the wide registers that are available on the AVX512 architectures. In this paper, we explain the functionality of these instructions, and demonstrate their usage for some fast computations in GF($ 2^8$). We also use the Intel Intelligent Storage Acceleration Library (ISA-L) in order to estimate potential future improvement for erasure codes that are based on RS codes. Our results predict $ 1.4 \times $ speedup for vectorized multiplication, and $ 1.83 \times $ speedup for the actual encoding.

entry:
@InProceedings{Drucker:2018:CRS,
  author =       "Nir Drucker and Shay Gueron and Vlad Krasnov",
  title =        "The Comeback of {Reed--Solomon} Codes",
  crossref =     "Tenca:2018:PIS",
  pages =        "125--129",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464690",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Distributed storage systems utilize erasure codes to
                 reduce their storage costs while efficiently handling
                 failures. Many of these codes (e.g., Reed-Solomon (RS)
                 codes) rely on Galois Field (GF) arithmetic, which is
                 considered to be fast when the field characteristic is
                 2. Nevertheless, some developments in the field of
                 erasure codes offer new efficient techniques that
                 require mostly XOR operations, and are thus faster than
                 GF operations. Recently, Intel announced [1] that its
                 future architecture (codename Ice Lake) will introduce
                 new set of instructions called Galois Field New
                 Instruction (GF-NI). These instructions allow software
                 flows to perform vector and matrix multiplications over
                 GF ($ 2^8$) on the wide registers that are available on
                 the AVX512 architectures. In this paper, we explain the
                 functionality of these instructions, and demonstrate
                 their usage for some fast computations in GF($ 2^8$).
                 We also use the Intel Intelligent Storage Acceleration
                 Library (ISA-L) in order to estimate potential future
                 improvement for erasure codes that are based on RS
                 codes. Our results predict $ 1.4 \times $ speedup for
                 vectorized multiplication, and $ 1.83 \times $ speedup
                 for the actual encoding.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; ARITH-25; AVX512 architectures; codename
                 Ice Lake; Computer architecture; distributed storage
                 systems; Encoding; erasure codes; field characteristic;
                 Galois Field arithmetic; Galois fields; GF operations;
                 GF-NI; Intel; Intelligent Storage Acceleration Library;
                 matrix multiplication; matrix multiplications;
                 Reed-Solomon codes; Registers; RS codes; storage costs;
                 vector; vectors; Web services; XOR operations",
}


bibtype: inproceedings
filename: fparith.bib
label: Drucker:2018:FMB
author: Nir Drucker and Shay Gueron and Vlad Krasnov
title: Fast multiplication of binary polynomials with the forthcoming vectorized VPCLMULQDQ instruction
crossref: Tenca:2018:PIS
pages: 115--119
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464777
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Nir Drucker and Shay Gueron and Vlad Krasnov
rawtitle: Fast multiplication of binary polynomials with the forthcoming vectorized {VPCLMULQDQ} instruction
abstract:
Polynomial multiplication over binary fields $ mathbb F_2^n $ is a common primitive, used for example by current cryptosystems such as AES-GCM (with $ n = 128$). It also turns out to be a primitive for other cryptosystems, that are being designed for the Post Quantum era, with values n 128. Examples from the recent submissions to the NIST Post-Quantum Cryptography project, are BIKE, LEDAKem, and GeMSS, where the performance of the polynomial multiplications, is significant. Therefore, efficient polynomial multiplication over $ mathbb F_2^n$, with large $n$, is a significant emerging optimization target. Anticipating future applications, Intel has recently announced that its future architecture (codename Ice Lake) will introduce a new vectorized way to use the current VPCLMULQDQ instruction. In this paper, we demonstrate how to use this instruction for accelerating polynomial multiplication. Our analysis shows a prediction for at least $ 2 times $ speedup for multiplications with polynomials of degree 512 or more.

keywords:
Acceleration; AES-GCM; ARITH-25; BIKE; binary field-mathbbF2n; Computer architecture; Cryptography; cryptosystems; fast binary polynomial multiplication; fast multiplication; GeMSS; ice lake; LEDAKem; NIST; NIST Post-Quantum Cryptography project; optimisation; Optimization; optimization target; polynomials; post quantum cryptography; quantum cryptography; Registers; vectorized VPCLMULQDQ instruction; Web services

rawabstract:
Polynomial multiplication over binary fields $ \mathbb {F}_{2^n} $ is a common primitive, used for example by current cryptosystems such as AES-GCM (with $ n = 128$). It also turns out to be a primitive for other cryptosystems, that are being designed for the Post Quantum era, with values n 128. Examples from the recent submissions to the NIST Post-Quantum Cryptography project, are BIKE, LEDAKem, and GeMSS, where the performance of the polynomial multiplications, is significant. Therefore, efficient polynomial multiplication over $ \mathbb {F}_{2^n}$, with large $n$, is a significant emerging optimization target. Anticipating future applications, Intel has recently announced that its future architecture (codename Ice Lake) will introduce a new vectorized way to use the current VPCLMULQDQ instruction. In this paper, we demonstrate how to use this instruction for accelerating polynomial multiplication. Our analysis shows a prediction for at least $ 2 \times $ speedup for multiplications with polynomials of degree 512 or more.

entry:
@InProceedings{Drucker:2018:FMB,
  author =       "Nir Drucker and Shay Gueron and Vlad Krasnov",
  title =        "Fast multiplication of binary polynomials with the
                 forthcoming vectorized {VPCLMULQDQ} instruction",
  crossref =     "Tenca:2018:PIS",
  pages =        "115--119",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464777",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Polynomial multiplication over binary fields $ \mathbb
                 {F}_{2^n} $ is a common primitive, used for example by
                 current cryptosystems such as AES-GCM (with $ n =
                 128$). It also turns out to be a primitive for other
                 cryptosystems, that are being designed for the Post
                 Quantum era, with values n 128. Examples from the
                 recent submissions to the NIST Post-Quantum
                 Cryptography project, are BIKE, LEDAKem, and GeMSS,
                 where the performance of the polynomial
                 multiplications, is significant. Therefore, efficient
                 polynomial multiplication over $ \mathbb {F}_{2^n}$,
                 with large $n$, is a significant emerging optimization
                 target. Anticipating future applications, Intel has
                 recently announced that its future architecture
                 (codename Ice Lake) will introduce a new vectorized way
                 to use the current VPCLMULQDQ instruction. In this
                 paper, we demonstrate how to use this instruction for
                 accelerating polynomial multiplication. Our analysis
                 shows a prediction for at least $ 2 \times $ speedup
                 for multiplications with polynomials of degree 512 or
                 more.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; AES-GCM; ARITH-25; BIKE; binary
                 field-mathbbF2n; Computer architecture; Cryptography;
                 cryptosystems; fast binary polynomial multiplication;
                 fast multiplication; GeMSS; ice lake; LEDAKem; NIST;
                 NIST Post-Quantum Cryptography project; optimisation;
                 Optimization; optimization target; polynomials; post
                 quantum cryptography; quantum cryptography; Registers;
                 vectorized VPCLMULQDQ instruction; Web services",
}


bibtype: article
filename: fparith.bib
label: Dutt:2018:ADA
author: Sunil Dutt and Sukumar Nandi and Gaurav Trivedi
title: Analysis and Design of Adders for Approximate Computing
journal: j-TECS
volume: 17
number: 2
pages: 40:1--40:??
month: apr
monthnumber: 4
year: 2018
DOI: https://doi.org/10.1145/3131274
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Oct 17 18:16:34 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2019.10.17 18:16:34 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 40
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J840
rawauthor: Sunil Dutt and Sukumar Nandi and Gaurav Trivedi
rawtitle: Analysis and Design of Adders for Approximate Computing
abstract:
The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an N-bit approximate adder that hereinafter is referred as ``ApproxADD.'' An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay (O(1)). ApproxADD also provides improvement in dynamic power consumption by 46.31% and in area by 28.57% w.r.t. Ripple Carry Adder (RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i) Error Distance (ED) is too high; and (ii) Error Rate (ER) increases rapidly with bit-width ($N$). To improve ED and ER, we exploit the concept of carry-lifetime and Error Detection and Correction logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD $ upsilon $ 1 and ApproxADD. We call these as ApproxADD $ upsilon $ 1 and ApproxADD $ upsilon $ 2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) modules with ApproxADD $ upsilon $ 2.

rawabstract:
The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an N-bit approximate adder that hereinafter is referred as ``ApproxADD.'' An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay (O(1)). ApproxADD also provides improvement in dynamic power consumption by 46.31\% and in area by 28.57\% w.r.t. Ripple Carry Adder (RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i) Error Distance (ED) is too high; and (ii) Error Rate (ER) increases rapidly with bit-width ($N$). To improve ED and ER, we exploit the concept of carry-lifetime and Error Detection and Correction logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD $ \upsilon $ 1 and ApproxADD. We call these as ApproxADD $ \upsilon $ 1 and ApproxADD $ \upsilon $ 2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) modules with ApproxADD $ \upsilon $ 2.

entry:
@Article{Dutt:2018:ADA,
  author =       "Sunil Dutt and Sukumar Nandi and Gaurav Trivedi",
  title =        "Analysis and Design of Adders for Approximate
                 Computing",
  journal =      j-TECS,
  volume =       "17",
  number =       "2",
  pages =        "40:1--40:??",
  month =        apr,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3131274",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Oct 17 18:16:34 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  abstract =     "The concept of approximate computing, that is, to
                 sacrifice computation quality for computation efforts,
                 has recently emerged as a promising design approach.
                 Over the past decade, several research works have
                 explored approximate computing at both the software
                 level and hardware level of abstraction with
                 encouraging results. At the hardware level of
                 abstraction, adders (being the fundamental and most
                 widely used data operators in digital systems) have
                 attracted a significant attention for approximation. In
                 this article, we first explain briefly the
                 need/significance of approximate adders. We then
                 propose four Approximate Full Adders (AFAs) for
                 high-performance energy-efficient approximate
                 computing. The key design objective behind the proposed
                 AFAs is to curtail the length of carry propagation
                 subjected to minimal error rate. Next, we exploit one
                 of the proposed AFAs (optimal one) to construct an
                 N-bit approximate adder that hereinafter is referred as
                 ``ApproxADD.'' An emergent property of ApproxADD is
                 that carries do not propagate in it, and, consequently,
                 it provides bit-width-aware constant delay (O(1)).
                 ApproxADD also provides improvement in dynamic power
                 consumption by 46.31\% and in area by 28.57\% w.r.t.
                 Ripple Carry Adder (RCA), which exhibits the lowest
                 power and area. Although ApproxADD provides a
                 significant improvement in delay, power, and area, it
                 may not be preferred for some of the error-resilient
                 applications because its: (i) Error Distance (ED) is
                 too high; and (ii) Error Rate (ER) increases rapidly
                 with bit-width ($N$). To improve ED and ER, we exploit
                 the concept of carry-lifetime and Error Detection and
                 Correction logic, respectively. In this way, we
                 introduce two more (improved) versions of
                 ApproxADD--ApproxADD $ \upsilon $ 1 and ApproxADD. We
                 call these as ApproxADD $ \upsilon $ 1 and ApproxADD $
                 \upsilon $ 2 with existing approximate adders based on
                 conventional design metrics and approximate computing
                 design metrics. Furthermore, to inspect effectiveness
                 of the proposed approach in real-life applications, we
                 demonstrate image compression and decompression by
                 replacing the conventional addition operations in
                 Discrete Cosine Transform (DCT) and Inverse Discrete
                 Cosine Transform (IDCT) modules with ApproxADD $
                 \upsilon $ 2.",
  acknowledgement = ack-nhfb,
  articleno =    "40",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J840",
}


bibtype: inproceedings
filename: fparith.bib
label: Emmart:2018:FME
author: Niall Emmart and Fangyu Zhengt and Charles Weems
title: Faster Modular Exponentiation Using Double Precision Floating Point Arithmetic on the GPU
crossref: Tenca:2018:PIS
pages: 130--137
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464792
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Niall Emmart and Fangyu Zhengt and Charles Weems
rawtitle: Faster Modular Exponentiation Using Double Precision Floating Point Arithmetic on the {GPU}
abstract:
This paper presents a new approach to integer multiple precision (MP) modular exponentiation, using double-precision floating point (DPF) operations, that is suitable for GPU implementation. We show speedups ranging from 20% to 34% over the best prior GPU times for sizes corresponding to common RSA cryptographic operations (2048 to 4096 bits). Three techniques are described. First, by adding $ 2^104 $ to the high half of the product, and $ 2^52 $ to the low half, we set the implicit leading 1 in the DPF mantissa so that the full 52 explicit bits are available for each half of the 104-bit products of samples. Second, the DPF values are cast bitwise to 64-bit integers for adding the column sums to get the MP result. Normally the cast would require masking off the exponents, but because they are constant, we can include them in the column sums and correct just once for their total. Third, by initializing the column sums with the appropriate negative value to compensate for the exponent sums, no corrective subtraction is needed. Our implementation on an NVIDIA GTX Titan Black GPU achieves between 132.5K and 161.9K modular exponentiations per second of size 1024 bits, with latencies ranging from 21.7 ms to 17.8 ms, making it practical for online RSA applications. Proportional results are shown for 1536 and 2048 bits. The implementation is so efficient that its maximum sustained performance is actually bounded by the thermal limit of the GPU.

keywords:
appropriate negative value; ARITH-25; column sums; common RSA cryptographic operations; Computer architecture; cryptography; Cryptography; double precision floating point arithmetic; DPF mantissa; exponent sum compensation; faster modular exponentiation; floating point arithmetic; Floating-point arithmetic; Graphics processing units; graphics processing units; Hardware; integer multiple precision modular exponentiation; multiple precision modular exponentiation; NVIDIA GTX Titan Black GPU; online RSA applications; parallel architectures; time 17.8 ms to 21.7 ms; word length 1024.0 bit; word length 104 bit; word length 1536.0 bit; word length 2048 bit to 4096 bit; word length 64 bit

rawabstract:
This paper presents a new approach to integer multiple precision (MP) modular exponentiation, using double-precision floating point (DPF) operations, that is suitable for GPU implementation. We show speedups ranging from 20\% to 34\% over the best prior GPU times for sizes corresponding to common RSA cryptographic operations (2048 to 4096 bits). Three techniques are described. First, by adding $ 2^{104} $ to the high half of the product, and $ 2^{52} $ to the low half, we set the implicit leading 1 in the DPF mantissa so that the full 52 explicit bits are available for each half of the 104-bit products of samples. Second, the DPF values are cast bitwise to 64-bit integers for adding the column sums to get the MP result. Normally the cast would require masking off the exponents, but because they are constant, we can include them in the column sums and correct just once for their total. Third, by initializing the column sums with the appropriate negative value to compensate for the exponent sums, no corrective subtraction is needed. Our implementation on an NVIDIA GTX Titan Black GPU achieves between 132.5K and 161.9K modular exponentiations per second of size 1024 bits, with latencies ranging from 21.7 ms to 17.8 ms, making it practical for online RSA applications. Proportional results are shown for 1536 and 2048 bits. The implementation is so efficient that its maximum sustained performance is actually bounded by the thermal limit of the GPU.

entry:
@InProceedings{Emmart:2018:FME,
  author =       "Niall Emmart and Fangyu Zhengt and Charles Weems",
  title =        "Faster Modular Exponentiation Using Double Precision
                 Floating Point Arithmetic on the {GPU}",
  crossref =     "Tenca:2018:PIS",
  pages =        "130--137",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464792",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a new approach to integer multiple
                 precision (MP) modular exponentiation, using
                 double-precision floating point (DPF) operations, that
                 is suitable for GPU implementation. We show speedups
                 ranging from 20\% to 34\% over the best prior GPU times
                 for sizes corresponding to common RSA cryptographic
                 operations (2048 to 4096 bits). Three techniques are
                 described. First, by adding $ 2^{104} $ to the high
                 half of the product, and $ 2^{52} $ to the low half, we
                 set the implicit leading 1 in the DPF mantissa so that
                 the full 52 explicit bits are available for each half
                 of the 104-bit products of samples. Second, the DPF
                 values are cast bitwise to 64-bit integers for adding
                 the column sums to get the MP result. Normally the cast
                 would require masking off the exponents, but because
                 they are constant, we can include them in the column
                 sums and correct just once for their total. Third, by
                 initializing the column sums with the appropriate
                 negative value to compensate for the exponent sums, no
                 corrective subtraction is needed. Our implementation on
                 an NVIDIA GTX Titan Black GPU achieves between 132.5K
                 and 161.9K modular exponentiations per second of size
                 1024 bits, with latencies ranging from 21.7 ms to 17.8
                 ms, making it practical for online RSA applications.
                 Proportional results are shown for 1536 and 2048 bits.
                 The implementation is so efficient that its maximum
                 sustained performance is actually bounded by the
                 thermal limit of the GPU.",
  acknowledgement = ack-nhfb,
  keywords =     "appropriate negative value; ARITH-25; column sums;
                 common RSA cryptographic operations; Computer
                 architecture; cryptography; Cryptography; double
                 precision floating point arithmetic; DPF mantissa;
                 exponent sum compensation; faster modular
                 exponentiation; floating point arithmetic;
                 Floating-point arithmetic; Graphics processing units;
                 graphics processing units; Hardware; integer multiple
                 precision modular exponentiation; multiple precision
                 modular exponentiation; NVIDIA GTX Titan Black GPU;
                 online RSA applications; parallel architectures; time
                 17.8 ms to 21.7 ms; word length 1024.0 bit; word length
                 104 bit; word length 1536.0 bit; word length 2048 bit
                 to 4096 bit; word length 64 bit",
}


bibtype: inproceedings
filename: fparith.bib
label: Emmart:2018:NVB
author: Niall Emmart and Fangyu Zheng and Charles Weems
title: A New Variant of the Barrett Algorithm Applied to Quotient Selection
crossref: Tenca:2018:PIS
pages: 138--144
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464771
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Niall Emmart and Fangyu Zheng and Charles Weems
rawtitle: A New Variant of the {Barrett} Algorithm Applied to Quotient Selection
abstract:
Quotient Selection (QS) is a key step in the classic $ O(n^2) $ multiple precision division algorithm. On processors with fast hardware division, it is a trivial problem, but on GPUs, division is quite slow. In this paper we investigate the effectiveness of Brent and Zimmermann's variant as well as our own novel variant of Barrett's algorithm. Our new approach is shown to be suitable for low radix (single precision) QS. Three highly optimized implementations, two of the Brent and Zimmerman variant and one based on our new approach, have been developed and we show that each is many times faster than using the division operation built in to the compiler. In addition, our variant is on average 22% faster than the other two implementations. We also sketch proofs of correctness for all of the implementations and our new algorithm.

keywords:
Approximation algorithms; ARITH-25; Barrett algorithm; Barrett reduction; classic $O(n^2)$ multiple precision division algorithm; Computer security; digital arithmetic; Digital arithmetic; division operation; fast hardware division; GPU; graphics processing units; Hardware; low radix QS; multiple precision division; Newton method; O; processors; Program processors; quotient selection; Zimmermann variant

rawabstract:
Quotient Selection (QS) is a key step in the classic $ O(n^2) $ multiple precision division algorithm. On processors with fast hardware division, it is a trivial problem, but on GPUs, division is quite slow. In this paper we investigate the effectiveness of Brent and Zimmermann's variant as well as our own novel variant of Barrett's algorithm. Our new approach is shown to be suitable for low radix (single precision) QS. Three highly optimized implementations, two of the Brent and Zimmerman variant and one based on our new approach, have been developed and we show that each is many times faster than using the division operation built in to the compiler. In addition, our variant is on average 22\% faster than the other two implementations. We also sketch proofs of correctness for all of the implementations and our new algorithm.

entry:
@InProceedings{Emmart:2018:NVB,
  author =       "Niall Emmart and Fangyu Zheng and Charles Weems",
  title =        "A New Variant of the {Barrett} Algorithm Applied to
                 Quotient Selection",
  crossref =     "Tenca:2018:PIS",
  pages =        "138--144",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464771",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Quotient Selection (QS) is a key step in the classic $
                 O(n^2) $ multiple precision division algorithm. On
                 processors with fast hardware division, it is a trivial
                 problem, but on GPUs, division is quite slow. In this
                 paper we investigate the effectiveness of Brent and
                 Zimmermann's variant as well as our own novel variant
                 of Barrett's algorithm. Our new approach is shown to be
                 suitable for low radix (single precision) QS. Three
                 highly optimized implementations, two of the Brent and
                 Zimmerman variant and one based on our new approach,
                 have been developed and we show that each is many times
                 faster than using the division operation built in to
                 the compiler. In addition, our variant is on average
                 22\% faster than the other two implementations. We also
                 sketch proofs of correctness for all of the
                 implementations and our new algorithm.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; ARITH-25; Barrett algorithm;
                 Barrett reduction; classic $O(n^2)$ multiple precision
                 division algorithm; Computer security; digital
                 arithmetic; Digital arithmetic; division operation;
                 fast hardware division; GPU; graphics processing units;
                 Hardware; low radix QS; multiple precision division;
                 Newton method; O; processors; Program processors;
                 quotient selection; Zimmermann variant",
}


bibtype: article
filename: fparith.bib
label: Ferguson:2018:DSM
author: Warren E. Ferguson and Jesse Bingham and Levent Erkok and John R. Harrison and Joe Leslie-Hurd
title: Digit Serial Methods with Applications to Division and Square Root
journal: j-IEEE-TRANS-COMPUT
volume: 67
number: 3
pages: 449--456
month: mar
monthnumber: 3
year: 2018
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2759764
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Feb 15 05:53:34 MST 2018
bibtimestamp: 2018.02.15 05:53:34 MST
URL: http://ieeexplore.ieee.org/document/8060979/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Warren E. Ferguson and Jesse Bingham and Levent Erk{\"o}k and John R. Harrison and Joe Leslie-Hurd
rawtitle: Digit Serial Methods with Applications to Division and Square Root
entry:
@Article{Ferguson:2018:DSM,
  author =       "Warren E. Ferguson and Jesse Bingham and Levent
                 Erk{\"o}k and John R. Harrison and Joe Leslie-Hurd",
  title =        "Digit Serial Methods with Applications to Division and
                 Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "67",
  number =       "3",
  pages =        "449--456",
  month =        mar,
  year =         "2018",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2759764",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Feb 15 05:53:34 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/8060979/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Garland:2018:LCM
author: James Garland and David Gregg
title: Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing
journal: j-TACO
volume: 15
number: 3
pages: 31:1--31:??
month: oct
monthnumber: 10
year: 2018
DOI: https://doi.org/10.1145/3233300
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Tue Jan 8 17:19:59 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib
bibtimestamp: 2019.01.08 17:19:59 MST
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
articleno: 31
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J924
rawauthor: James Garland and David Gregg
rawtitle: Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing
abstract:
Convolutional neural networks (CNNs) are one of the most successful machine-learning techniques for image, voice, and video processing. CNNs require large amounts of processing capacity and memory bandwidth. Hardware accelerators have been proposed for CNNs that typically contain large numbers of multiply-accumulate (MAC) units, the multipliers of which are large in integrated circuit (IC) gate count and power consumption. ``Weight-sharing'' accelerators have been proposed where the full range of weight values in a trained CNN are compressed and put into bins, and the bin index is used to access the weight-shared value. We reduce power and area of the CNN by implementing parallel accumulate shared MAC (PASM) in a weight-shared CNN. PASM re-architects the MAC to instead count the frequency of each weight and place it in a bin. The accumulated value is computed in a subsequent multiply phase, significantly reducing gate count and power consumption of the CNN. In this article, we implement PASM in a weight-shared CNN convolution hardware accelerator and analyze its effectiveness. Experiments show that for a clock speed 1GHz implemented on a 45nm ASIC process our approach results in fewer gates, smaller logic, and reduced power with only a slight increase in latency. We also show that the same weight-shared-with-PASM CNN accelerator can be implemented in resource-constrained FPGAs, where the FPGA has limited numbers of digital signal processor (DSP) units to accelerate the MAC operations.

rawabstract:
Convolutional neural networks (CNNs) are one of the most successful machine-learning techniques for image, voice, and video processing. CNNs require large amounts of processing capacity and memory bandwidth. Hardware accelerators have been proposed for CNNs that typically contain large numbers of multiply-accumulate (MAC) units, the multipliers of which are large in integrated circuit (IC) gate count and power consumption. ``Weight-sharing'' accelerators have been proposed where the full range of weight values in a trained CNN are compressed and put into bins, and the bin index is used to access the weight-shared value. We reduce power and area of the CNN by implementing parallel accumulate shared MAC (PASM) in a weight-shared CNN. PASM re-architects the MAC to instead count the frequency of each weight and place it in a bin. The accumulated value is computed in a subsequent multiply phase, significantly reducing gate count and power consumption of the CNN. In this article, we implement PASM in a weight-shared CNN convolution hardware accelerator and analyze its effectiveness. Experiments show that for a clock speed 1GHz implemented on a 45nm ASIC process our approach results in fewer gates, smaller logic, and reduced power with only a slight increase in latency. We also show that the same weight-shared-with-PASM CNN accelerator can be implemented in resource-constrained FPGAs, where the FPGA has limited numbers of digital signal processor (DSP) units to accelerate the MAC operations.

entry:
@Article{Garland:2018:LCM,
  author =       "James Garland and David Gregg",
  title =        "Low Complexity Multiply-Accumulate Units for
                 Convolutional Neural Networks with Weight-Sharing",
  journal =      j-TACO,
  volume =       "15",
  number =       "3",
  pages =        "31:1--31:??",
  month =        oct,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3233300",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Tue Jan 8 17:19:59 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  abstract =     "Convolutional neural networks (CNNs) are one of the
                 most successful machine-learning techniques for image,
                 voice, and video processing. CNNs require large amounts
                 of processing capacity and memory bandwidth. Hardware
                 accelerators have been proposed for CNNs that typically
                 contain large numbers of multiply-accumulate (MAC)
                 units, the multipliers of which are large in integrated
                 circuit (IC) gate count and power consumption.
                 ``Weight-sharing'' accelerators have been proposed
                 where the full range of weight values in a trained CNN
                 are compressed and put into bins, and the bin index is
                 used to access the weight-shared value. We reduce power
                 and area of the CNN by implementing parallel accumulate
                 shared MAC (PASM) in a weight-shared CNN. PASM
                 re-architects the MAC to instead count the frequency of
                 each weight and place it in a bin. The accumulated
                 value is computed in a subsequent multiply phase,
                 significantly reducing gate count and power consumption
                 of the CNN. In this article, we implement PASM in a
                 weight-shared CNN convolution hardware accelerator and
                 analyze its effectiveness. Experiments show that for a
                 clock speed 1GHz implemented on a 45nm ASIC process our
                 approach results in fewer gates, smaller logic, and
                 reduced power with only a slight increase in latency.
                 We also show that the same weight-shared-with-PASM CNN
                 accelerator can be implemented in resource-constrained
                 FPGAs, where the FPGA has limited numbers of digital
                 signal processor (DSP) units to accelerate the MAC
                 operations.",
  acknowledgement = ack-nhfb,
  articleno =    "31",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J924",
}


bibtype: inproceedings
filename: fparith.bib
label: Glaser:2018:MMU
booktitle: 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
title: An 826 MOPS, 210uW / MHz Unum ALU in 65nm
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2018
DOI: https://doi.org/10.1109/ISCAS.2018.8351546
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2018 IEEE International Symposium on Circuits and Systems (ISCAS)}
rawtitle: An {826 MOPS}, {210uW\slash MHz} Unum {ALU} in 65nm
author:
Florian Glaser and Stefan Mach and Abbas Rahimi and Frank K. Gurkaynak and Qiuting Huang and Luca Benini

rawauthor:
Florian Glaser and Stefan Mach and Abbas Rahimi and Frank K. G{\"u}rkaynak and Qiuting Huang and Luca Benini

entry:
@InProceedings{Glaser:2018:MMU,
  author =       "Florian Glaser and Stefan Mach and Abbas Rahimi and
                 Frank K. G{\"u}rkaynak and Qiuting Huang and Luca
                 Benini",
  booktitle =    "{2018 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "An {826 MOPS}, {210uW\slash MHz} Unum {ALU} in 65nm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISCAS.2018.8351546",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Graillat:2018:NVC
author: Stef Graillat and Fabienne Jezequel and Romain Picot
title: Numerical validation of compensated algorithms with stochastic arithmetic
journal: j-APPL-MATH-COMP
volume: 329
pages: 339--363
day: 15
month: jul
monthnumber: 7
year: 2018
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2018.02.004
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Mar 17 16:59:00 MDT 2018
bibtimestamp: 2018.03.17 16:59:00 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0096300318300985
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain Picot
rawtitle: Numerical validation of compensated algorithms with stochastic arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
accurate floating-point dot product; accurate floating-point summation; CADNA; compensated algorithms; discrete stochastic arithmetic; error-free transformations; floating-point arithmetic; numerical validation; rounding errors

entry:
@Article{Graillat:2018:NVC,
  author =       "Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain
                 Picot",
  title =        "Numerical validation of compensated algorithms with
                 stochastic arithmetic",
  journal =      j-APPL-MATH-COMP,
  volume =       "329",
  number =       "??",
  pages =        "339--363",
  day =          "15",
  month =        jul,
  year =         "2018",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2018.02.004",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Mar 17 16:59:00 MDT 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0096300318300985",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
  keywords =     "accurate floating-point dot product; accurate
                 floating-point summation; CADNA; compensated
                 algorithms; discrete stochastic arithmetic; error-free
                 transformations; floating-point arithmetic; numerical
                 validation; rounding errors",
}


bibtype: incollection
filename: fparith.bib
label: Haidar:2018:DFE
booktitle: Computational science---ICCS 2018. Part I
volume: 10860
publisher: Springer
address: Cham, Switzerland
pages: 586--600
year: 2018
MRclass: 65Fxx (65Y10)
MRnumber: 3815810
bibdate: Tue Jan 8 09:18:00 2019
bibtimestamp: 2019.01.08 09:18:00 ???
series: ser-LNCS
acknowledgement: ack-nhfb
rawbooktitle: Computational science---{ICCS 2018}. {Part I}
ORCID: Dongarra, Jack/0000-0003-3247-1782
author:
Azzam Haidar and Ahmad Abdelfattah and Mawussi Zounon and Panruo Wu and Srikara Pranesh and Stanimire Tomov and Jack Dongarra

title:
The design of fast and energy-efficient linear solvers: on the potential of half-precision arithmetic and iterative refinement techniques

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawauthor:
Azzam Haidar and Ahmad Abdelfattah and Mawussi Zounon and Panruo Wu and Srikara Pranesh and Stanimire Tomov and Jack Dongarra

rawtitle:
The design of fast and energy-efficient linear solvers: on the potential of half-precision arithmetic and iterative refinement techniques

entry:
@InCollection{Haidar:2018:DFE,
  author =       "Azzam Haidar and Ahmad Abdelfattah and Mawussi Zounon
                 and Panruo Wu and Srikara Pranesh and Stanimire Tomov
                 and Jack Dongarra",
  booktitle =    "Computational science---{ICCS 2018}. {Part I}",
  title =        "The design of fast and energy-efficient linear
                 solvers: on the potential of half-precision arithmetic
                 and iterative refinement techniques",
  volume =       "10860",
  publisher =    "Springer",
  address =      "Cham, Switzerland",
  pages =        "586--600",
  year =         "2018",
  MRclass =      "65Fxx (65Y10)",
  MRnumber =     "3815810",
  bibdate =      "Tue Jan 8 09:18:00 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-LNCS,
  acknowledgement = ack-nhfb,
  ORCID-numbers = "Dongarra, Jack/0000-0003-3247-1782",
}


bibtype: inproceedings
filename: fparith.bib
label: Haidar:2018:HGT
author: Azzam Haidar and Stanimire Tomov and Jack Dongarra and Nicholas J. Higham
editor: IEEE
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 47:1--47:11
year: 2018
ISBN: 1-5386-8384-9 OR 1538683849
ISBN13: 978-1-5386-8384-2 OR 9781538683842
bibdate: Sat Jan 19 18:51:19 2019
bibtimestamp: 2019.01.19 18:51:19 ???
URL: https://dl.acm.org/citation.cfm?id=3291656.3291719
acknowledgement: ack-nhfb
rawauthor: Azzam Haidar and Stanimire Tomov and Jack Dongarra and Nicholas J. Higham
raweditor: {IEEE}
booktitle:
SC '18 Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, Dallas, Texas, November 11--16, 2018

title:
Harnessing GPU tensor cores for fast FP16 arithmetic to speed up mixed-precision iterative refinement solvers

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Low-precision floating-point arithmetic is a powerful tool for accelerating scientific computing applications, especially those in artificial intelligence. Here, we present an investigation showing that other high-performance computing (HPC) applications can also harness this power. Specifically, we use the general HPC problem, Ax = b, where A is a large dense matrix, and a double precision (FP64) solution is needed for accuracy. Our approach is based on mixed-precision (FP16 $ to $ FP64) iterative refinement, and we generalize and extend prior advances into a framework, for which we develop architecture-specific algorithms and highly tuned implementations. These new methods show how using half-precision Tensor Cores (FP16-TC) for the arithmetic can provide up to 4X speedup. This is due to the performance boost that the FP16-TC provide as well as to the improved accuracy over the classical FP16 arithmetic that is obtained because the GEMM accumulation occurs in FP32 arithmetic.

rawabstract:
Low-precision floating-point arithmetic is a powerful tool for accelerating scientific computing applications, especially those in artificial intelligence. Here, we present an investigation showing that other high-performance computing (HPC) applications can also harness this power. Specifically, we use the general HPC problem, Ax = b, where A is a large dense matrix, and a double precision (FP64) solution is needed for accuracy. Our approach is based on mixed-precision (FP16 $ \to $ FP64) iterative refinement, and we generalize and extend prior advances into a framework, for which we develop architecture-specific algorithms and highly tuned implementations. These new methods show how using half-precision Tensor Cores (FP16-TC) for the arithmetic can provide up to 4X speedup. This is due to the performance boost that the FP16-TC provide as well as to the improved accuracy over the classical FP16 arithmetic that is obtained because the GEMM accumulation occurs in FP32 arithmetic.

rawbooktitle:
{SC '18 Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, Dallas, Texas, November 11--16, 2018}

rawtitle:
Harnessing {GPU} tensor cores for fast {FP16} arithmetic to speed up mixed-precision iterative refinement solvers

entry:
@InProceedings{Haidar:2018:HGT,
  author =       "Azzam Haidar and Stanimire Tomov and Jack Dongarra and
                 Nicholas J. Higham",
  editor =       "{IEEE}",
  booktitle =    "{SC '18 Proceedings of the International Conference
                 for High Performance Computing, Networking, Storage,
                 and Analysis, Dallas, Texas, November 11--16, 2018}",
  title =        "Harnessing {GPU} tensor cores for fast {FP16}
                 arithmetic to speed up mixed-precision iterative
                 refinement solvers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "47:1--47:11",
  year =         "2018",
  ISBN =         "1-5386-8384-9",
  ISBN-13 =      "978-1-5386-8384-2",
  LCCN =         "????",
  bibdate =      "Sat Jan 19 18:51:19 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3291656.3291719",
  abstract =     "Low-precision floating-point arithmetic is a powerful
                 tool for accelerating scientific computing
                 applications, especially those in artificial
                 intelligence. Here, we present an investigation showing
                 that other high-performance computing (HPC)
                 applications can also harness this power. Specifically,
                 we use the general HPC problem, Ax = b, where A is a
                 large dense matrix, and a double precision (FP64)
                 solution is needed for accuracy. Our approach is based
                 on mixed-precision (FP16 $ \to $ FP64) iterative
                 refinement, and we generalize and extend prior advances
                 into a framework, for which we develop
                 architecture-specific algorithms and highly tuned
                 implementations. These new methods show how using
                 half-precision Tensor Cores (FP16-TC) for the
                 arithmetic can provide up to 4X speedup. This is due to
                 the performance boost that the FP16-TC provide as well
                 as to the improved accuracy over the classical FP16
                 arithmetic that is obtained because the GEMM
                 accumulation occurs in FP32 arithmetic.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hanson:2018:RAM
author: Richard J. Hanson and Tim Hopkins
journal: j-TOMS
volume: 44
number: 3
pages: 24:1--24:23
month: apr
monthnumber: 4
year: 2018
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3134441
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon Jan 22 17:49:32 MST 2018
bibtimestamp: 2018.01.22 17:49:32 MST
URL: https://dl.acm.org/citation.cfm?id=3134441
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 24
journalURL: https://dl.acm.org/loi/toms
rawauthor: Richard J. Hanson and Tim Hopkins
title:
Remark on Algorithm 539: A Modern Fortran Reference Implementation for Carefully Computing the Euclidean Norm

bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fortran3.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We propose a set of new Fortran reference implementations, based on an algorithm proposed by Kahan, for the Level 1 BLAS routines *NRM2 that compute the Euclidean norm of a real or complex input vector. The principal advantage of these routines over the current offerings is that, rather than losing accuracy as the length of the vector increases, they generate results that are accurate to almost machine precision for vectors of length $ N < N_rm max $ where $ N_rm max $ depends upon the precision of the floating point arithmetic being used. In addition, we make use of intrinsic modules, introduced in the latest Fortran standards, to detect occurrences of non-finite numbers in the input data and return suitable values as well as setting IEEE floating point status flags as appropriate. A set of C interface routines is also provided to allow simple, portable access to the new routines. To improve execution speed, we advocate a hybrid algorithm; a simple loop is used first and, only if IEEE floating point exception flags signal, do we fall back on Kahan's algorithm. Since most input vectors are ``easy,'' i.e., they do not require the sophistication of Kahan's algorithm, the simple loop improves performance while the use of compensated summation ensures high accuracy. We also report on a comprehensive suite of test problems that has been developed to test both our new implementation and existing codes for both accuracy and the appropriate settings of the IEEE arithmetic status flags.

rawabstract:
We propose a set of new Fortran reference implementations, based on an algorithm proposed by Kahan, for the Level 1 BLAS routines *NRM2 that compute the Euclidean norm of a real or complex input vector. The principal advantage of these routines over the current offerings is that, rather than losing accuracy as the length of the vector increases, they generate results that are accurate to almost machine precision for vectors of length $ N < N_{\rm max} $ where $ N_{\rm max} $ depends upon the precision of the floating point arithmetic being used. In addition, we make use of intrinsic modules, introduced in the latest Fortran standards, to detect occurrences of non-finite numbers in the input data and return suitable values as well as setting IEEE floating point status flags as appropriate. A set of C interface routines is also provided to allow simple, portable access to the new routines. To improve execution speed, we advocate a hybrid algorithm; a simple loop is used first and, only if IEEE floating point exception flags signal, do we fall back on Kahan's algorithm. Since most input vectors are ``easy,'' i.e., they do not require the sophistication of Kahan's algorithm, the simple loop improves performance while the use of compensated summation ensures high accuracy. We also report on a comprehensive suite of test problems that has been developed to test both our new implementation and existing codes for both accuracy and the appropriate settings of the IEEE arithmetic status flags.

rawtitle:
Remark on {Algorithm 539: A Modern Fortran Reference Implementation for Carefully Computing the Euclidean Norm}

entry:
@Article{Hanson:2018:RAM,
  author =       "Richard J. Hanson and Tim Hopkins",
  title =        "Remark on {Algorithm 539: A Modern Fortran Reference
                 Implementation for Carefully Computing the Euclidean
                 Norm}",
  journal =      j-TOMS,
  volume =       "44",
  number =       "3",
  pages =        "24:1--24:23",
  month =        apr,
  year =         "2018",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3134441",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon Jan 22 17:49:32 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fortran3.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3134441",
  abstract =     "We propose a set of new Fortran reference
                 implementations, based on an algorithm proposed by
                 Kahan, for the Level 1 BLAS routines *NRM2 that compute
                 the Euclidean norm of a real or complex input vector.
                 The principal advantage of these routines over the
                 current offerings is that, rather than losing accuracy
                 as the length of the vector increases, they generate
                 results that are accurate to almost machine precision
                 for vectors of length $ N < N_{\rm max} $ where $
                 N_{\rm max} $ depends upon the precision of the
                 floating point arithmetic being used. In addition, we
                 make use of intrinsic modules, introduced in the latest
                 Fortran standards, to detect occurrences of non-finite
                 numbers in the input data and return suitable values as
                 well as setting IEEE floating point status flags as
                 appropriate. A set of C interface routines is also
                 provided to allow simple, portable access to the new
                 routines. To improve execution speed, we advocate a
                 hybrid algorithm; a simple loop is used first and, only
                 if IEEE floating point exception flags signal, do we
                 fall back on Kahan's algorithm. Since most input
                 vectors are ``easy,'' i.e., they do not require the
                 sophistication of Kahan's algorithm, the simple loop
                 improves performance while the use of compensated
                 summation ensures high accuracy. We also report on a
                 comprehensive suite of test problems that has been
                 developed to test both our new implementation and
                 existing codes for both accuracy and the appropriate
                 settings of the IEEE arithmetic status flags.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  xxnote =       "See \cite{Lawson:1979:ABL}.",
}


bibtype: article
filename: fparith.bib
label: Hasanikhah:2018:EIS
author: Narjes Hasanikhah and Siavash Amin-Nejad and Ghafar Darvish and M. R. Moniri
journal: j-J-SUPERCOMPUTING
volume: 74
number: 7
pages: 3193--3210
month: jul
monthnumber: 7
year: 2018
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-018-2369-7
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Oct 10 15:31:13 MDT 2019
bibtimestamp: 2019.10.10 15:31:13 MDT
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: Narjes Hasanikhah and Siavash Amin-Nejad and Ghafar Darvish and M. R. Moniri
title:
Efficient implementation of space-time adaptive processing for adaptive weights calculation based on floating point FPGAs

bibsource:
http://link.springer.com/journal/11227/74/7; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper.bib

rawtitle:
Efficient implementation of space-time adaptive processing for adaptive weights calculation based on floating point {FPGAs}

entry:
@Article{Hasanikhah:2018:EIS,
  author =       "Narjes Hasanikhah and Siavash Amin-Nejad and Ghafar
                 Darvish and M. R. Moniri",
  title =        "Efficient implementation of space-time adaptive
                 processing for adaptive weights calculation based on
                 floating point {FPGAs}",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "74",
  number =       "7",
  pages =        "3193--3210",
  month =        jul,
  year =         "2018",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-018-2369-7",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Oct 10 15:31:13 MDT 2019",
  bibsource =    "http://link.springer.com/journal/11227/74/7;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: misc
filename: fparith.bib
label: Higham:2018:HPA
author: Nicholas J. Higham
title: Half Precision Arithmetic: fp16 Versus bfloat16
pages: 3193--3210
day: 3
month: dec
monthnumber: 12
year: 2018
bibdate: Sat Jan 19 18:43:15 2019
bibtimestamp: 2019.01.19 18:43:15 ???
URL: https://nickhigham.wordpress.com/2018/12/03/half-precision-arithmetic-fp16-versus-bfloat16/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Nicholas J. Higham
rawtitle: Half Precision Arithmetic: fp16 Versus bfloat16
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The 2008 revision of the IEEE Standard for Floating-Point Arithmetic introduced a half precision 16-bit floating point format, known as fp16, as a storage format. Various manufacturers have adopted fp16 for computation, using the obvious extension of the rules for the fp32 (single precision) and fp64 (double precision) formats. For example, fp16 is supported by the NVIDIA P100 and V100 GPUs and the AMD Radeon Instinct MI25 GPU, as well as the A64FX Arm processor that will power the Fujitsu Post-K exascale computer.

rawabstract:
The 2008 revision of the IEEE Standard for Floating-Point Arithmetic introduced a half precision 16-bit floating point format, known as fp16, as a storage format. Various manufacturers have adopted fp16 for computation, using the obvious extension of the rules for the fp32 (single precision) and fp64 (double precision) formats. For example, fp16 is supported by the NVIDIA P100 and V100 GPUs and the AMD Radeon Instinct MI25 GPU, as well as the A64FX Arm processor that will power the Fujitsu Post-K exascale computer.

entry:
@Misc{Higham:2018:HPA,
  author =       "Nicholas J. Higham",
  title =        "Half Precision Arithmetic: fp16 Versus bfloat16",
  howpublished = "Web site.",
  day =          "3",
  month =        dec,
  year =         "2018",
  bibdate =      "Sat Jan 19 18:43:15 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://nickhigham.wordpress.com/2018/12/03/half-precision-arithmetic-fp16-versus-bfloat16/",
  abstract =     "The 2008 revision of the IEEE Standard for
                 Floating-Point Arithmetic introduced a half precision
                 16-bit floating point format, known as fp16, as a
                 storage format. Various manufacturers have adopted fp16
                 for computation, using the obvious extension of the
                 rules for the fp32 (single precision) and fp64 (double
                 precision) formats. For example, fp16 is supported by
                 the NVIDIA P100 and V100 GPUs and the AMD Radeon
                 Instinct MI25 GPU, as well as the A64FX Arm processor
                 that will power the Fujitsu Post-K exascale computer.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Higham:2018:UN
author: Nicholas J. Higham
title: The Unwinding Number
journal: j-SIAM-NEWS
volume: 51
number: 8
pages: ??--??
month: oct
monthnumber: 10
year: 2018
ISSN: 0036-1437 OR 00361437
ISSNL: 0036-1437 OR 00361437
bibdate: Sat Oct 06 08:46:15 2018
bibtimestamp: 2018.10.06 08:46:15 ???
URL: https://sinews.siam.org/Details-Page/the-unwinding-number
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: https://sinews.siam.org/
rawauthor: Nicholas J. Higham
rawtitle: The Unwinding Number
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
While Fortran 66 had a complex data type, this was not true of most other early programming languages, such as Algol 60. As a result, programmers had to write their own procedures to implement complex arithmetic and transcendental functions in terms of separately stored real and imaginary parts. They quickly realized that this is not a trivial task; in the early 1960s, it took five published attempts over three years to obtain a correct implementation of the complex logarithm in Algol 60.

rawabstract:
While Fortran 66 had a complex data type, this was not true of most other early programming languages, such as Algol 60. As a result, programmers had to write their own procedures to implement complex arithmetic and transcendental functions in terms of separately stored real and imaginary parts. They quickly realized that this is not a trivial task; in the early 1960s, it took five published attempts over three years to obtain a correct implementation of the complex logarithm in Algol 60.

entry:
@Article{Higham:2018:UN,
  author =       "Nicholas J. Higham",
  title =        "The Unwinding Number",
  journal =      j-SIAM-NEWS,
  volume =       "51",
  number =       "8",
  pages =        "??--??",
  month =        oct,
  year =         "2018",
  ISSN =         "0036-1437",
  ISSN-L =       "0036-1437",
  bibdate =      "Sat Oct 06 08:46:15 2018",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/the-unwinding-number",
  abstract =     "While Fortran 66 had a complex data type, this was not
                 true of most other early programming languages, such as
                 Algol 60. As a result, programmers had to write their
                 own procedures to implement complex arithmetic and
                 transcendental functions in terms of separately stored
                 real and imaginary parts. They quickly realized that
                 this is not a trivial task; in the early 1960s, it took
                 five published attempts over three years to obtain a
                 correct implementation of the complex logarithm in
                 Algol 60.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "https://sinews.siam.org/",
}


bibtype: article
filename: fparith.bib
label: Hines:2018:MPS
author: Jonathan Hines
title: Mixed Precision: A Strategy for New Science Opportunities
journal: j-COMPUT-SCI-ENG
volume: 20
number: 6
pages: 67--71
month: nov
monthnumber: 11
year: 2018
CODEN: CSENFA
DOI: https://doi.org/10.1109/MCSE.2018.2874161
ISSN: 1521-9615 (print), 1558-366X (electronic) OR 15219615 (print), 1558366X (electronic)
ISSNL: 1521-9615 OR 15219615
bibdate: Wed Jan 30 17:58:50 MST 2019
bibtimestamp: 2019.01.30 17:58:50 MST
URL: https://www.computer.org/csdl/mags/cs/2018/06/08625902-abs.html
fjournal: Computing in Science and Engineering
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992
rawauthor: Jonathan Hines
rawtitle: Mixed Precision: A Strategy for New Science Opportunities
bibsource:
http://csdl.computer.org/comp/mags/cs/2018/06/c6toc.htm; https://www.math.utah.edu/pub/tex/bib/computscieng.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Hines:2018:MPS,
  author =       "Jonathan Hines",
  title =        "Mixed Precision: A Strategy for New Science
                 Opportunities",
  journal =      j-COMPUT-SCI-ENG,
  volume =       "20",
  number =       "6",
  pages =        "67--71",
  month =        nov # "\slash " # dec,
  year =         "2018",
  CODEN =        "CSENFA",
  DOI =          "https://doi.org/10.1109/MCSE.2018.2874161",
  ISSN =         "1521-9615 (print), 1558-366X (electronic)",
  ISSN-L =       "1521-9615",
  bibdate =      "Wed Jan 30 17:58:50 MST 2019",
  bibsource =    "http://csdl.computer.org/comp/mags/cs/2018/06/c6toc.htm;
                 https://www.math.utah.edu/pub/tex/bib/computscieng.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.computer.org/csdl/mags/cs/2018/06/08625902-abs.html",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing in Science and Engineering",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992",
}


bibtype: article
filename: fparith.bib
label: Hou:2018:EAD
author: Junjie Hou and Yongxin Zhu and Sen Du and Shijin Song
journal: Journal of Signal Processing Systems
volume: 91
number: 10
publisher: pub-SV
address: pub-SV:adr
pages: 1137--1148
month: nov
monthnumber: 11
year: 2018
DOI: https://doi.org/10.1007/s11265-018-1420-5
ISSN: 1939-8018 (print), 1939-8115 (electronic) OR 19398018 (print), 19398115 (electronic)
ISSNL: 1939-8115 OR 19398115
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Junjie Hou and Yongxin Zhu and Sen Du and Shijin Song
title:
Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on FPGA

rawtitle:
Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on {FPGA}

entry:
@Article{Hou:2018:EAD,
  author =       "Junjie Hou and Yongxin Zhu and Sen Du and Shijin
                 Song",
  title =        "Enhancing Accuracy and Dynamic Range of Scientific
                 Data Analytics by Implementing Posit Arithmetic on
                 {FPGA}",
  journal =      "Journal of Signal Processing Systems",
  volume =       "91",
  number =       "10",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "1137--1148",
  month =        nov,
  year =         "2018",
  DOI =          "https://doi.org/10.1007/s11265-018-1420-5",
  ISSN =         "1939-8018 (print), 1939-8115 (electronic)",
  ISSN-L =       "1939-8115",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Hrycak:2018:ECP
author: Tomasz Hrycak and Sebastian Schmutzhard
title: Evaluation of Chebyshev polynomials by a three-term recurrence in floating-point arithmetic
journal: j-BIT-NUM-MATH
volume: 58
number: 2
pages: 317--330
month: jun
monthnumber: 6
year: 2018
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-017-0683-8
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Wed Sep 26 07:36:57 MDT 2018
bibtimestamp: 2018.09.26 07:36:57 MDT
URL: https://link.springer.com/article/10.1007/s10543-017-0683-8
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: Tomasz Hrycak and Sebastian Schmutzhard
rawtitle: Evaluation of {Chebyshev} polynomials by a three-term recurrence in floating-point arithmetic
bibsource:
http://link.springer.com/journal/10543/58/2; https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Hrycak:2018:ECP,
  author =       "Tomasz Hrycak and Sebastian Schmutzhard",
  title =        "Evaluation of {Chebyshev} polynomials by a three-term
                 recurrence in floating-point arithmetic",
  journal =      j-BIT-NUM-MATH,
  volume =       "58",
  number =       "2",
  pages =        "317--330",
  month =        jun,
  year =         "2018",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-017-0683-8",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Wed Sep 26 07:36:57 MDT 2018",
  bibsource =    "http://link.springer.com/journal/10543/58/2;
                 https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://link.springer.com/article/10.1007/s10543-017-0683-8",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: article
filename: fparith.bib
label: Hutter:2018:FMP
author: Michael Hutter and Erich Wenger
title: Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
journal: j-J-CRYPTOLOGY
volume: 31
number: 4
pages: 1164--1182
month: oct
monthnumber: 10
year: 2018
CODEN: JOCREQ
DOI: https://doi.org/10.1007/s00145-018-9298-8
ISSN: 0933-2790 (print), 1432-1378 (electronic) OR 09332790 (print), 14321378 (electronic)
ISSNL: 0933-2790 OR 09332790
bibdate: Wed Sep 26 09:58:08 MDT 2018
bibtimestamp: 2018.09.26 09:58:08 MDT
URL: https://link.springer.com/article/10.1007/s00145-018-9298-8
fjournal: Journal of Cryptology
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/145
rawauthor: Michael Hutter and Erich Wenger
rawtitle: Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
bibsource:
http://link.springer.com/journal/145/31/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcryptology.bib

entry:
@Article{Hutter:2018:FMP,
  author =       "Michael Hutter and Erich Wenger",
  title =        "Fast Multi-precision Multiplication for Public-Key
                 Cryptography on Embedded Microprocessors",
  journal =      j-J-CRYPTOLOGY,
  volume =       "31",
  number =       "4",
  pages =        "1164--1182",
  month =        oct,
  year =         "2018",
  CODEN =        "JOCREQ",
  DOI =          "https://doi.org/10.1007/s00145-018-9298-8",
  ISSN =         "0933-2790 (print), 1432-1378 (electronic)",
  ISSN-L =       "0933-2790",
  bibdate =      "Wed Sep 26 09:58:08 MDT 2018",
  bibsource =    "http://link.springer.com/journal/145/31/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptology.bib",
  URL =          "https://link.springer.com/article/10.1007/s00145-018-9298-8",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptology",
  journal-URL =  "http://link.springer.com/journal/145",
}


bibtype: techreport
filename: fparith.bib
label: Intel:2018:BHN
author: Intel Corporation
title: BFLOAT16 --- Hardware Numerics Definition
type: White paper
number: 338302-001US
institution: pub-INTEL
address: pub-INTEL:adr
pages: 7
month: nov
monthnumber: 11
year: 2018
bibdate: Sat Jan 19 18:48:10 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.01.19 18:48:10 ???
URL: https://software.intel.com/en-us/download/bfloat16-hardware-numerics-definition
acknowledgement: ack-nhfb
rawauthor: {Intel Corporation}
rawtitle: {BFLOAT16} --- Hardware Numerics Definition
remark:
The BFLOAT16 (BF16) format has a 1-bit sign, 8-bit exponent, and 7-bit stored significand, corresponding to the top 16 bits of IEEE 754 Binary32. However, Intel's implementation does not provide subnormal numbers, or floating-point exceptions, and it only supports the IEEE 754 round-to-nearest ties-to-even rounding mode. Subnormal inputs are reduced to zero.

entry:
@TechReport{Intel:2018:BHN,
  author =       "{Intel Corporation}",
  title =        "{BFLOAT16} --- Hardware Numerics Definition",
  type =         "White paper",
  number =       "338302-001US",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "7",
  month =        nov,
  year =         "2018",
  bibdate =      "Sat Jan 19 18:48:10 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://software.intel.com/en-us/download/bfloat16-hardware-numerics-definition",
  acknowledgement = ack-nhfb,
  remark =       "The BFLOAT16 (BF16) format has a 1-bit sign, 8-bit
                 exponent, and 7-bit stored significand, corresponding
                 to the top 16 bits of IEEE 754 Binary32. However,
                 Intel's implementation does not provide subnormal
                 numbers, or floating-point exceptions, and it only
                 supports the IEEE 754 round-to-nearest ties-to-even
                 rounding mode. Subnormal inputs are reduced to zero.",
}


bibtype: inproceedings
filename: fparith.bib
label: Jaiswal:2018:AGT
author: Manish Kumar Jaiswal and Hayden K.-H So
editor: IEEE
booktitle: 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Architecture Generator for Type-3 Unum Posit Adder / Subtractor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2018
DOI: https://doi.org/10.1109/ISCAS.2018.8351142
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Manish Kumar Jaiswal and Hayden K.-H So
rawbooktitle: {2018 IEEE International Symposium on Circuits and Systems (ISCAS)}
raweditor: {IEEE}
rawtitle: Architecture Generator for {Type-3} Unum Posit Adder\slash Subtractor
entry:
@InProceedings{Jaiswal:2018:AGT,
  author =       "Manish Kumar Jaiswal and Hayden K.-H So",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Architecture Generator for {Type-3} Unum Posit
                 Adder\slash Subtractor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISCAS.2018.8351142",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jaiswal:2018:UNP
author: Manish Kumar Jaiswal and Hayden K.-H So
editor: IEEE
booktitle: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
title: Universal number posit arithmetic generator on FPGA
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1159--1162
year: 2018
DOI: https://doi.org/10.23919/DATE.2018.8342187
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Manish Kumar Jaiswal and Hayden K.-H So
rawbooktitle: {2018 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
raweditor: {IEEE}
rawtitle: Universal number posit arithmetic generator on {FPGA}
entry:
@InProceedings{Jaiswal:2018:UNP,
  author =       "Manish Kumar Jaiswal and Hayden K.-H So",
  editor =       "{IEEE}",
  booktitle =    "{2018 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Universal number posit arithmetic generator on
                 {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1159--1162",
  year =         "2018",
  DOI =          "https://doi.org/10.23919/DATE.2018.8342187",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jeangoudoux:2018:CRM
author: Clothilde Jeangoudoux and Christoph Lauter
title: A Correctly Rounded Mixed-Radix Fused-Multiply-Add
crossref: Tenca:2018:PIS
pages: 21--28
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464818
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Clothilde Jeangoudoux and Christoph Lauter
rawtitle: A Correctly Rounded Mixed-Radix Fused-Multiply-Add
abstract:
The IEEE 754-2008 Standard governs Floating-Point Arithmetic in all types of Computer Systems. The Standard provides for two radices, 2 and 10. It specifies conversion operations between these radices, but does not allow floating-point formats of different radices to be mixed in computational operations. In contrast, the Standard does provide for mixing formats of one radix in one operation. In order to enhance the Standard and make it closed under all basic computational operations, we propose an algorithm for a correctly rounded mixed-radix Fused-Multiply-and-Add (FMA). Our algorithm takes any combination of IEEE754 binary64 and decimal64 numbers in argument and provides a result in IEEE754 binary64 and decimal64, rounded according to any for the five IEEE754 rounding modes. Our implementation does not require any dynamic memory allocation; its runtime can be bounded statically. We compare our implementation to a basic mixed-radix FMA implementation based on the GMP Multiple Precision library.

keywords:
ARITH-25; basic computational operations; computer systems; conversion operations; correctly rounded mixed-radix Fused; decimal64 numbers; Electronic mail; floating point arithmetic; floating-point arithmetic; Floating-point arithmetic; floating-point formats; Heuristic algorithms; IEEE 754-2008 Standard; IEEE standards; IEEE754 rounding modes; Libraries; mixed-radix FMA implementation; Software; Standards; Systematics

rawabstract:
The IEEE 754-2008 Standard governs Floating-Point Arithmetic in all types of Computer Systems. The Standard provides for two radices, 2 and 10. It specifies conversion operations between these radices, but does not allow floating-point formats of different radices to be mixed in computational operations. In contrast, the Standard does provide for mixing formats of one radix in one operation. In order to enhance the Standard and make it closed under all basic computational operations, we propose an algorithm for a correctly rounded mixed-radix Fused-Multiply-and-Add (FMA). Our algorithm takes any combination of IEEE754 binary64 and decimal64 numbers in argument and provides a result in IEEE754 binary64 and decimal64, rounded according to any for the five IEEE754 rounding modes. Our implementation does not require any dynamic memory allocation; its runtime can be bounded statically. We compare our implementation to a basic mixed-radix FMA implementation based on the GMP Multiple Precision library.

entry:
@InProceedings{Jeangoudoux:2018:CRM,
  author =       "Clothilde Jeangoudoux and Christoph Lauter",
  title =        "A Correctly Rounded Mixed-Radix Fused-Multiply-Add",
  crossref =     "Tenca:2018:PIS",
  pages =        "21--28",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464818",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IEEE 754-2008 Standard governs Floating-Point
                 Arithmetic in all types of Computer Systems. The
                 Standard provides for two radices, 2 and 10. It
                 specifies conversion operations between these radices,
                 but does not allow floating-point formats of different
                 radices to be mixed in computational operations. In
                 contrast, the Standard does provide for mixing formats
                 of one radix in one operation. In order to enhance the
                 Standard and make it closed under all basic
                 computational operations, we propose an algorithm for a
                 correctly rounded mixed-radix Fused-Multiply-and-Add
                 (FMA). Our algorithm takes any combination of IEEE754
                 binary64 and decimal64 numbers in argument and provides
                 a result in IEEE754 binary64 and decimal64, rounded
                 according to any for the five IEEE754 rounding modes.
                 Our implementation does not require any dynamic memory
                 allocation; its runtime can be bounded statically. We
                 compare our implementation to a basic mixed-radix FMA
                 implementation based on the GMP Multiple Precision
                 library.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; basic computational operations; computer
                 systems; conversion operations; correctly rounded
                 mixed-radix Fused; decimal64 numbers; Electronic mail;
                 floating point arithmetic; floating-point arithmetic;
                 Floating-point arithmetic; floating-point formats;
                 Heuristic algorithms; IEEE 754-2008 Standard; IEEE
                 standards; IEEE754 rounding modes; Libraries;
                 mixed-radix FMA implementation; Software; Standards;
                 Systematics",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2018:REF
author: Claude-Pierre Jeannerod and Siegfried M. Rump
title: On relative errors of floating-point operations: Optimal bounds and applications
journal: j-MATH-COMPUT
volume: 87
number: 310
pages: 803--819
year: 2018
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Sat Jan 13 15:49:09 MST 2018
bibtimestamp: 2018.01.13 15:49:09 MST
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Claude-Pierre Jeannerod and Siegfried M. Rump
rawtitle: On relative errors of floating-point operations: {Optimal} bounds and applications
bibsource:
http://www.ams.org/mcom/2018-87-310; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8; http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8/S0025-5718-2017-03234-8.pdf; https://www.ams.org/mathscinet/search/authors.html?authorName=Rump%2C%20Siegfried%20M.; https://www.ams.org/mathscinet/search/authors.html?mrauthid=644190

entry:
@Article{Jeannerod:2018:REF,
  author =       "Claude-Pierre Jeannerod and Siegfried M. Rump",
  title =        "On relative errors of floating-point operations:
                 {Optimal} bounds and applications",
  journal =      j-MATH-COMPUT,
  volume =       "87",
  number =       "310",
  pages =        "803--819",
  month =        "",
  year =         "2018",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Sat Jan 13 15:49:09 MST 2018",
  bibsource =    "http://www.ams.org/mcom/2018-87-310;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8;
                 http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8/S0025-5718-2017-03234-8.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?authorName=Rump%2C%20Siegfried%20M.;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=644190",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: inproceedings
filename: fparith.bib
label: Jeannerod:2018:VWS
author: Claude-Pierre Jeannerod and Jean-Michel Muller and Paul Zimmermann
title: On Various Ways to Split a Floating-Point Number
crossref: Tenca:2018:PIS
pages: 53--60
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464793
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Claude-Pierre Jeannerod and Jean-Michel Muller and Paul Zimmermann
rawtitle: On Various Ways to Split a Floating-Point Number
abstract:
We review several ways to split a floating-point number, that is, to decompose it into the exact sum of two floating-point numbers of smaller precision. All the methods considered here involve only a few IEEE floating-point operations, with rounding to nearest and including possibly the fused multiply-add (FMA). Applications range from the implementation of integer functions such as round and floor to the computation of suitable scaling factors aimed, for example, at avoiding spurious underflows and overflows when implementing functions such as the hypotenuse.

keywords:
ARITH-25; Computer architecture; Containers; Digital arithmetic; floating point arithmetic; floating-point number; Floors; IEEE floating-point operations; integer functions; Lips; Matlab; Optimization

rawabstract:
We review several ways to split a floating-point number, that is, to decompose it into the exact sum of two floating-point numbers of smaller precision. All the methods considered here involve only a few IEEE floating-point operations, with rounding to nearest and including possibly the fused multiply-add (FMA). Applications range from the implementation of integer functions such as round and floor to the computation of suitable scaling factors aimed, for example, at avoiding spurious underflows and overflows when implementing functions such as the hypotenuse.

entry:
@InProceedings{Jeannerod:2018:VWS,
  author =       "Claude-Pierre Jeannerod and Jean-Michel Muller and
                 Paul Zimmermann",
  title =        "On Various Ways to Split a Floating-Point Number",
  crossref =     "Tenca:2018:PIS",
  pages =        "53--60",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464793",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We review several ways to split a floating-point
                 number, that is, to decompose it into the exact sum of
                 two floating-point numbers of smaller precision. All
                 the methods considered here involve only a few IEEE
                 floating-point operations, with rounding to nearest and
                 including possibly the fused multiply-add (FMA).
                 Applications range from the implementation of integer
                 functions such as round and floor to the computation of
                 suitable scaling factors aimed, for example, at
                 avoiding spurious underflows and overflows when
                 implementing functions such as the hypotenuse.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; Computer architecture; Containers; Digital
                 arithmetic; floating point arithmetic; floating-point
                 number; Floors; IEEE floating-point operations; integer
                 functions; Lips; Matlab; Optimization",
}


bibtype: article
filename: fparith.bib
label: Jeon:2018:HMP
author: Dong-Ik Jeon and Kyeong-Bin Park and Ki-Seok Chung
journal: j-IEEE-COMPUT-ARCHIT-LETT
volume: 17
number: 1
pages: 5--8
month: jan
monthnumber: 1
year: 2018
DOI: https://doi.org/10.1109/LCA.2017.2700298
ISSN: 1556-6056 (print), 1556-6064 (electronic) OR 15566056 (print), 15566064 (electronic)
ISSNL: 1556-6056 OR 15566056
bibdate: Tue Jun 25 07:41:05 2019
bibtimestamp: 2019.06.25 07:41:05 ???
fjournal: IEEE Computer Architecture Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208
rawauthor: Dong-Ik Jeon and Kyeong-Bin Park and Ki-Seok Chung
ORCID: Jeon, Dong-Ik/0000-0002-8572-4184
title:
HMC-MAC: Processing-in Memory Architecture for Multiply--Accumulate Operations with Hybrid Memory Cube

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib

abstract:
Many studies focus on implementing processing-in memory (PIM) on the logic die of the hybrid memory cube (HMC) architecture. The multiply-accumulate (MAC) operation is heavily used in digital signal processing (DSP) systems. In this paper, a novel PIM architecture called HMC-MAC that implements the MAC operation in the HMC is proposed. The vault controllers of the conventional HMC are working independently to maximize the parallelism, and HMC-MAC is based on the conventional HMC without modifying the architecture much. Therefore, a large number of MAC operations can be processed in parallel. In HMC-MAC, the MAC operation can be carried out simultaneously with as much as 128 KB data. The correctness on HMC-MAC is verified by simulations, and its performance is better than the conventional CPU-based MAC operation when the MAC operation is consecutively executed at least six times

keywords:
Computers; CPU-based MAC operation; digital signal processing; digital signal processing systems; DRAM chips; DSP systems; Electronic mail; HMC-MAC; hybrid memory cube architecture; logic circuits; logic die; memory architecture; Memory architecture; Memory management; memory size 128.0 KByte; Memory structures; memory used as logic; multiple data stream architectures; multiply-accumulate operation; parallel processing; processing-in memory architecture; Random access memory; Registers; vault controllers

affiliation:
Chung, KS (Reprint Author), Hanyang Univ, Dept Elect & Comp Engn, Seoul 04763, South Korea. Jeon, Dong-Ik; Park, Kyeong-Bin; Chung, Ki-Seok, Hanyang Univ, Dept Elect & Comp Engn, Seoul 04763, South Korea.

rawabstract:
Many studies focus on implementing processing-in memory (PIM) on the logic die of the hybrid memory cube (HMC) architecture. The multiply-accumulate (MAC) operation is heavily used in digital signal processing (DSP) systems. In this paper, a novel PIM architecture called HMC-MAC that implements the MAC operation in the HMC is proposed. The vault controllers of the conventional HMC are working independently to maximize the parallelism, and HMC-MAC is based on the conventional HMC without modifying the architecture much. Therefore, a large number of MAC operations can be processed in parallel. In HMC-MAC, the MAC operation can be carried out simultaneously with as much as 128 KB data. The correctness on HMC-MAC is verified by simulations, and its performance is better than the conventional CPU-based MAC operation when the MAC operation is consecutively executed at least six times

rawtitle:
{HMC-MAC}: Processing-in Memory Architecture for Multiply--Accumulate Operations with Hybrid Memory Cube

entry:
@Article{Jeon:2018:HMP,
  author =       "Dong-Ik Jeon and Kyeong-Bin Park and Ki-Seok Chung",
  title =        "{HMC-MAC}: Processing-in Memory Architecture for
                 Multiply--Accumulate Operations with Hybrid Memory
                 Cube",
  journal =      j-IEEE-COMPUT-ARCHIT-LETT,
  volume =       "17",
  number =       "1",
  pages =        "5--8",
  month =        jan # "\slash " # jun,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/LCA.2017.2700298",
  ISSN =         "1556-6056 (print), 1556-6064 (electronic)",
  ISSN-L =       "1556-6056",
  bibdate =      "Tue Jun 25 07:41:05 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib",
  abstract =     "Many studies focus on implementing processing-in
                 memory (PIM) on the logic die of the hybrid memory cube
                 (HMC) architecture. The multiply-accumulate (MAC)
                 operation is heavily used in digital signal processing
                 (DSP) systems. In this paper, a novel PIM architecture
                 called HMC-MAC that implements the MAC operation in the
                 HMC is proposed. The vault controllers of the
                 conventional HMC are working independently to maximize
                 the parallelism, and HMC-MAC is based on the
                 conventional HMC without modifying the architecture
                 much. Therefore, a large number of MAC operations can
                 be processed in parallel. In HMC-MAC, the MAC operation
                 can be carried out simultaneously with as much as 128
                 KB data. The correctness on HMC-MAC is verified by
                 simulations, and its performance is better than the
                 conventional CPU-based MAC operation when the MAC
                 operation is consecutively executed at least six
                 times",
  acknowledgement = ack-nhfb,
  affiliation =  "Chung, KS (Reprint Author), Hanyang Univ, Dept Elect
                 \& Comp Engn, Seoul 04763, South Korea. Jeon, Dong-Ik;
                 Park, Kyeong-Bin; Chung, Ki-Seok, Hanyang Univ, Dept
                 Elect \& Comp Engn, Seoul 04763, South Korea.",
  author-email = "estwingz@naver.com lay1523@naver.com
                 kchung@hanyang.ac.kr",
  da =           "2019-06-20",
  doc-delivery-number = "FZ6EO",
  eissn =        "1556-6064",
  fjournal =     "IEEE Computer Architecture Letters",
  funding-acknowledgement = "Basic Science Research Program through the
                 National Research Foundation of Korea(NRF) --- Ministry
                 of Education [NRF-2015R1D1A1A09061079]",
  funding-text = "This research was supported by Basic Science Research
                 Program through the National Research Foundation of
                 Korea(NRF) funded by the Ministry of Education
                 (NRF-2015R1D1A1A09061079).",
  journal-iso =  "IEEE Comput. Archit. Lett.",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
  keywords =     "Computers; CPU-based MAC operation; digital signal
                 processing; digital signal processing systems; DRAM
                 chips; DSP systems; Electronic mail; HMC-MAC; hybrid
                 memory cube architecture; logic circuits; logic die;
                 memory architecture; Memory architecture; Memory
                 management; memory size 128.0 KByte; Memory structures;
                 memory used as logic; multiple data stream
                 architectures; multiply-accumulate operation; parallel
                 processing; processing-in memory architecture; Random
                 access memory; Registers; vault controllers",
  number-of-cited-references = "11",
  ORCID-numbers = "Jeon, Dong-Ik/0000-0002-8572-4184",
  research-areas = "Computer Science",
  times-cited =  "0",
  unique-id =    "Jeon:2018:HMP",
  web-of-science-categories = "Computer Science, Hardware \&
                 Architecture",
}


bibtype: article
filename: fparith.bib
label: Jiang:2018:EFD
author: Xiaoyu Jiang and Kicheon Hong
title: Explicit form of determinants and inverse matrices of Tribonacci $r$-circulant type matrices
journal: j-J-MATH-CHEM
volume: 56
number: 4
pages: 1234--1249
month: apr
monthnumber: 4
year: 2018
CODEN: JMCHEG
DOI: https://doi.org/10.1007/s10910-017-0843-8
ISSN: 0259-9791 (print), 1572-8897 (electronic) OR 02599791 (print), 15728897 (electronic)
ISSNL: 0259-9791 OR 02599791
bibdate: Tue Mar 6 07:08:26 MST 2018
bibtimestamp: 2018.03.06 07:08:26 MST
URL: https://link.springer.com/article/10.1007/s10910-017-0843-8
fjournal: Journal of Mathematical Chemistry
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10910
journalabr: J. Math. Chem.
rawauthor: Xiaoyu Jiang and Kicheon Hong
rawtitle: Explicit form of determinants and inverse matrices of {Tribonacci} $r$-circulant type matrices
bibsource:
http://link.springer.com/journal/10910/56/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jmathchem.bib

entry:
@Article{Jiang:2018:EFD,
  author =       "Xiaoyu Jiang and Kicheon Hong",
  title =        "Explicit form of determinants and inverse matrices of
                 {Tribonacci} $r$-circulant type matrices",
  journal =      j-J-MATH-CHEM,
  volume =       "56",
  number =       "4",
  pages =        "1234--1249",
  month =        apr,
  year =         "2018",
  CODEN =        "JMCHEG",
  DOI =          "https://doi.org/10.1007/s10910-017-0843-8",
  ISSN =         "0259-9791 (print), 1572-8897 (electronic)",
  ISSN-L =       "0259-9791",
  bibdate =      "Tue Mar 6 07:08:26 MST 2018",
  bibsource =    "http://link.springer.com/journal/10910/56/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jmathchem.bib",
  URL =          "https://link.springer.com/article/10.1007/s10910-017-0843-8",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Mathematical Chemistry",
  journal-URL =  "http://link.springer.com/journal/10910",
  journalabr =   "J. Math. Chem.",
}


bibtype: article
filename: fparith.bib
label: Johnson:2018:RFP
author: Jeff Johnson
title: Rethinking floating point for deep learning
journal: arXiv.org
pages: 8
day: 1
month: nov
monthnumber: 11
year: 2018
bibdate: Mon Feb 10 09:27:01 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 09:27:01 ???
URL: https://arxiv.org/abs/1811.01721
acknowledgement: ack-nhfb
rawauthor: Jeff Johnson
rawtitle: Rethinking floating point for deep learning
abstract:
Reducing hardware overhead of neural networks for faster or lower power inference and training is an active area of research. Uniform quantization using integer multiply-add has been thoroughly investigated, which requires learning many quantization parameters, fine-tuning training or other prerequisites. Little effort is made to improve floating point relative to this baseline; it remains energy inefficient, and word size reduction yields drastic loss in needed dynamic range. We improve floating point to be more energy efficient than equivalent bit width integer hardware on a 28 nm ASIC process while retaining accuracy in 8 bits with a novel hybrid log multiply / linear add, Kulisch accumulation and tapered encodings from Gustafson's posit format. With no network retraining, and drop-in replacement of all math and float32 parameters via round-to-nearest-even only, this open-sourced 8-bit log float is within 0.9% top-1 and 0.2% top-5 accuracy of the original float32 ResNet-50 CNN model on ImageNet. Unlike int8 quantization, it is still a general purpose floating point arithmetic, interpretable out-of-the-box. Our 8/38-bit log float multiply-add is synthesized and power profiled at 28 nm at $ 0.96 times $ the power and $ 1.12 times $ the area of 8/32-bit integer multiply-add. In 16 bits, our log float multiply-add is $ 0.59 times $ the power and $ 0.68 times $ the area of IEEE 754 float16 fused multiply-add, maintaining the same significand precision and dynamic range, proving useful for training ASICs as well.

rawabstract:
Reducing hardware overhead of neural networks for faster or lower power inference and training is an active area of research. Uniform quantization using integer multiply-add has been thoroughly investigated, which requires learning many quantization parameters, fine-tuning training or other prerequisites. Little effort is made to improve floating point relative to this baseline; it remains energy inefficient, and word size reduction yields drastic loss in needed dynamic range. We improve floating point to be more energy efficient than equivalent bit width integer hardware on a 28 nm ASIC process while retaining accuracy in 8 bits with a novel hybrid log multiply\slash linear add, Kulisch accumulation and tapered encodings from Gustafson's posit format. With no network retraining, and drop-in replacement of all math and float32 parameters via round-to-nearest-even only, this open-sourced 8-bit log float is within 0.9\% top-1 and 0.2\% top-5 accuracy of the original float32 ResNet-50 CNN model on ImageNet. Unlike int8 quantization, it is still a general purpose floating point arithmetic, interpretable out-of-the-box. Our 8/38-bit log float multiply-add is synthesized and power profiled at 28 nm at $ 0.96 \times $ the power and $ 1.12 \times $ the area of 8/32-bit integer multiply-add. In 16 bits, our log float multiply-add is $ 0.59 \times $ the power and $ 0.68 \times $ the area of IEEE 754 float16 fused multiply-add, maintaining the same significand precision and dynamic range, proving useful for training ASICs as well.

entry:
@Article{Johnson:2018:RFP,
  author =       "Jeff Johnson",
  title =        "Rethinking floating point for deep learning",
  journal =      "arXiv.org",
  pages =        "8",
  day =          "1",
  month =        nov,
  year =         "2018",
  bibdate =      "Mon Feb 10 09:27:01 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1811.01721",
  abstract =     "Reducing hardware overhead of neural networks for
                 faster or lower power inference and training is an
                 active area of research. Uniform quantization using
                 integer multiply-add has been thoroughly investigated,
                 which requires learning many quantization parameters,
                 fine-tuning training or other prerequisites. Little
                 effort is made to improve floating point relative to
                 this baseline; it remains energy inefficient, and word
                 size reduction yields drastic loss in needed dynamic
                 range. We improve floating point to be more energy
                 efficient than equivalent bit width integer hardware on
                 a 28 nm ASIC process while retaining accuracy in 8 bits
                 with a novel hybrid log multiply\slash linear add,
                 Kulisch accumulation and tapered encodings from
                 Gustafson's posit format. With no network retraining,
                 and drop-in replacement of all math and float32
                 parameters via round-to-nearest-even only, this
                 open-sourced 8-bit log float is within 0.9\% top-1 and
                 0.2\% top-5 accuracy of the original float32 ResNet-50
                 CNN model on ImageNet. Unlike int8 quantization, it is
                 still a general purpose floating point arithmetic,
                 interpretable out-of-the-box. Our 8/38-bit log float
                 multiply-add is synthesized and power profiled at 28 nm
                 at $ 0.96 \times $ the power and $ 1.12 \times $ the
                 area of 8/32-bit integer multiply-add. In 16 bits, our
                 log float multiply-add is $ 0.59 \times $ the power and
                 $ 0.68 \times $ the area of IEEE 754 float16 fused
                 multiply-add, maintaining the same significand
                 precision and dynamic range, proving useful for
                 training ASICs as well.",
  acknowledgement = ack-nhfb,
  primaryclass = "cs.NA",
}


bibtype: inproceedings
filename: fparith.bib
label: Kohlbecker:2018:SNF
author: Ignaz Kohlbecker
title: The Slide Number Format
crossref: ACM:2018:CNG
pages: 1--6
year: 2018
DOI: https://doi.org/10.1145/3190339.3190342
bibdate: Mon Dec 11 09:01:38 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 09:01:38 ???
keywords: posit arithmetic; slide number format; universal number (unum) arithmetic
acknowledgement: ack-nhfb
articleno: 3
rawauthor: Ignaz Kohlbecker
rawtitle: The Slide Number Format
abstract:
The Slide number format divides the real number line into connected sets. Compared to the unum format [3], there is no ubit, no infinity, and values are placed on a logarithmic scale with base 10. Formal definitions for Slides and intervals composed of Slide pairs are provided. The relative error is compared with that of single precision floats. The performance of conversions to and from human readable form is measured.

rawabstract:
The Slide number format divides the real number line into connected sets. Compared to the unum format [3], there is no ubit, no infinity, and values are placed on a logarithmic scale with base 10. Formal definitions for Slides and intervals composed of Slide pairs are provided. The relative error is compared with that of single precision floats. The performance of conversions to and from human readable form is measured.

entry:
@InProceedings{Kohlbecker:2018:SNF,
  author =       "Ignaz Kohlbecker",
  title =        "The Slide Number Format",
  crossref =     "ACM:2018:CNG",
  pages =        "1--6",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190342",
  bibdate =      "Mon Dec 11 09:01:38 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Slide number format divides the real number line
                 into connected sets. Compared to the unum format [3],
                 there is no ubit, no infinity, and values are placed on
                 a logarithmic scale with base 10. Formal definitions
                 for Slides and intervals composed of Slide pairs are
                 provided. The relative error is compared with that of
                 single precision floats. The performance of conversions
                 to and from human readable form is measured.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  keywords =     "posit arithmetic; slide number format; universal
                 number (unum) arithmetic",
}


bibtype: article
filename: fparith.bib
label: Kromer:2018:AQO
author: Pavel Kromer and Jan Platos and Jana Nowakova and Vaclav Snasel
title: An acceleration of quasigroup operations by residue arithmetic
journal: j-CCPE
volume: 30
number: 2
pages: ??--??
day: 25
month: jan
monthnumber: 1
year: 2018
CODEN: CCPEBO
DOI: https://doi.org/10.1002/cpe.4239
ISSN: 1532-0626 (print), 1532-0634 (electronic) OR 15320626 (print), 15320634 (electronic)
ISSNL: 1532-0626 OR 15320626
bibdate: Sat Dec 30 09:12:00 MST 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/ccpe.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.12.30 09:12:00 MST
fjournal: Concurrency and Computation: Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://www.interscience.wiley.com/jpages/1532-0626
rawauthor: Pavel Kr{\"o}mer and Jan Plato{\v{s}} and Jana Nowakov{\'a} and V{\'a}clav Sn{\'a}{\v{s}}el
rawtitle: An acceleration of quasigroup operations by residue arithmetic
entry:
@Article{Kromer:2018:AQO,
  author =       "Pavel Kr{\"o}mer and Jan Plato{\v{s}} and Jana
                 Nowakov{\'a} and V{\'a}clav Sn{\'a}{\v{s}}el",
  title =        "An acceleration of quasigroup operations by residue
                 arithmetic",
  journal =      j-CCPE,
  volume =       "30",
  number =       "2",
  pages =        "??--??",
  day =          "25",
  month =        jan,
  year =         "2018",
  CODEN =        "CCPEBO",
  DOI =          "https://doi.org/10.1002/cpe.4239",
  ISSN =         "1532-0626 (print), 1532-0634 (electronic)",
  ISSN-L =       "1532-0626",
  bibdate =      "Sat Dec 30 09:12:00 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ccpe.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Concurrency and Computation: Practice and Experience",
  journal-URL =  "http://www.interscience.wiley.com/jpages/1532-0626",
}


bibtype: inproceedings
filename: fparith.bib
label: Kumm:2018:KRM
author: Martin Kumm and Oscar Gustafsson and Florent de Dinechin and Johannes Kappauf and Peter Zipf
title: Karatsuba with Rectangular Multipliers for FPGAs
crossref: Tenca:2018:PIS
pages: 13--20
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464809
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Martin Kumm and Oscar Gustafsson and Florent de Dinechin and Johannes Kappauf and Peter Zipf
rawtitle: {Karatsuba} with Rectangular Multipliers for {FPGAs}
abstract:
This work presents an extension of Karatsuba's method to efficiently use rectangular multipliers as a base for larger multipliers. The rectangular multipliers that motivate this work are the embedded $ 18 times 25$-bit signed multipliers found in the DSP blocks of recent Xilinx FPGAs: The traditional Karatsuba approach must under-use them as square $ 18 times 18 $ ones. This work shows that rectangular multipliers can be efficiently exploited in a modified Karatsuba method if their input word sizes have a large greatest common divider. In the Xilinx FPG A case, this can be obtained by using the embedded multipliers as $ 16 times 24 $ unsigned and as $ 17 times 25$ signed ones. The obtained architectures are implemented with due detail to architectural features such as the pre-adders and post-adders available in Xilinx DSP blocks. They are synthesized and compared with traditional Karatsuba, but also with (non-Karatsuba) state-of-the-art tiling techniques that make use of the full rectangular multipliers. The proposed technique improves resource consumption and performance for multipliers of numbers larger than 64 bits.

keywords:
25-bit signed multipliers; adders; ARITH-25; Computer architecture; Delays; Digital arithmetic; digital arithmetic; Electrical engineering; embedded multipliers; field programmable gate arrays; Field programmable gate arrays; Hardware; larger multipliers; modified Karatsuba method; multiplying circuits; rectangular multipliers; word length 64.0 bit

rawabstract:
This work presents an extension of Karatsuba's method to efficiently use rectangular multipliers as a base for larger multipliers. The rectangular multipliers that motivate this work are the embedded $ 18 \times 25$-bit signed multipliers found in the DSP blocks of recent Xilinx FPGAs: The traditional Karatsuba approach must under-use them as square $ 18 \times 18 $ ones. This work shows that rectangular multipliers can be efficiently exploited in a modified Karatsuba method if their input word sizes have a large greatest common divider. In the Xilinx FPG A case, this can be obtained by using the embedded multipliers as $ 16 \times 24 $ unsigned and as $ 17 \times 25$ signed ones. The obtained architectures are implemented with due detail to architectural features such as the pre-adders and post-adders available in Xilinx DSP blocks. They are synthesized and compared with traditional Karatsuba, but also with (non-Karatsuba) state-of-the-art tiling techniques that make use of the full rectangular multipliers. The proposed technique improves resource consumption and performance for multipliers of numbers larger than 64 bits.

entry:
@InProceedings{Kumm:2018:KRM,
  author =       "Martin Kumm and Oscar Gustafsson and Florent de
                 Dinechin and Johannes Kappauf and Peter Zipf",
  title =        "{Karatsuba} with Rectangular Multipliers for {FPGAs}",
  crossref =     "Tenca:2018:PIS",
  pages =        "13--20",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464809",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This work presents an extension of Karatsuba's method
                 to efficiently use rectangular multipliers as a base
                 for larger multipliers. The rectangular multipliers
                 that motivate this work are the embedded $ 18 \times
                 25$-bit signed multipliers found in the DSP blocks of
                 recent Xilinx FPGAs: The traditional Karatsuba approach
                 must under-use them as square $ 18 \times 18 $ ones.
                 This work shows that rectangular multipliers can be
                 efficiently exploited in a modified Karatsuba method if
                 their input word sizes have a large greatest common
                 divider. In the Xilinx FPG A case, this can be obtained
                 by using the embedded multipliers as $ 16 \times 24 $
                 unsigned and as $ 17 \times 25$ signed ones. The
                 obtained architectures are implemented with due detail
                 to architectural features such as the pre-adders and
                 post-adders available in Xilinx DSP blocks. They are
                 synthesized and compared with traditional Karatsuba,
                 but also with (non-Karatsuba) state-of-the-art tiling
                 techniques that make use of the full rectangular
                 multipliers. The proposed technique improves resource
                 consumption and performance for multipliers of numbers
                 larger than 64 bits.",
  acknowledgement = ack-nhfb,
  keywords =     "25-bit signed multipliers; adders; ARITH-25; Computer
                 architecture; Delays; Digital arithmetic; digital
                 arithmetic; Electrical engineering; embedded
                 multipliers; field programmable gate arrays; Field
                 programmable gate arrays; Hardware; larger multipliers;
                 modified Karatsuba method; multiplying circuits;
                 rectangular multipliers; word length 64.0 bit",
}


bibtype: article
filename: fparith.bib
label: Kumm:2018:OSC
author: Martin Kumm and Oscar Gustafsson and Mario Garrido and Peter Zipf
title: Optimal Single Constant Multiplication Using Ternary Adders
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 65
number: 7
pages: 928--932
month: jul
monthnumber: 7
year: 2018
DOI: https://doi.org/10.1109/TCSII.2016.2631630
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Sat Feb 8 09:52:23 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:52:23 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
ajournal: IEEE trans. circuits syst., II Express briefs
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Martin Kumm and Oscar Gustafsson and Mario Garrido and Peter Zipf
rawtitle: Optimal Single Constant Multiplication Using Ternary Adders
keywords:
adders; Adders; Arithmetic; average adder reductions; bit shifts; circuit optimization; circuits; coefficient word sizes; Complexity theory; digital arithmetic; field programmable gate arrays; Field programmable gate arrays; field-programmable gate arrays; field-programmable gate arrays (FPGAs); fixed-point arithmetic optimization; FPGA; mathematics; multiplying circuits; numeric algorithms; optimal constant multiplication circuits; optimal single constant multiplication; Optimization; optimization methods; Signal processing algorithms; single constant coefficient multiplication; support efficient ternary adders; Topology; two-input adders; word length 22.0 bit; word length 5.0 bit

entry:
@Article{Kumm:2018:OSC,
  author =       "Martin Kumm and Oscar Gustafsson and Mario Garrido and
                 Peter Zipf",
  title =        "Optimal Single Constant Multiplication Using Ternary
                 Adders",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "65",
  number =       "7",
  pages =        "928--932",
  month =        jul,
  year =         "2018",
  DOI =          "https://doi.org/10.1109/TCSII.2016.2631630",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Feb 8 09:52:23 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE trans. circuits syst., II Express briefs",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "adders; Adders; Arithmetic; average adder reductions;
                 bit shifts; circuit optimization; circuits; coefficient
                 word sizes; Complexity theory; digital arithmetic;
                 field programmable gate arrays; Field programmable gate
                 arrays; field-programmable gate arrays;
                 field-programmable gate arrays (FPGAs); fixed-point
                 arithmetic optimization; FPGA; mathematics; multiplying
                 circuits; numeric algorithms; optimal constant
                 multiplication circuits; optimal single constant
                 multiplication; Optimization; optimization methods;
                 Signal processing algorithms; single constant
                 coefficient multiplication; support efficient ternary
                 adders; Topology; two-input adders; word length 22.0
                 bit; word length 5.0 bit",
}


bibtype: article
filename: fparith.bib
label: Lam:2018:FGF
author: Michael O. Lam and Jeffrey K. Hollingsworth
title: Fine-grained floating-point precision analysis
journal: j-IJHPCA
volume: 32
number: 2
pages: 231--245
year: 2018
CODEN: IHPCFL
DOI: https://doi.org/10.1177/1094342016652462
ISSN: 1094-3420 (print), 1741-2846 (electronic) OR 10943420 (print), 17412846 (electronic)
ISSNL: 1094-3420 OR 10943420
bibdate: Mon Nov 5 17:34:16 MST 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ijsa.bib
bibtimestamp: 2018.11.05 17:34:16 MST
URL: http://journals.sagepub.com/doi/full/10.1177/1094342016652462
fjournal: International Journal of High Performance Computing Applications
keywords: interval arithmetic; truncating arithmetic; variable-precision arithmetic
acknowledgement: ack-nhfb
journalURL: http://hpc.sagepub.com/content/by/year
rawauthor: Michael O. Lam and Jeffrey K. Hollingsworth
rawtitle: Fine-grained floating-point precision analysis
entry:
@Article{Lam:2018:FGF,
  author =       "Michael O. Lam and Jeffrey K. Hollingsworth",
  title =        "Fine-grained floating-point precision analysis",
  journal =      j-IJHPCA,
  volume =       "32",
  number =       "2",
  pages =        "231--245",
  year =         "2018",
  CODEN =        "IHPCFL",
  DOI =          "https://doi.org/10.1177/1094342016652462",
  ISSN =         "1094-3420 (print), 1741-2846 (electronic)",
  ISSN-L =       "1094-3420",
  bibdate =      "Mon Nov 5 17:34:16 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ijsa.bib",
  URL =          "http://journals.sagepub.com/doi/full/10.1177/1094342016652462",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of High Performance Computing
                 Applications",
  journal-URL =  "http://hpc.sagepub.com/content/by/year",
  keywords =     "interval arithmetic; truncating arithmetic;
                 variable-precision arithmetic",
  xxmonth =      mar,
}


bibtype: inproceedings
filename: fparith.bib
label: Langhammer:2018:HDP
author: Martin Langhammer and Gregg Baeckler
title: High Density and Performance Multiplication for FPGA
crossref: Tenca:2018:PIS
pages: 5--12
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464695
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Martin Langhammer and Gregg Baeckler
rawtitle: High Density and Performance Multiplication for {FPGA}
abstract:
Arithmetic based applications are one of the most common use cases for modern FPGAs. Currently, machine learning is emerging as the fastest growth area for FPG As, renewing an interest in low precision multiplication. There is now a new focus on multiplication in the soft fabric --- very high-density systems, consisting of many thousands of operations, are the current norm. In this paper we introduce multiplier regularization, which restructures common multiplier algorithms into smaller, and more efficient architectures. The multiplier structure is parameterizable, and results are given for a continuous range of input sizes, although the algorithm is most efficient for small input precisions. The multiplier is particularly effective for typical machine learning inferencing uses, and the presented cores can be used for dot products required for these applications. Although the examples presented here are optimized for Intel Stratix 10 devices, the concept of regularized arithmetic structures are applicable to generic FPGA LUT architectures. Results are compared to Intel Megafunction IP as well as contrasted with normalized representations of recently published results for Xilinx devices. We report a 10% to 35% smaller area, and a more significant latency reduction, in the range of 25% to 50%, for typical inferencing use cases.

keywords:
Adders; ARITH-25; arithmetic based applications; common multiplier algorithms; digital arithmetic; dot products; Field programmable gate arrays; field programmable gate arrays; generic FPGA LUT architectures; high-density systems; Intel Megafunction IP; Intel Stratix devices; IP networks; latency reduction; logic design; low precision multiplication; Machine learning; machine learning; multiplier regularization; multiplier structure; Performance evaluation; performance multiplication; regularized arithmetic structures; Routing; soft fabric-very high-density systems; table lookup; Table lookup

rawabstract:
Arithmetic based applications are one of the most common use cases for modern FPGAs. Currently, machine learning is emerging as the fastest growth area for FPG As, renewing an interest in low precision multiplication. There is now a new focus on multiplication in the soft fabric --- very high-density systems, consisting of many thousands of operations, are the current norm. In this paper we introduce multiplier regularization, which restructures common multiplier algorithms into smaller, and more efficient architectures. The multiplier structure is parameterizable, and results are given for a continuous range of input sizes, although the algorithm is most efficient for small input precisions. The multiplier is particularly effective for typical machine learning inferencing uses, and the presented cores can be used for dot products required for these applications. Although the examples presented here are optimized for Intel Stratix 10 devices, the concept of regularized arithmetic structures are applicable to generic FPGA LUT architectures. Results are compared to Intel Megafunction IP as well as contrasted with normalized representations of recently published results for Xilinx devices. We report a 10\% to 35\% smaller area, and a more significant latency reduction, in the range of 25\% to 50\%, for typical inferencing use cases.

entry:
@InProceedings{Langhammer:2018:HDP,
  author =       "Martin Langhammer and Gregg Baeckler",
  title =        "High Density and Performance Multiplication for
                 {FPGA}",
  crossref =     "Tenca:2018:PIS",
  pages =        "5--12",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464695",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Arithmetic based applications are one of the most
                 common use cases for modern FPGAs. Currently, machine
                 learning is emerging as the fastest growth area for FPG
                 As, renewing an interest in low precision
                 multiplication. There is now a new focus on
                 multiplication in the soft fabric --- very high-density
                 systems, consisting of many thousands of operations,
                 are the current norm. In this paper we introduce
                 multiplier regularization, which restructures common
                 multiplier algorithms into smaller, and more efficient
                 architectures. The multiplier structure is
                 parameterizable, and results are given for a continuous
                 range of input sizes, although the algorithm is most
                 efficient for small input precisions. The multiplier is
                 particularly effective for typical machine learning
                 inferencing uses, and the presented cores can be used
                 for dot products required for these applications.
                 Although the examples presented here are optimized for
                 Intel Stratix 10 devices, the concept of regularized
                 arithmetic structures are applicable to generic FPGA
                 LUT architectures. Results are compared to Intel
                 Megafunction IP as well as contrasted with normalized
                 representations of recently published results for
                 Xilinx devices. We report a 10\% to 35\% smaller area,
                 and a more significant latency reduction, in the range
                 of 25\% to 50\%, for typical inferencing use cases.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-25; arithmetic based applications;
                 common multiplier algorithms; digital arithmetic; dot
                 products; Field programmable gate arrays; field
                 programmable gate arrays; generic FPGA LUT
                 architectures; high-density systems; Intel Megafunction
                 IP; Intel Stratix devices; IP networks; latency
                 reduction; logic design; low precision multiplication;
                 Machine learning; machine learning; multiplier
                 regularization; multiplier structure; Performance
                 evaluation; performance multiplication; regularized
                 arithmetic structures; Routing; soft fabric-very
                 high-density systems; table lookup; Table lookup",
}


bibtype: inproceedings
filename: fparith.bib
label: Langroudi:2018:DLI
author: Seyed Hamed Fatemi Langroudi and Tej Pandit and Dhireesha Kudithipudi
editor: IEEE
title: Deep Learning Inference on Embedded Devices: Fixed-Point vs Posit
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 19--23
year: 2018
DOI: https://doi.org/10.1109/EMC2.2018.00012
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Seyed Hamed Fatemi Langroudi and Tej Pandit and Dhireesha Kudithipudi
raweditor: {IEEE}
rawtitle: Deep Learning Inference on Embedded Devices: Fixed-Point vs Posit
booktitle:
2018 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2)

rawbooktitle:
{2018 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2)}

entry:
@InProceedings{Langroudi:2018:DLI,
  author =       "Seyed Hamed Fatemi Langroudi and Tej Pandit and
                 Dhireesha Kudithipudi",
  editor =       "{IEEE}",
  booktitle =    "{2018 1st Workshop on Energy Efficient Machine
                 Learning and Cognitive Computing for Embedded
                 Applications (EMC2)}",
  title =        "Deep Learning Inference on Embedded Devices:
                 Fixed-Point vs Posit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "19--23",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/EMC2.2018.00012",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Lee:2018:APC
author: Wonyeol Lee and Rahul Sharma and Alex Aiken
title: On automatically proving the correctness of tt math.h implementations
journal: j-PACMPL
volume: 2
number: POPL
pages: 47:1--47:??
month: jan
monthnumber: 1
year: 2018
DOI: https://doi.org/10.1145/3158135
ISSN: 2475-1421 OR 24751421
bibdate: Wed Jan 10 09:45:26 MST 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2018.01.10 09:45:26 MST
fjournal: Proceedings of the ACM on Programming Languages
acknowledgement: ack-nhfb
articleno: 47
journalURL: https://pacmpl.acm.org/
rawauthor: Wonyeol Lee and Rahul Sharma and Alex Aiken
rawtitle: On automatically proving the correctness of {\tt math.h} implementations
abstract:
Industry standard implementations of tt math.h claim (often without formal proof) tight bounds on floating-point errors. We demonstrate a novel static analysis that proves these bounds and verifies the correctness of these implementations. Our key insight is a reduction of this verification task to a set of mathematical optimization problems that can be solved by off-the-shelf computer algebra systems. We use this analysis to prove the correctness of implementations in Intel's math library automatically. Prior to this work, these implementations could only be verified with significant manual effort.

rawabstract:
Industry standard implementations of {\tt math.h} claim (often without formal proof) tight bounds on floating-point errors. We demonstrate a novel static analysis that proves these bounds and verifies the correctness of these implementations. Our key insight is a reduction of this verification task to a set of mathematical optimization problems that can be solved by off-the-shelf computer algebra systems. We use this analysis to prove the correctness of implementations in Intel's math library automatically. Prior to this work, these implementations could only be verified with significant manual effort.

entry:
@Article{Lee:2018:APC,
  author =       "Wonyeol Lee and Rahul Sharma and Alex Aiken",
  title =        "On automatically proving the correctness of {\tt
                 math.h} implementations",
  journal =      j-PACMPL,
  volume =       "2",
  number =       "POPL",
  pages =        "47:1--47:??",
  month =        jan,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3158135",
  ISSN =         "2475-1421",
  bibdate =      "Wed Jan 10 09:45:26 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  abstract =     "Industry standard implementations of {\tt math.h}
                 claim (often without formal proof) tight bounds on
                 floating-point errors. We demonstrate a novel static
                 analysis that proves these bounds and verifies the
                 correctness of these implementations. Our key insight
                 is a reduction of this verification task to a set of
                 mathematical optimization problems that can be solved
                 by off-the-shelf computer algebra systems. We use this
                 analysis to prove the correctness of implementations in
                 Intel's math library automatically. Prior to this work,
                 these implementations could only be verified with
                 significant manual effort.",
  acknowledgement = ack-nhfb,
  articleno =    "47",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Lehoczky:2018:HLN
crossref: ACM:2018:CNG
pages: 1--7
year: 2018
DOI: https://doi.org/10.1145/3190339.3190343
bibdate: Mon Dec 11 09:02:49 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 09:02:49 ???
keywords: posit arithmetic; universal number arithmetic
acknowledgement: ack-nhfb
articleno: 4
author:
Zoltan Lehoczky and Andras Retzler and Richard Toth and Almos Szabo and Benedek Farkas and Krisztian Somogyi

title:
High-level .NET Software Implementations of Unum Type I and Posit with Simultaneous FPGA Implementation Using Hastlayer

abstract:
The unum arithmetic framework has been proposed by Gustafson, D. J. to address the short-comings of the IEEE 754 Standard's floating-point. In this paper, we present our software and hardware implementations of Type I and posit unums. The software implementation is built on the .NET platform as an open source library written in the C# programming language. We automatically create hardware implementations using our .NET to FPGA converter tool called Hastlayer. The amount of hardware resources needed for addition operations are quantified, and the performance of software and prototype hardware for posits are compared. We show that posits are significantly more hardware friendly than Type I unums. Furthermore, our posit FPGA implementation is about 2.04 times more efficient per clock cycle than its software implementation.

rawabstract:
The unum arithmetic framework has been proposed by Gustafson, D. J. to address the short-comings of the IEEE 754 Standard's floating-point. In this paper, we present our software and hardware implementations of Type I and posit unums. The software implementation is built on the .NET platform as an open source library written in the C\# programming language. We automatically create hardware implementations using our .NET to FPGA converter tool called Hastlayer. The amount of hardware resources needed for addition operations are quantified, and the performance of software and prototype hardware for posits are compared. We show that posits are significantly more hardware friendly than Type I unums. Furthermore, our posit FPGA implementation is about 2.04 times more efficient per clock cycle than its software implementation.

rawauthor:
Zolt{\'a}n Leh{\'o}czky and Andr{\'a}s Retzler and Rich{\'a}rd T{\'o}th and {\'A}lmos Szab{\'o} and Benedek Farkas and Kriszti{\'a}n Somogyi

rawtitle:
High-level {.NET} Software Implementations of Unum {Type I} and Posit with Simultaneous {FPGA} Implementation Using {Hastlayer}

entry:
@InProceedings{Lehoczky:2018:HLN,
  author =       "Zolt{\'a}n Leh{\'o}czky and Andr{\'a}s Retzler and
                 Rich{\'a}rd T{\'o}th and {\'A}lmos Szab{\'o} and
                 Benedek Farkas and Kriszti{\'a}n Somogyi",
  title =        "High-level {.NET} Software Implementations of Unum
                 {Type I} and Posit with Simultaneous {FPGA}
                 Implementation Using {Hastlayer}",
  crossref =     "ACM:2018:CNG",
  pages =        "1--7",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190343",
  bibdate =      "Mon Dec 11 09:02:49 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The unum arithmetic framework has been proposed by
                 Gustafson, D. J. to address the short-comings of the
                 IEEE 754 Standard's floating-point. In this paper, we
                 present our software and hardware implementations of
                 Type I and posit unums. The software implementation is
                 built on the .NET platform as an open source library
                 written in the C\# programming language. We
                 automatically create hardware implementations using our
                 .NET to FPGA converter tool called Hastlayer. The
                 amount of hardware resources needed for addition
                 operations are quantified, and the performance of
                 software and prototype hardware for posits are
                 compared. We show that posits are significantly more
                 hardware friendly than Type I unums. Furthermore, our
                 posit FPGA implementation is about 2.04 times more
                 efficient per clock cycle than its software
                 implementation.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  keywords =     "posit arithmetic; universal number arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Leong:2018:SV
author: Cerlane Leong
title: SoftPosit Version 0.4.1rc
pages: 1--7
year: 2018
bibdate: Sat Dec 16 15:18:01 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 15:18:01 ???
URL: https://gitlab.com/cerlane/SoftPosit
acknowledgement: ack-nhfb
howpublished: Web source code.
rawauthor: Cerlane Leong
rawtitle: {SoftPosit} Version 0.4.1rc
entry:
@Misc{Leong:2018:SV,
  author =       "Cerlane Leong",
  title =        "{SoftPosit} Version 0.4.1rc",
  howpublished = "Web source code.",
  year =         "2018",
  bibdate =      "Sat Dec 16 15:18:01 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://gitlab.com/cerlane/SoftPosit",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2018:DEA
author: He Li and James J. Davis and John Wickerson and George A. Constantinides
title: Digit Elision for Arbitrary-accuracy Iterative Computation
crossref: Tenca:2018:PIS
pages: 107--114
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464691
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: He Li and James J. Davis and John Wickerson and George A. Constantinides
rawtitle: Digit Elision for Arbitrary-accuracy Iterative Computation
abstract:
We recently proposed the first hardware architecture enabling the iterative solution of systems of linear equations to accuracies limited only by the amount of available memory. This technique, named ARCHITECT, achieves exact numeric computation by using online arithmetic to allow the refinement of results from earlier iterations over time, eschewing rounding error. ARCHITECT has a key drawback, however: often, many more digits than strictly necessary are generated, with this problem exacerbating the more accurate a solution is sought. In this paper, we infer the locations of these superfluous digits within stationary iterative calculations by exploiting online arithmetic's digit dependencies and using forward error analysis. We demonstrate that their lack of computation is guaranteed not to affect the ability to reach a solution of any accuracy. Versus ARCHITECT, our illustrative hardware implementation achieves a geometric mean $ 20.1 times $ speedup in the solution of a set of representative linear systems through the avoidance of redundant digit calculation. For the computation of high-precision results, we also obtain an up-to $ 22.4 times $ memory requirement reduction over the same baseline. Finally, we demonstrate that solvers implemented following our proposals can show superiority over conventional arithmetic implementations by virtue of their runtime-tunable precisions.

keywords:
arbitrary-accuracy iterative computation; ARCHITECT; ARITH-25; arithmetic implementations; Delays; digit dependencies; digit elision; digital arithmetic; error analysis; exact numeric computation; forward error analysis; Hardware; hardware architecture; iterative methods; Iterative methods; iterative solution; Jacobian matrices; linear equations; Linear systems; linear systems; memory requirement reduction; online arithmetic; Proposals; redundant digit calculation; rounding error; Runtime; stationary iterative calculations; superfluous digits

rawabstract:
We recently proposed the first hardware architecture enabling the iterative solution of systems of linear equations to accuracies limited only by the amount of available memory. This technique, named ARCHITECT, achieves exact numeric computation by using online arithmetic to allow the refinement of results from earlier iterations over time, eschewing rounding error. ARCHITECT has a key drawback, however: often, many more digits than strictly necessary are generated, with this problem exacerbating the more accurate a solution is sought. In this paper, we infer the locations of these superfluous digits within stationary iterative calculations by exploiting online arithmetic's digit dependencies and using forward error analysis. We demonstrate that their lack of computation is guaranteed not to affect the ability to reach a solution of any accuracy. Versus ARCHITECT, our illustrative hardware implementation achieves a geometric mean $ 20.1 \times $ speedup in the solution of a set of representative linear systems through the avoidance of redundant digit calculation. For the computation of high-precision results, we also obtain an up-to $ 22.4 \times $ memory requirement reduction over the same baseline. Finally, we demonstrate that solvers implemented following our proposals can show superiority over conventional arithmetic implementations by virtue of their runtime-tunable precisions.

entry:
@InProceedings{Li:2018:DEA,
  author =       "He Li and James J. Davis and John Wickerson and George
                 A. Constantinides",
  title =        "Digit Elision for Arbitrary-accuracy Iterative
                 Computation",
  crossref =     "Tenca:2018:PIS",
  pages =        "107--114",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464691",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We recently proposed the first hardware architecture
                 enabling the iterative solution of systems of linear
                 equations to accuracies limited only by the amount of
                 available memory. This technique, named ARCHITECT,
                 achieves exact numeric computation by using online
                 arithmetic to allow the refinement of results from
                 earlier iterations over time, eschewing rounding error.
                 ARCHITECT has a key drawback, however: often, many more
                 digits than strictly necessary are generated, with this
                 problem exacerbating the more accurate a solution is
                 sought. In this paper, we infer the locations of these
                 superfluous digits within stationary iterative
                 calculations by exploiting online arithmetic's digit
                 dependencies and using forward error analysis. We
                 demonstrate that their lack of computation is
                 guaranteed not to affect the ability to reach a
                 solution of any accuracy. Versus ARCHITECT, our
                 illustrative hardware implementation achieves a
                 geometric mean $ 20.1 \times $ speedup in the solution
                 of a set of representative linear systems through the
                 avoidance of redundant digit calculation. For the
                 computation of high-precision results, we also obtain
                 an up-to $ 22.4 \times $ memory requirement reduction
                 over the same baseline. Finally, we demonstrate that
                 solvers implemented following our proposals can show
                 superiority over conventional arithmetic
                 implementations by virtue of their runtime-tunable
                 precisions.",
  acknowledgement = ack-nhfb,
  keywords =     "arbitrary-accuracy iterative computation; ARCHITECT;
                 ARITH-25; arithmetic implementations; Delays; digit
                 dependencies; digit elision; digital arithmetic; error
                 analysis; exact numeric computation; forward error
                 analysis; Hardware; hardware architecture; iterative
                 methods; Iterative methods; iterative solution;
                 Jacobian matrices; linear equations; Linear systems;
                 linear systems; memory requirement reduction; online
                 arithmetic; Proposals; redundant digit calculation;
                 rounding error; Runtime; stationary iterative
                 calculations; superfluous digits",
}


bibtype: misc
filename: fparith.bib
label: Lie:2018:FPU
author: Sean Lie and Michael Edwin James and Michael Morrison and Gary R. Lauterbach and Srikanth Arekapudi
title: Floating-point unit stochastic rounding for accelerated deep learning
pages: 107--114
day: 13
month: apr
monthnumber: 4
year: 2018
bibdate: Fri Sep 22 17:25:05 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 17:25:05 ???
note: Patent granted 20 September 2022; expires 29 November 2038.
acknowledgement: ack-nhfb
howpublished: U.S. Patent US11449574B2
rawauthor: Sean Lie and Michael Edwin James and Michael Morrison and Gary R. Lauterbach and Srikanth Arekapudi
rawnote: Patent granted 20 September 2022; expires 29 November 2038.
rawtitle: Floating-point unit stochastic rounding for accelerated deep learning
abstract:
Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has a respective floating-point unit enabled to perform stochastic rounding, thus in some circumstances enabling reducing systematic bias in long dependency chains of floating-point computations. The long dependency chains of floating-point computations are performed, e.g., to train a neural network or to perform inference with respect to a trained neural network.

rawabstract:
Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has a respective floating-point unit enabled to perform stochastic rounding, thus in some circumstances enabling reducing systematic bias in long dependency chains of floating-point computations. The long dependency chains of floating-point computations are performed, e.g., to train a neural network or to perform inference with respect to a trained neural network.

entry:
@Misc{Lie:2018:FPU,
  author =       "Sean Lie and Michael Edwin James and Michael Morrison
                 and Gary R. Lauterbach and Srikanth Arekapudi",
  title =        "Floating-point unit stochastic rounding for
                 accelerated deep learning",
  howpublished = "U.S. Patent US11449574B2",
  day =          "13",
  month =        apr,
  year =         "2018",
  bibdate =      "Fri Sep 22 17:25:05 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Patent granted 20 September 2022; expires 29 November
                 2038.",
  abstract =     "Techniques in advanced deep learning provide
                 improvements in one or more of accuracy, performance,
                 and energy efficiency. An array of processing elements
                 comprising a portion of a neural network accelerator
                 performs flow-based computations on wavelets of data.
                 Each processing element has a respective compute
                 element and a respective routing element. Each compute
                 element has a respective floating-point unit enabled to
                 perform stochastic rounding, thus in some circumstances
                 enabling reducing systematic bias in long dependency
                 chains of floating-point computations. The long
                 dependency chains of floating-point computations are
                 performed, e.g., to train a neural network or to
                 perform inference with respect to a trained neural
                 network.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lindstrom:2018:UCR
author: Peter Lindstrom and Scott Lloyd and Jeffrey Hittinger
title: Universal Coding of the Reals: Alternatives to IEEE Floating Point
crossref: ACM:2018:CNG
pages: 1--14
year: 2018
DOI: https://doi.org/10.1145/3190339.3190344
bibdate: Sun Dec 10 14:24:09 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.10 14:24:09 ???
acknowledgement: ack-nhfb
articleno: 5
rawauthor: Peter Lindstrom and Scott Lloyd and Jeffrey Hittinger
rawtitle: Universal Coding of the Reals: Alternatives to {IEEE} Floating Point
abstract:
We propose a modular framework for representing the real numbers that generalizes IEEE, posits, and related floating-point number systems, and which has its roots in universal codes for the positive integers such as the Elias codes. This framework unifies several known but seemingly unrelated representations within a single schema while also introducing new representations. We particularly focus on variable-length encoding of the binary exponent and on the manner in which fraction bits are mapped to values. Our framework builds upon and shares many of the attractive properties of posits but allows for independent experimentation with exponent codes, fraction mappings, reciprocal closure, rounding modes, handling of under- and overflow, and underlying precision.

rawabstract:
We propose a modular framework for representing the real numbers that generalizes IEEE, posits, and related floating-point number systems, and which has its roots in universal codes for the positive integers such as the Elias codes. This framework unifies several known but seemingly unrelated representations within a single schema while also introducing new representations. We particularly focus on variable-length encoding of the binary exponent and on the manner in which fraction bits are mapped to values. Our framework builds upon and shares many of the attractive properties of posits but allows for independent experimentation with exponent codes, fraction mappings, reciprocal closure, rounding modes, handling of under- and overflow, and underlying precision.

entry:
@InProceedings{Lindstrom:2018:UCR,
  author =       "Peter Lindstrom and Scott Lloyd and Jeffrey
                 Hittinger",
  title =        "Universal Coding of the Reals: Alternatives to {IEEE}
                 Floating Point",
  crossref =     "ACM:2018:CNG",
  pages =        "1--14",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190344",
  bibdate =      "Sun Dec 10 14:24:09 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We propose a modular framework for representing the
                 real numbers that generalizes IEEE, posits, and related
                 floating-point number systems, and which has its roots
                 in universal codes for the positive integers such as
                 the Elias codes. This framework unifies several known
                 but seemingly unrelated representations within a single
                 schema while also introducing new representations. We
                 particularly focus on variable-length encoding of the
                 binary exponent and on the manner in which fraction
                 bits are mapped to values. Our framework builds upon
                 and shares many of the attractive properties of posits
                 but allows for independent experimentation with
                 exponent codes, fraction mappings, reciprocal closure,
                 rounding modes, handling of under- and overflow, and
                 underlying precision.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
}


bibtype: inproceedings
filename: fparith.bib
label: Liu:2018:CRA
author: Weiqiang Liu and Jing Li and Tao Xu and Chenghua Wang and Paolo Montuschi and Fabrizio Lombardi
title: Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design
crossref: Tenca:2018:PIS
pages: 92--98
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464807
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Weiqiang Liu and Jing Li and Tao Xu and Chenghua Wang and Paolo Montuschi and Fabrizio Lombardi
rawtitle: Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design
abstract:
This paper proposes a new design of an approximate hybrid divider (AXHD), which combines the restoring array and the logarithmic dividers to achieve an excellent tradeoff between accuracy and hardware performance. Exact restoring divider cells (EXDCrs) are used to generate the MSBs of the quotient for attaining a high accuracy; the other quotient digits are processed by a logarithmic divider as inexact scheme to improve figures of merit such as power consumption, area and delay. The proposed AXHD is evaluated and analyzed using error and hardware metrics. The proposed design is also compared with the exact restoring divider (EXDr) and previous approximate restoring dividers (AXDrs). The results show that the proposed design achieves very good performance in terms of accuracy and hardware; case studies for image processing also show the validity of the proposed designs.

keywords:
Adders; Approximate Computing; approximate hybrid divider design; approximate restoring dividers; ARITH-25; AXDrs; AXHD; circuit stability; dividing circuits; Electronic mail; Error analysis; exact restoring divider cells; EXDCrs; Hardware; hardware metrics; hardware performance; image processing; Image restoration; logarithmic divider; Logarithmic Divider; logic design; Low Power; MSBs; Power demand; quotient digit processing; restoring array; Restoring Array Divider

rawabstract:
This paper proposes a new design of an approximate hybrid divider (AXHD), which combines the restoring array and the logarithmic dividers to achieve an excellent tradeoff between accuracy and hardware performance. Exact restoring divider cells (EXDCrs) are used to generate the MSBs of the quotient for attaining a high accuracy; the other quotient digits are processed by a logarithmic divider as inexact scheme to improve figures of merit such as power consumption, area and delay. The proposed AXHD is evaluated and analyzed using error and hardware metrics. The proposed design is also compared with the exact restoring divider (EXDr) and previous approximate restoring dividers (AXDrs). The results show that the proposed design achieves very good performance in terms of accuracy and hardware; case studies for image processing also show the validity of the proposed designs.

entry:
@InProceedings{Liu:2018:CRA,
  author =       "Weiqiang Liu and Jing Li and Tao Xu and Chenghua Wang
                 and Paolo Montuschi and Fabrizio Lombardi",
  title =        "Combining Restoring Array and Logarithmic Dividers
                 into an Approximate Hybrid Design",
  crossref =     "Tenca:2018:PIS",
  pages =        "92--98",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464807",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper proposes a new design of an approximate
                 hybrid divider (AXHD), which combines the restoring
                 array and the logarithmic dividers to achieve an
                 excellent tradeoff between accuracy and hardware
                 performance. Exact restoring divider cells (EXDCrs) are
                 used to generate the MSBs of the quotient for attaining
                 a high accuracy; the other quotient digits are
                 processed by a logarithmic divider as inexact scheme to
                 improve figures of merit such as power consumption,
                 area and delay. The proposed AXHD is evaluated and
                 analyzed using error and hardware metrics. The proposed
                 design is also compared with the exact restoring
                 divider (EXDr) and previous approximate restoring
                 dividers (AXDrs). The results show that the proposed
                 design achieves very good performance in terms of
                 accuracy and hardware; case studies for image
                 processing also show the validity of the proposed
                 designs.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; Approximate Computing; approximate hybrid
                 divider design; approximate restoring dividers;
                 ARITH-25; AXDrs; AXHD; circuit stability; dividing
                 circuits; Electronic mail; Error analysis; exact
                 restoring divider cells; EXDCrs; Hardware; hardware
                 metrics; hardware performance; image processing; Image
                 restoration; logarithmic divider; Logarithmic Divider;
                 logic design; Low Power; MSBs; Power demand; quotient
                 digit processing; restoring array; Restoring Array
                 Divider",
}


bibtype: article
filename: fparith.bib
label: Loeffler:2018:WBP
author: John Loeffler
journal: Interesting Engineering
pages: ??--??
day: 22
month: nov
monthnumber: 11
year: 2018
bibdate: Fri Nov 23 11:32:14 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.11.23 11:32:14 ???
URL: https://interestingengineering.com/when-bad-programming-turns-deadly
keywords: floating-point arithmetic; Patriot missile; radiological equipment software malfunction
acknowledgement: ack-nhfb
rawauthor: John Loeffler
title:
When Bad Programming Turns Deadly: A look at programming disasters and how bad programming can be deadly

rawtitle:
When Bad Programming Turns Deadly: A look at programming disasters and how bad programming can be deadly

entry:
@Article{Loeffler:2018:WBP,
  author =       "John Loeffler",
  title =        "When Bad Programming Turns Deadly: A look at
                 programming disasters and how bad programming can be
                 deadly",
  journal =      "Interesting Engineering",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "22",
  month =        nov,
  year =         "2018",
  bibdate =      "Fri Nov 23 11:32:14 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://interestingengineering.com/when-bad-programming-turns-deadly",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic; Patriot missile;
                 radiological equipment software malfunction",
}


bibtype: misc
filename: fparith.bib
label: Marchese:2018:ACM
author: Sergio Marchese
pages: ??--??
day: 27
month: sep
monthnumber: 9
year: 2018
bibdate: Fri Sep 28 06:12:07 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.09.28 06:12:07 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Sergio Marchese
title:
AI Chips Must Get The Floating-Point Math Right: Formal verification of FPUs is no longer a prerogative of big companies spending big bucks

rawtitle:
{AI} Chips Must Get The Floating-Point Math Right: Formal verification of {FPUs} is no longer a prerogative of big companies spending big bucks

entry:
@Misc{Marchese:2018:ACM,
  author =       "Sergio Marchese",
  title =        "{AI} Chips Must Get The Floating-Point Math Right:
                 Formal verification of {FPUs} is no longer a
                 prerogative of big companies spending big bucks",
  howpublished = "Web site.",
  day =          "27",
  month =        sep,
  year =         "2018",
  bibdate =      "Fri Sep 28 06:12:07 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Mikaitis:2018:AFP
title: Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip
crossref: Tenca:2018:PIS
pages: 37--44
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464785
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawtitle: Approximate Fixed-Point Elementary Function Accelerator for the {SpiNNaker-2} Neuromorphic Chip
author:
Mantas Mikaitis and David R. Lester and Delong Shang and Steve Furber and Gengting Liu and Jim Garside and Stefan Scholze and Sebastian Hoppner and Andreas Dixius

abstract:
Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks (SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more ex components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

keywords:
Adders; algorithmic level approximation control; approximate arithmetic; approximate fixed-point elementary function accelerator; ARITH-25; Biological system modeling; biologically inspired spiking-neural-networks; complex neural models; Computational modeling; Convergence; differential equations; digital neuromorphic chip; energy efficiency; exponential function; fast exponential function; FDSOI process; fixed-point arithmetic; hardware accelerators; iterative algorithms; iterative methods; logarithm function; Mathematical model; memory requirements; memory resources; MPSoC; neural chips; neuromorphic chip prototype; neuromorphic computing; Neuromorphics; next generation SpiNNaker chip; parameterized elementary function unit; pre-calculated look-up tables; single hardware accelerator; size 22.0 nm; SNN algorithms; SpiNNaker-2 neuromorphic chip; SpiNNaker2; table lookup; Table lookup

rawabstract:
Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks (SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more ex components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

rawauthor:
Mantas Mikaitis and David R. Lester and Delong Shang and Steve Furber and Gengting Liu and Jim Garside and Stefan Scholze and Sebastian H{\"o}ppner and Andreas Dixius

entry:
@InProceedings{Mikaitis:2018:AFP,
  author =       "Mantas Mikaitis and David R. Lester and Delong Shang
                 and Steve Furber and Gengting Liu and Jim Garside and
                 Stefan Scholze and Sebastian H{\"o}ppner and Andreas
                 Dixius",
  title =        "Approximate Fixed-Point Elementary Function
                 Accelerator for the {SpiNNaker-2} Neuromorphic Chip",
  crossref =     "Tenca:2018:PIS",
  pages =        "37--44",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464785",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Neuromorphic chips are used to model biologically
                 inspired Spiking-Neural-Networks (SNNs) where most
                 models are based on differential equations. Equations
                 for most SNN algorithms usually contain variables with
                 one or more ex components. SpiNNaker is a digital
                 neuromorphic chip that has so far been using
                 pre-calculated look-up tables for exponential function.
                 However this approach is limited because the memory
                 requirements grow as more complex neural models are
                 developed. To save already limited memory resources in
                 the next generation SpiNNaker chip, we are including a
                 fast exponential function in the silicon. In this paper
                 we analyse iterative algorithms for elementary
                 functions and show how to build a single hardware
                 accelerator for exp and natural log, for a neuromorphic
                 chip prototype, to be manufactured in a 22 nm FDSOI
                 process. We present the accelerator that has
                 algorithmic level approximation control, allowing it to
                 trade precision for latency and energy efficiency. As
                 an addition to neuromorphic chip application, we
                 provide analysis of a parameterized elementary function
                 unit that can be tailored for other systems with
                 different power, area, accuracy and latency
                 constraints.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; algorithmic level approximation control;
                 approximate arithmetic; approximate fixed-point
                 elementary function accelerator; ARITH-25; Biological
                 system modeling; biologically inspired
                 spiking-neural-networks; complex neural models;
                 Computational modeling; Convergence; differential
                 equations; digital neuromorphic chip; energy
                 efficiency; exponential function; fast exponential
                 function; FDSOI process; fixed-point arithmetic;
                 hardware accelerators; iterative algorithms; iterative
                 methods; logarithm function; Mathematical model; memory
                 requirements; memory resources; MPSoC; neural chips;
                 neuromorphic chip prototype; neuromorphic computing;
                 Neuromorphics; next generation SpiNNaker chip;
                 parameterized elementary function unit; pre-calculated
                 look-up tables; single hardware accelerator; size 22.0
                 nm; SNN algorithms; SpiNNaker-2 neuromorphic chip;
                 SpiNNaker2; table lookup; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Moroz:2018:FCI
title: Fast calculation of inverse square root with the use of magic constant --- analytical approach
journal: j-APPL-MATH-COMP
volume: 316
pages: 245--255
day: 1
month: jan
monthnumber: 1
year: 2018
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2017.08.025
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Tue Oct 10 15:56:03 MDT 2017
bibtimestamp: 2017.10.10 15:56:03 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0096300317305763
fjournal: Applied Mathematics and Computation
keywords: single-precision 32-bit IEEE 754 binary arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawtitle: Fast calculation of inverse square root with the use of magic constant --- analytical approach
author:
Leonid V. Moroz and Cezary J. Walczyk and Andriy Hrynchyshyn and Vijay Holimath and Jan L. Cieslinski

bibsource:
https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawauthor:
Leonid V. Moroz and Cezary J. Walczyk and Andriy Hrynchyshyn and Vijay Holimath and Jan L. Cie{\'s}li{\'n}ski

entry:
@Article{Moroz:2018:FCI,
  author =       "Leonid V. Moroz and Cezary J. Walczyk and Andriy
                 Hrynchyshyn and Vijay Holimath and Jan L.
                 Cie{\'s}li{\'n}ski",
  title =        "Fast calculation of inverse square root with the use
                 of magic constant --- analytical approach",
  journal =      j-APPL-MATH-COMP,
  volume =       "316",
  number =       "??",
  pages =        "245--255",
  day =          "1",
  month =        jan,
  year =         "2018",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2017.08.025",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Tue Oct 10 15:56:03 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0096300317305763",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
  keywords =     "single-precision 32-bit IEEE 754 binary arithmetic",
}


bibtype: book
filename: fparith.bib
label: Muller:2018:HFP
title: Handbook of Floating-Point Arithmetic
publisher: pub-BIRKHAUSER
address: pub-BIRKHAUSER:adr
edition: Second
pages: 245--255
year: 2018
DOI: https://doi.org/10.1007/978-3-319-76526-6
ISBN: 3-319-76525-6, 3-319-76526-4 (e-book) OR 3319765256, 3319765264 (ebook)
ISBN13: 978-3-319-76525-9, 978-3-319-76526-6 (e-book) OR 9783319765259, 9783319765266 (ebook)
LCCN: QA76.9.C62
bibdate: Fri Jun 1 06:59:01 MDT 2018
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.06.01 06:59:01 MDT
acknowledgement: ack-nhfb
rawtitle: Handbook of Floating-Point Arithmetic
author:
Jean-Michel Muller and Nicolas Brunie and Florent de Dinechin and Claude-Pierre Jeannerod and Mioara Joldes and Vincent Lefevre and Guillaume Melquiond and Nathalie Revol and Serge Torres

abstract:
This handbook aims to provide a complete overview of modern floating-point arithmetic. This includes a detailed treatment of the current (IEEE-754) and next (preliminarily called IEEE-754R) standards for floating-point arithmetic.

subject:
Floating-point arithmetic; Handbooks, manuals, etc; Computer arithmetic; COMPUTERS / Computer Literacy; COMPUTERS / Computer Science; COMPUTERS / Data Processing; COMPUTERS / Hardware / General; COMPUTERS / Information Technology; COMPUTERS / Machine Theory; COMPUTERS / Reference.

TOC:
Intro Contents List of Figures List of Tables Preface I Introduction, Basic Definitions, and Standards 1 Introduction 1.1 Some History 1.2 Desirable Properties 1.3 Some Strange Behaviors 1.3.1 Some famous bugs 1.3.2 Difficult problems 1.3.2.1 A sequence that seems to converge to a wrong limit 1.3.2.2 The Chaotic Bank Society 1.3.2.3 Rump's example 2 Definitions and Basic Notions 2.1 Floating-Point Numbers 2.1.1 Main definitions 2.1.2 Normalized representations, normal and subnormal numbers 2.1.3 A note on underflow 2.1.4 Special floating-point data 2.2 Rounding 2.2.1 Rounding functions 2.2.2 Useful properties 2.3 Tools for Manipulating Floating-Point Errors 2.3.1 Relative error due to rounding 2.3.2 The ulp function 2.3.3 Link between errors in ulps and relative errors 2.3.3.1 Converting from errors in ulps to relative errors 2.3.3.2 Converting from relative errors to errors in ulps 2.3.3.3 Loss of information during these conversions 2.3.4 An example: iterated products 2.4 The Fused Multiply-Add (FMA) Instruction 2.5 Exceptions 2.6 Lost and Preserved Properties of Real Arithmetic 2.7 Note on the Choice of the Radix 2.7.1 Representation errors 2.7.2 A case for radix 10 2.8 Reproducibility 3 Floating-Point Formats and Environment 3.1 The IEEE 754-2008 Standard 3.1.1 Formats 3.1.1.1 Binary interchange format encodings 3.1.1.2 Decimal interchange format encodings 3.1.1.3 Larger formats 3.1.1.4 Extended and extendable precisions 3.1.1.5 Little-endian, big-endian 3.1.2 Attributes and rounding 3.1.2.1 Rounding direction attributes 3.1.2.2 Alternate exception-handling attributes 3.1.2.3 Preferred width attributes 3.1.2.4 Value-changing optimization attributes 3.1.2.5 Reproducibility attributes 3.1.3 Operations specified by the standard 3.1.3.1 Arithmetic operations and square root 3.1.3.2 Remainders 3.1.3.3 Preferred exponent for arithmetic operations in the decimal format 3.1.3.4 scaleB and logB 3.1.3.5 Miscellaneous 3.1.4 Comparisons 3.1.5 Conversions to/from string representations 3.1.6 Default exception handling 3.1.6.1 Invalid operation 3.1.6.2 Division by zero 3.1.6.3 Overflow 3.1.6.4 Underflow 3.1.6.5 Inexact 3.1.7 Special values 3.1.7.1 NaN: Not a Number 3.1.7.2 Arithmetic of infinities and zeros 3.1.8 Recommended functions 3.2 On the Possible Hidden Use of a Higher Internal Precision 3.3 Revision of the IEEE 754-2008 Standard 3.4 Floating-Point Hardware in Current Processors 3.4.1 The common hardware denominator 3.4.2 Fused multiply-add 3.4.3 Extended precision and 128-bit formats 3.4.4 Rounding and precision control 3.4.5 SIMD instructions 3.4.6 Binary16 (half-precision) support 3.4.7 Decimal arithmetic 3.4.8 The legacy x87 processor 3.5 Floating-Point Hardware in Recent Graphics Processing Units 3.6 IEEE Support in Programming Languages 3.7 Checking the Environment 3.7.1 MACHAR 3.7.2 Paranoia ldots Basic Properties and Algorithms Enhanced Floating-Point Sums, Dot Products, and Polynomial Values Languages and Compilers Algorithms for the Basic Operations Hardware Implementation of Floating-Point Arithmetic Software Implementation of Floating-Point Arithmetic Evaluating Floating-Point Elementary Functions Complex Numbers Interval Arithmetic Verifying Floating-Point Algorithms Extending the Precision

rawabstract:
This handbook aims to provide a complete overview of modern floating-point arithmetic. This includes a detailed treatment of the current (IEEE-754) and next (preliminarily called IEEE-754R) standards for floating-point arithmetic.

rawauthor:
Jean-Michel Muller and Nicolas Brunie and Florent de Dinechin and Claude-Pierre Jeannerod and Mioara Joldes and Vincent Lef{\`e}vre and Guillaume Melquiond and Nathalie Revol and Serge Torres

shortTOC:
Introduction / 3--14 Definitions and Basic Notions / 15--45 Floating-Point Formats and Environment / 47--93 Basic Properties and Algorithms / 97--162 Enhanced Floating-Point Sums, Dot Products, and Polynomial Values / 163--192 Languages and Compilers / 193--230 Algorithms for the Basic Operations / 233--266 Hardware Implementation of Floating-Point Arithmetic / 267--320 Software Implementation of Floating-Point Arithmetic / 321--374 Evaluating Floating-Point Elementary Functions / 375--433 Complex Numbers / 437--452 Interval Arithmetic / 453--477 Verifying Floating-Point Algorithms / 479--511 Extending the Precision / 513--552

rawshortTOC:
Introduction / 3--14 \\ Definitions and Basic Notions / 15--45 \\ Floating-Point Formats and Environment / 47--93 \\ Basic Properties and Algorithms / 97--162 \\ Enhanced Floating-Point Sums, Dot Products, and Polynomial Values / 163--192 \\ Languages and Compilers / 193--230 \\ Algorithms for the Basic Operations / 233--266 \\ Hardware Implementation of Floating-Point Arithmetic / 267--320 \\ Software Implementation of Floating-Point Arithmetic / 321--374 \\ Evaluating Floating-Point Elementary Functions / 375--433 \\ Complex Numbers / 437--452 \\ Interval Arithmetic / 453--477 \\ Verifying Floating-Point Algorithms / 479--511 \\ Extending the Precision / 513--552

rawTOC:
Intro \\ Contents \\ List of Figures \\ List of Tables \\ Preface \\ I Introduction, Basic Definitions, and Standards \\ 1 Introduction \\ 1.1 Some History \\ 1.2 Desirable Properties \\ 1.3 Some Strange Behaviors \\ 1.3.1 Some famous bugs \\ 1.3.2 Difficult problems \\ 1.3.2.1 A sequence that seems to converge to a wrong limit \\ 1.3.2.2 The Chaotic Bank Society \\ 1.3.2.3 Rump's example \\ 2 Definitions and Basic Notions \\ 2.1 Floating-Point Numbers \\ 2.1.1 Main definitions \\ 2.1.2 Normalized representations, normal and subnormal numbers \\ 2.1.3 A note on underflow \\ 2.1.4 Special floating-point data \\ 2.2 Rounding \\ 2.2.1 Rounding functions \\ 2.2.2 Useful properties \\ 2.3 Tools for Manipulating Floating-Point Errors \\ 2.3.1 Relative error due to rounding \\ 2.3.2 The ulp function \\ 2.3.3 Link between errors in ulps and relative errors \\ 2.3.3.1 Converting from errors in ulps to relative errors \\ 2.3.3.2 Converting from relative errors to errors in ulps \\ 2.3.3.3 Loss of information during these conversions \\ 2.3.4 An example: iterated products \\ 2.4 The Fused Multiply-Add (FMA) Instruction \\ 2.5 Exceptions \\ 2.6 Lost and Preserved Properties of Real Arithmetic \\ 2.7 Note on the Choice of the Radix \\ 2.7.1 Representation errors \\ 2.7.2 A case for radix 10 \\ 2.8 Reproducibility \\ 3 Floating-Point Formats and Environment \\ 3.1 The IEEE 754-2008 Standard \\ 3.1.1 Formats \\ 3.1.1.1 Binary interchange format encodings \\ 3.1.1.2 Decimal interchange format encodings \\ 3.1.1.3 Larger formats \\ 3.1.1.4 Extended and extendable precisions \\ 3.1.1.5 Little-endian, big-endian \\ 3.1.2 Attributes and rounding \\ 3.1.2.1 Rounding direction attributes \\ 3.1.2.2 Alternate exception-handling attributes \\ 3.1.2.3 Preferred width attributes \\ 3.1.2.4 Value-changing optimization attributes \\ 3.1.2.5 Reproducibility attributes \\ 3.1.3 Operations specified by the standard \\ 3.1.3.1 Arithmetic operations and square root \\ 3.1.3.2 Remainders \\ 3.1.3.3 Preferred exponent for arithmetic operations in the decimal format \\ 3.1.3.4 scaleB and logB \\ 3.1.3.5 Miscellaneous \\ 3.1.4 Comparisons \\ 3.1.5 Conversions to/from string representations \\ 3.1.6 Default exception handling \\ 3.1.6.1 Invalid operation \\ 3.1.6.2 Division by zero \\ 3.1.6.3 Overflow \\ 3.1.6.4 Underflow \\ 3.1.6.5 Inexact \\ 3.1.7 Special values \\ 3.1.7.1 NaN: Not a Number \\ 3.1.7.2 Arithmetic of infinities and zeros \\ 3.1.8 Recommended functions \\ 3.2 On the Possible Hidden Use of a Higher Internal Precision \\ 3.3 Revision of the IEEE 754-2008 Standard \\ 3.4 Floating-Point Hardware in Current Processors \\ 3.4.1 The common hardware denominator \\ 3.4.2 Fused multiply-add \\ 3.4.3 Extended precision and 128-bit formats \\ 3.4.4 Rounding and precision control \\ 3.4.5 SIMD instructions \\ 3.4.6 Binary16 (half-precision) support \\ 3.4.7 Decimal arithmetic \\ 3.4.8 The legacy x87 processor \\ 3.5 Floating-Point Hardware in Recent Graphics Processing Units \\ 3.6 IEEE Support in Programming Languages \\ 3.7 Checking the Environment \\ 3.7.1 MACHAR \\ 3.7.2 Paranoia \\ \ldots{} \\ Basic Properties and Algorithms \\ Enhanced Floating-Point Sums, Dot Products, and Polynomial Values \\ Languages and Compilers \\ Algorithms for the Basic Operations \\ Hardware Implementation of Floating-Point Arithmetic \\ Software Implementation of Floating-Point Arithmetic \\ Evaluating Floating-Point Elementary Functions \\ Complex Numbers \\ Interval Arithmetic \\ Verifying Floating-Point Algorithms \\ Extending the Precision

entry:
@Book{Muller:2018:HFP,
  author =       "Jean-Michel Muller and Nicolas Brunie and Florent de
                 Dinechin and Claude-Pierre Jeannerod and Mioara Joldes
                 and Vincent Lef{\`e}vre and Guillaume Melquiond and
                 Nathalie Revol and Serge Torres",
  title =        "Handbook of Floating-Point Arithmetic",
  publisher =    pub-BIRKHAUSER,
  address =      pub-BIRKHAUSER:adr,
  edition =      "Second",
  year =         "2018",
  DOI =          "https://doi.org/10.1007/978-3-319-76526-6",
  ISBN =         "3-319-76525-6, 3-319-76526-4 (e-book)",
  ISBN-13 =      "978-3-319-76525-9, 978-3-319-76526-6 (e-book)",
  LCCN =         "QA76.9.C62",
  bibdate =      "Fri Jun 1 06:59:01 MDT 2018",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This handbook aims to provide a complete overview of
                 modern floating-point arithmetic. This includes a
                 detailed treatment of the current (IEEE-754) and next
                 (preliminarily called IEEE-754R) standards for
                 floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  shorttableofcontents = "Introduction / 3--14 \\
                 Definitions and Basic Notions / 15--45 \\
                 Floating-Point Formats and Environment / 47--93 \\
                 Basic Properties and Algorithms / 97--162 \\
                 Enhanced Floating-Point Sums, Dot Products, and
                 Polynomial Values / 163--192 \\
                 Languages and Compilers / 193--230 \\
                 Algorithms for the Basic Operations / 233--266 \\
                 Hardware Implementation of Floating-Point Arithmetic /
                 267--320 \\
                 Software Implementation of Floating-Point Arithmetic /
                 321--374 \\
                 Evaluating Floating-Point Elementary Functions /
                 375--433 \\
                 Complex Numbers / 437--452 \\
                 Interval Arithmetic / 453--477 \\
                 Verifying Floating-Point Algorithms / 479--511 \\
                 Extending the Precision / 513--552",
  subject =      "Floating-point arithmetic; Handbooks, manuals, etc;
                 Computer arithmetic; COMPUTERS / Computer Literacy;
                 COMPUTERS / Computer Science; COMPUTERS / Data
                 Processing; COMPUTERS / Hardware / General; COMPUTERS /
                 Information Technology; COMPUTERS / Machine Theory;
                 COMPUTERS / Reference.",
  tableofcontents = "Intro \\
                 Contents \\
                 List of Figures \\
                 List of Tables \\
                 Preface \\
                 I Introduction, Basic Definitions, and Standards \\
                 1 Introduction \\
                 1.1 Some History \\
                 1.2 Desirable Properties \\
                 1.3 Some Strange Behaviors \\
                 1.3.1 Some famous bugs \\
                 1.3.2 Difficult problems \\
                 1.3.2.1 A sequence that seems to converge to a wrong
                 limit \\
                 1.3.2.2 The Chaotic Bank Society \\
                 1.3.2.3 Rump's example \\
                 2 Definitions and Basic Notions \\
                 2.1 Floating-Point Numbers \\
                 2.1.1 Main definitions \\
                 2.1.2 Normalized representations, normal and subnormal
                 numbers \\
                 2.1.3 A note on underflow \\
                 2.1.4 Special floating-point data \\
                 2.2 Rounding \\
                 2.2.1 Rounding functions \\
                 2.2.2 Useful properties \\
                 2.3 Tools for Manipulating Floating-Point Errors \\
                 2.3.1 Relative error due to rounding \\
                 2.3.2 The ulp function \\
                 2.3.3 Link between errors in ulps and relative errors
                 \\
                 2.3.3.1 Converting from errors in ulps to relative
                 errors \\
                 2.3.3.2 Converting from relative errors to errors in
                 ulps \\
                 2.3.3.3 Loss of information during these conversions
                 \\
                 2.3.4 An example: iterated products \\
                 2.4 The Fused Multiply-Add (FMA) Instruction \\
                 2.5 Exceptions \\
                 2.6 Lost and Preserved Properties of Real Arithmetic
                 \\
                 2.7 Note on the Choice of the Radix \\
                 2.7.1 Representation errors \\
                 2.7.2 A case for radix 10 \\
                 2.8 Reproducibility \\
                 3 Floating-Point Formats and Environment \\
                 3.1 The IEEE 754-2008 Standard \\
                 3.1.1 Formats \\
                 3.1.1.1 Binary interchange format encodings \\
                 3.1.1.2 Decimal interchange format encodings \\
                 3.1.1.3 Larger formats \\
                 3.1.1.4 Extended and extendable precisions \\
                 3.1.1.5 Little-endian, big-endian \\
                 3.1.2 Attributes and rounding \\
                 3.1.2.1 Rounding direction attributes \\
                 3.1.2.2 Alternate exception-handling attributes \\
                 3.1.2.3 Preferred width attributes \\
                 3.1.2.4 Value-changing optimization attributes \\
                 3.1.2.5 Reproducibility attributes \\
                 3.1.3 Operations specified by the standard \\
                 3.1.3.1 Arithmetic operations and square root \\
                 3.1.3.2 Remainders \\
                 3.1.3.3 Preferred exponent for arithmetic operations in
                 the decimal format \\
                 3.1.3.4 scaleB and logB \\
                 3.1.3.5 Miscellaneous \\
                 3.1.4 Comparisons \\
                 3.1.5 Conversions to/from string representations \\
                 3.1.6 Default exception handling \\
                 3.1.6.1 Invalid operation \\
                 3.1.6.2 Division by zero \\
                 3.1.6.3 Overflow \\
                 3.1.6.4 Underflow \\
                 3.1.6.5 Inexact \\
                 3.1.7 Special values \\
                 3.1.7.1 NaN: Not a Number \\
                 3.1.7.2 Arithmetic of infinities and zeros \\
                 3.1.8 Recommended functions \\
                 3.2 On the Possible Hidden Use of a Higher Internal
                 Precision \\
                 3.3 Revision of the IEEE 754-2008 Standard \\
                 3.4 Floating-Point Hardware in Current Processors \\
                 3.4.1 The common hardware denominator \\
                 3.4.2 Fused multiply-add \\
                 3.4.3 Extended precision and 128-bit formats \\
                 3.4.4 Rounding and precision control \\
                 3.4.5 SIMD instructions \\
                 3.4.6 Binary16 (half-precision) support \\
                 3.4.7 Decimal arithmetic \\
                 3.4.8 The legacy x87 processor \\
                 3.5 Floating-Point Hardware in Recent Graphics
                 Processing Units \\
                 3.6 IEEE Support in Programming Languages \\
                 3.7 Checking the Environment \\
                 3.7.1 MACHAR \\
                 3.7.2 Paranoia \\
                 \ldots{} \\
                 Basic Properties and Algorithms \\
                 Enhanced Floating-Point Sums, Dot Products, and
                 Polynomial Values \\
                 Languages and Compilers \\
                 Algorithms for the Basic Operations \\
                 Hardware Implementation of Floating-Point Arithmetic
                 \\
                 Software Implementation of Floating-Point Arithmetic
                 \\
                 Evaluating Floating-Point Elementary Functions \\
                 Complex Numbers \\
                 Interval Arithmetic \\
                 Verifying Floating-Point Algorithms \\
                 Extending the Precision",
}


bibtype: article
filename: fparith.bib
label: Munoz-Coreas:2018:CQO
author: Edgard Munoz-Coreas and Himanshu Thapliyal
title: T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm
journal: j-JETC
volume: 14
number: 3
pages: 36:1--36:15
month: oct
monthnumber: 10
year: 2018
DOI: https://doi.org/10.1145/3264816
ISSN: 1550-4832 (print), 1550-4840 (electronic) OR 15504832 (print), 15504840 (electronic)
ISSNL: 1550-4832 OR 15504832
bibdate: Thu Nov 1 16:44:41 MDT 2018
bibtimestamp: 2018.11.01 16:44:41 MDT
fjournal: ACM Journal on Emerging Technologies in Computing Systems (JETC)
acknowledgement: ack-nhfb
articleno: 36
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J967
rawauthor: Edgard Mu{\~n}oz-Coreas and Himanshu Thapliyal
rawtitle: {T}-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jetc.bib

abstract:
Quantum circuits for basic mathematical functions such as the square root are required to implement scientific computing algorithms on quantum computers. Quantum circuits that are based on Clifford+T gates can easily be made fault tolerant, but the T gate is very costly to implement. As a result, reducing T-count has become an important optimization goal. Further, quantum circuits with many qubits are difficult to realize, making designs that save qubits and produce no garbage outputs desirable. In this work, we present a T-count optimized quantum square root circuit with only $ 2 s n + 1 $ qubits and no garbage output. To make a fair comparison against existing work, the Bennett's garbage removal scheme is used to remove garbage output from existing works. We determined that our proposed design achieves an average T-count savings of 43.44%, 98.95%, 41.06%, and 20.28% as well as qubit savings of 85.46%, 95.16%, 90.59%, and 86.77% compared to existing works.

rawabstract:
Quantum circuits for basic mathematical functions such as the square root are required to implement scientific computing algorithms on quantum computers. Quantum circuits that are based on Clifford+T gates can easily be made fault tolerant, but the T gate is very costly to implement. As a result, reducing T-count has become an important optimization goal. Further, quantum circuits with many qubits are difficult to realize, making designs that save qubits and produce no garbage outputs desirable. In this work, we present a T-count optimized quantum square root circuit with only $ 2 s n + 1 $ qubits and no garbage output. To make a fair comparison against existing work, the Bennett's garbage removal scheme is used to remove garbage output from existing works. We determined that our proposed design achieves an average T-count savings of 43.44\%, 98.95\%, 41.06\%, and 20.28\% as well as qubit savings of 85.46\%, 95.16\%, 90.59\%, and 86.77\% compared to existing works.

entry:
@Article{Munoz-Coreas:2018:CQO,
  author =       "Edgard Mu{\~n}oz-Coreas and Himanshu Thapliyal",
  title =        "{T}-count and Qubit Optimized Quantum Circuit Design
                 of the Non-Restoring Square Root Algorithm",
  journal =      j-JETC,
  volume =       "14",
  number =       "3",
  pages =        "36:1--36:15",
  month =        oct,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3264816",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Nov 1 16:44:41 MDT 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Quantum circuits for basic mathematical functions such
                 as the square root are required to implement scientific
                 computing algorithms on quantum computers. Quantum
                 circuits that are based on Clifford+T gates can easily
                 be made fault tolerant, but the T gate is very costly
                 to implement. As a result, reducing T-count has become
                 an important optimization goal. Further, quantum
                 circuits with many qubits are difficult to realize,
                 making designs that save qubits and produce no garbage
                 outputs desirable. In this work, we present a T-count
                 optimized quantum square root circuit with only $ 2 s n
                 + 1 $ qubits and no garbage output. To make a fair
                 comparison against existing work, the Bennett's garbage
                 removal scheme is used to remove garbage output from
                 existing works. We determined that our proposed design
                 achieves an average T-count savings of 43.44\%,
                 98.95\%, 41.06\%, and 20.28\% as well as qubit savings
                 of 85.46\%, 95.16\%, 90.59\%, and 86.77\% compared to
                 existing works.",
  acknowledgement = ack-nhfb,
  articleno =    "36",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:2018:TFP
author: Alberto Nannarelli
title: Tunable Floating-Point for Energy Efficient Accelerators
crossref: Tenca:2018:PIS
pages: 29--36
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464797
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli
rawtitle: Tunable Floating-Point for Energy Efficient Accelerators
abstract:
In this work, we address the design of an on-chip accelerator for Machine Learning and other computation-demanding applications with a Tunable Floating-Point (TFP) precision. The precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of a given algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient. We focus on floating-point multiplication, which is the most power demanding arithmetic operation.

keywords:
Adders; ARITH-25; computation-demanding applications; Decoding; Dynamic range; electronic engineering computing; energy efficient accelerators; floating point arithmetic; floating-point multiplication; floating-point representation; Hardware; learning (artificial intelligence); Machine Learning; Machine learning; on-chip accelerator; Standards; System-on-chip; TFP precision; Tunable Floating-Point precision

rawabstract:
In this work, we address the design of an on-chip accelerator for Machine Learning and other computation-demanding applications with a Tunable Floating-Point (TFP) precision. The precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of a given algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient. We focus on floating-point multiplication, which is the most power demanding arithmetic operation.

entry:
@InProceedings{Nannarelli:2018:TFP,
  author =       "Alberto Nannarelli",
  title =        "Tunable Floating-Point for Energy Efficient
                 Accelerators",
  crossref =     "Tenca:2018:PIS",
  pages =        "29--36",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464797",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this work, we address the design of an on-chip
                 accelerator for Machine Learning and other
                 computation-demanding applications with a Tunable
                 Floating-Point (TFP) precision. The precision can be
                 chosen for a single operation by selecting a specific
                 number of bits for significand and exponent in the
                 floating-point representation. By tuning the precision
                 of a given algorithm to the minimum precision achieving
                 an acceptable target error, we can make the computation
                 more power efficient. We focus on floating-point
                 multiplication, which is the most power demanding
                 arithmetic operation.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-25; computation-demanding applications;
                 Decoding; Dynamic range; electronic engineering
                 computing; energy efficient accelerators; floating
                 point arithmetic; floating-point multiplication;
                 floating-point representation; Hardware; learning
                 (artificial intelligence); Machine Learning; Machine
                 learning; on-chip accelerator; Standards;
                 System-on-chip; TFP precision; Tunable Floating-Point
                 precision",
}


bibtype: article
filename: fparith.bib
label: Numahata:2018:RAS
author: Dai Numahata and Hiroshi Sekigawa
title: Robust algorithms for sparse interpolation of multivariate polynomials
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 52
number: 4
pages: 145--147
month: dec
monthnumber: 12
year: 2018
DOI: https://doi.org/10.1145/3338637.3338648
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Wed Oct 23 07:34:18 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigsam.bib
bibtimestamp: 2019.10.23 07:34:18 MDT
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: Dai Numahata and Hiroshi Sekigawa
rawtitle: Robust algorithms for sparse interpolation of multivariate polynomials
abstract:
We consider the problem of symbolic-numeric sparse interpolation of multivariate polynomials. The problem is to find the coefficients and the exponents of a given black-box polynomial $ f(x_1, ldots , x_n) = sum _j = 1^t c_j x_1^d_j, 1 ldots x_n^d_j, n in mathbb C[x_1, ldots , x_n] (c_j neq 0) $ by evaluating the value of $ f(x_1, ldots , x_n) $ at any point in $ mathbb C^n $ in floating-point arithmetic and by using the conditions of the input.

rawabstract:
We consider the problem of symbolic-numeric sparse interpolation of multivariate polynomials. The problem is to find the coefficients and the exponents of a given black-box polynomial $ f(x_1, \ldots, x_n) = \sum_{j = 1}^t c_j x_1^{d_{j, 1}} \ldots {} x_n^{d_{j, n}} \in \mathbb {C}[x_1, \ldots, x_n] (c_j \neq 0) $ by evaluating the value of $ f(x_1, \ldots, x_n) $ at any point in $ \mathbb {C}^n $ in floating-point arithmetic and by using the conditions of the input.

entry:
@Article{Numahata:2018:RAS,
  author =       "Dai Numahata and Hiroshi Sekigawa",
  title =        "Robust algorithms for sparse interpolation of
                 multivariate polynomials",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "52",
  number =       "4",
  pages =        "145--147",
  month =        dec,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3338637.3338648",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Wed Oct 23 07:34:18 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigsam.bib",
  abstract =     "We consider the problem of symbolic-numeric sparse
                 interpolation of multivariate polynomials. The problem
                 is to find the coefficients and the exponents of a
                 given black-box polynomial $ f(x_1, \ldots, x_n) =
                 \sum_{j = 1}^t c_j x_1^{d_{j, 1}} \ldots {} x_n^{d_{j,
                 n}} \in \mathbb {C}[x_1, \ldots, x_n] (c_j \neq 0) $ by
                 evaluating the value of $ f(x_1, \ldots, x_n) $ at any
                 point in $ \mathbb {C}^n $ in floating-point arithmetic
                 and by using the conditions of the input.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Oliveira:2018:MLB
author: Thomaz Oliveira and Julio Lopez and Francisco Rodriguez-Henriquez
title: The Montgomery ladder on binary elliptic curves
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 241--258
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0163-8
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0163-8
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Thomaz Oliveira and Julio L{\'o}pez and Francisco Rodr{\'{\i}}guez-Henr{\'{\i}}quez
rawtitle: The {Montgomery} ladder on binary elliptic curves
entry:
@Article{Oliveira:2018:MLB,
  author =       "Thomaz Oliveira and Julio L{\'o}pez and Francisco
                 Rodr{\'{\i}}guez-Henr{\'{\i}}quez",
  title =        "The {Montgomery} ladder on binary elliptic curves",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "241--258",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0163-8",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0163-8",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: inproceedings
filename: fparith.bib
label: Podobas:2018:HIP
author: Artur Podobas and Satoshi Matsuoka
editor: IEEE
booktitle: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
title: Hardware Implementation of POSITs and Their Application in FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 138--145
year: 2018
DOI: https://doi.org/10.1109/IPDPSW.2018.00029
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Artur Podobas and Satoshi Matsuoka
rawbooktitle: {2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}
raweditor: {IEEE}
rawtitle: Hardware Implementation of {POSITs} and Their Application in {FPGAs}
entry:
@InProceedings{Podobas:2018:HIP,
  author =       "Artur Podobas and Satoshi Matsuoka",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Parallel and Distributed
                 Processing Symposium Workshops (IPDPSW)}",
  title =        "Hardware Implementation of {POSITs} and Their
                 Application in {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "138--145",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/IPDPSW.2018.00029",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Popescu:2018:FPN
author: Valentina Popescu and Marcel Nassar and Xin Wang and Evren Tumer and Tristania Webb
title: Flexpoint: Predictive Numerics for Deep Learning
crossref: Tenca:2018:PIS
pages: 1--4
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464801
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Valentina Popescu and Marcel Nassar and Xin Wang and Evren Tumer and Tristania Webb
rawtitle: {Flexpoint}: Predictive Numerics for Deep Learning
abstract:
Deep learning has been undergoing rapid growth in recent years thanks to its state-of-the-art performance across a wide range of real-world applications. Traditionally neural networks were trained in IEEE-754 binary64 or binary32 format, a common practice in general scientific computing. However, the unique computational requirements of deep neural network training workloads allow for much more efficient and inexpensive alternatives, unleashing a new wave of numerical innovations powering specialized computing hardware. We previously presented Flexpoint, a blocked fixed-point data type combined with a novel predictive exponent management algorithm designed to support training of deep networks without modifications, aiming at a seamless replacement of the binary32 widely in practice today. We showed that Flexpoint with 16-bit mantissa and 5-bit shared exponent (flex16+S) achieved numerical parity to binary32 in training a number of convolutional neural networks. In the current paper we review the continuing trend of predictive numerics enhancing deep neural network training in specialized computing devices such as the Intel Nervana Neural Network Processor.

keywords:
ARITH-25; blocked fixed-point data type; convolution; convolutional neural networks; deep learning; Deep Learning; deep neural network training; feedforward neural nets; Flexpoint; floating point arithmetic; general scientific computing; Hardware; learning (artificial intelligence); Machine learning; Market research; Neural networks; Neural Networks; Prediction algorithms; predictive exponent management algorithm; Tensile stress; Training

rawabstract:
Deep learning has been undergoing rapid growth in recent years thanks to its state-of-the-art performance across a wide range of real-world applications. Traditionally neural networks were trained in IEEE-754 binary64 or binary32 format, a common practice in general scientific computing. However, the unique computational requirements of deep neural network training workloads allow for much more efficient and inexpensive alternatives, unleashing a new wave of numerical innovations powering specialized computing hardware. We previously presented Flexpoint, a blocked fixed-point data type combined with a novel predictive exponent management algorithm designed to support training of deep networks without modifications, aiming at a seamless replacement of the binary32 widely in practice today. We showed that Flexpoint with 16-bit mantissa and 5-bit shared exponent (flex16+S) achieved numerical parity to binary32 in training a number of convolutional neural networks. In the current paper we review the continuing trend of predictive numerics enhancing deep neural network training in specialized computing devices such as the Intel Nervana Neural Network Processor.

entry:
@InProceedings{Popescu:2018:FPN,
  author =       "Valentina Popescu and Marcel Nassar and Xin Wang and
                 Evren Tumer and Tristania Webb",
  title =        "{Flexpoint}: Predictive Numerics for Deep Learning",
  crossref =     "Tenca:2018:PIS",
  pages =        "1--4",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464801",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Deep learning has been undergoing rapid growth in
                 recent years thanks to its state-of-the-art performance
                 across a wide range of real-world applications.
                 Traditionally neural networks were trained in IEEE-754
                 binary64 or binary32 format, a common practice in
                 general scientific computing. However, the unique
                 computational requirements of deep neural network
                 training workloads allow for much more efficient and
                 inexpensive alternatives, unleashing a new wave of
                 numerical innovations powering specialized computing
                 hardware. We previously presented Flexpoint, a blocked
                 fixed-point data type combined with a novel predictive
                 exponent management algorithm designed to support
                 training of deep networks without modifications, aiming
                 at a seamless replacement of the binary32 widely in
                 practice today. We showed that Flexpoint with 16-bit
                 mantissa and 5-bit shared exponent (flex16+S) achieved
                 numerical parity to binary32 in training a number of
                 convolutional neural networks. In the current paper we
                 review the continuing trend of predictive numerics
                 enhancing deep neural network training in specialized
                 computing devices such as the Intel Nervana Neural
                 Network Processor.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; blocked fixed-point data type; convolution;
                 convolutional neural networks; deep learning; Deep
                 Learning; deep neural network training; feedforward
                 neural nets; Flexpoint; floating point arithmetic;
                 general scientific computing; Hardware; learning
                 (artificial intelligence); Machine learning; Market
                 research; Neural networks; Neural Networks; Prediction
                 algorithms; predictive exponent management algorithm;
                 Tensile stress; Training",
}


bibtype: article
filename: fparith.bib
label: Radford:2018:FIF
author: Peter Radford
title: A ``Feature'' of IBM 360 Floating Point
journal: Resurrection: The Journal of the Computer Conservation Society
number: 82
pages: ??--??
month: Summer
year: 2018
ISSN: 0958-7403 OR 09587403
ISSNL: 0958-7403 OR 09587403
bibdate: Mon Jul 27 18:19:06 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.07.27 18:19:06 ???
URL: https://computerconservationsociety.org/resurrection/res82.htm#f
acknowledgement: ack-nhfb
rawauthor: Peter Radford
rawtitle: A {``Feature''} of {IBM 360} Floating Point
remark:
The short article discusses the impact of hexadecimal normalization on representation of decimal input values, and ends with the statement: ``32-bit floating point remains an elephant trap for programmers to this day.''.

entry:
@Article{Radford:2018:FIF,
  author =       "Peter Radford",
  title =        "A {``Feature''} of {IBM 360} Floating Point",
  journal =      "Resurrection: The Journal of the Computer Conservation
                 Society",
  volume =       "??",
  number =       "82",
  pages =        "??--??",
  month =        "Summer",
  year =         "2018",
  ISSN =         "0958-7403",
  ISSN-L =       "0958-7403",
  bibdate =      "Mon Jul 27 18:19:06 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://computerconservationsociety.org/resurrection/res82.htm#f",
  acknowledgement = ack-nhfb,
  remark =       "The short article discusses the impact of hexadecimal
                 normalization on representation of decimal input
                 values, and ends with the statement: ``32-bit floating
                 point remains an elephant trap for programmers to this
                 day.''.",
}


bibtype: inproceedings
filename: fparith.bib
label: Ram:2018:FVF
author: Ravi Ram and Adam Elkins and Adnan Pratama and Sasa Stamenkovic and Sven Beyer and Sergio Marchese
booktitle: Proceedings of DVCon US 2018
title: Formal Verification of Floating-Point Hardware with Assertion-Based VIP
pages: 1--9
day: 5
month: jun
monthnumber: 6
year: 2018
bibdate: Fri Sep 28 06:20:43 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.09.28 06:20:43 ???
acknowledgement: ack-nhfb
rawauthor: Ravi Ram and Adam Elkins and Adnan Pratama and Sasa Stamenkovic and Sven Beyer and Sergio Marchese
rawbooktitle: Proceedings of {DVCon US 2018}
rawtitle: Formal Verification of Floating-Point Hardware with Assertion-Based {VIP}
URL:
https://www.onespin.com/fileadmin/user_upload/pdf/whitepapers/Formal_Verification_of_Floating_Point_Hardware.pdf

abstract:
Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the famous 1994 Intel Pentium bug, many companies have investigated and successfully applied formal methods to this task. However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; and significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to set up a formal testbench and uncover deep corner-case bugs with minimal effort. Results from industrial applications are reported.

rawabstract:
Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the famous 1994 Intel Pentium bug, many companies have investigated and successfully applied formal methods to this task. However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; and significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to set up a formal testbench and uncover deep corner-case bugs with minimal effort. Results from industrial applications are reported.

entry:
@InProceedings{Ram:2018:FVF,
  author =       "Ravi Ram and Adam Elkins and Adnan Pratama and Sasa
                 Stamenkovic and Sven Beyer and Sergio Marchese",
  editor =       "????",
  booktitle =    "Proceedings of {DVCon US 2018}",
  title =        "Formal Verification of Floating-Point Hardware with
                 Assertion-Based {VIP}",
  publisher =    "????",
  address =      "????",
  pages =        "1--9",
  day =          "5",
  month =        jun,
  year =         "2018",
  bibdate =      "Fri Sep 28 06:20:43 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.onespin.com/fileadmin/user_upload/pdf/whitepapers/Formal_Verification_of_Floating_Point_Hardware.pdf",
  abstract =     "Hardware for integer or fixed-point arithmetic is
                 relatively simple to design, at least at the
                 register-transfer level. If the range of values and
                 precision that can be represented with these formats is
                 not sufficient for the target application,
                 floating-point hardware might be required.
                 Unfortunately, floating-point units are complex to
                 design, and notoriously challenging to verify. Since
                 the famous 1994 Intel Pentium bug, many companies have
                 investigated and successfully applied formal methods to
                 this task. However, solutions often rely on a mix of
                 the following: hard-to-use formal tools; highly
                 specialized engineering skills; availability of a
                 suitable executable model of the hardware; and
                 significant, design-specific engineering effort. In
                 this paper, we present an alternative floating-point
                 hardware verification approach based on a reusable,
                 IEEE 754 compliant SystemVerilog arithmetic library.
                 While not addressing all verification challenges, this
                 method enables engineers to set up a formal testbench
                 and uncover deep corner-case bugs with minimal effort.
                 Results from industrial applications are reported.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Reddy:2018:DAD
author: K. Manikantta Reddy and M. H. Vasantha and Y. B. Nithin Kumar and Devesh Dwivedi
booktitle: 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
title: Design of Approximate Dividers for Error Tolerant Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--9
month: aug
monthnumber: 8
year: 2018
DOI: https://doi.org/10.1109/mwscas.2018.8623909
bibdate: Wed Dec 20 07:39:14 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:39:14 ???
acknowledgement: ack-nhfb
rawauthor: K. Manikantta Reddy and M. H. Vasantha and Y. B. Nithin Kumar and Devesh Dwivedi
rawbooktitle: {2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)}
rawtitle: Design of Approximate Dividers for Error Tolerant Applications
entry:
@InProceedings{Reddy:2018:DAD,
  author =       "K. Manikantta Reddy and M. H. Vasantha and Y. B.
                 Nithin Kumar and Devesh Dwivedi",
  booktitle =    "{2018 IEEE 61st International Midwest Symposium on
                 Circuits and Systems (MWSCAS)}",
  title =        "Design of Approximate Dividers for Error Tolerant
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  month =        aug,
  year =         "2018",
  DOI =          "https://doi.org/10.1109/mwscas.2018.8623909",
  bibdate =      "Wed Dec 20 07:39:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Reyhani-Masoleh:2018:NAR
author: Arash Reyhani-Masoleh and Mostafa Taha and Doaa Ashmawy
title: New Area Record for the AES Combined S-Box / Inverse S-Box
crossref: Tenca:2018:PIS
pages: 145--152
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464780
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Arash Reyhani-Masoleh and Mostafa Taha and Doaa Ashmawy
rawtitle: New Area Record for the {AES} Combined {S}-Box\slash Inverse {S}-Box
abstract:
The AES combined S-box/inverse S-box is a single construction that is shared between the encryption and decryption data paths of the AES. The currently most compact implementation of the AES combined S-box/inverse S-box is Canright's design, introduced back in 2005. Since then, the research community has introduced several optimizations over the S-box only, however the combined S-boxlinverse S-box received little attention. In this paper, we propose a new AES combined S-boxlinverse S-box design that is both smaller and faster than Canright's design. We achieve this goal by proposing to use new tower field and optimizing each and every block inside the combined architecture for this field. Our complexity analysis and ASIC implementation results in the CMOS STM 65nm and NanGate 15nm technologies show that our design outperforms the counterparts in terms of area and speed.

keywords:
AES combined S-box-inverse S-box; application specific integrated circuits; ARITH-25; Canright design; circuit optimisation; CMOS STM; Complexity theory; Computer architecture; cryptography; decryption data paths; Encryption; encryption data paths; Generators; Logic gates; Multiplexing; NanGate; Poles and towers; size 15.0 nm; size 65.0 nm

rawabstract:
The AES combined S-box/inverse S-box is a single construction that is shared between the encryption and decryption data paths of the AES. The currently most compact implementation of the AES combined S-box/inverse S-box is Canright's design, introduced back in 2005. Since then, the research community has introduced several optimizations over the S-box only, however the combined S-boxlinverse S-box received little attention. In this paper, we propose a new AES combined S-boxlinverse S-box design that is both smaller and faster than Canright's design. We achieve this goal by proposing to use new tower field and optimizing each and every block inside the combined architecture for this field. Our complexity analysis and ASIC implementation results in the CMOS STM 65nm and NanGate 15nm technologies show that our design outperforms the counterparts in terms of area and speed.

entry:
@InProceedings{Reyhani-Masoleh:2018:NAR,
  author =       "Arash Reyhani-Masoleh and Mostafa Taha and Doaa
                 Ashmawy",
  title =        "New Area Record for the {AES} Combined {S}-Box\slash
                 Inverse {S}-Box",
  crossref =     "Tenca:2018:PIS",
  pages =        "145--152",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464780",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The AES combined S-box/inverse S-box is a single
                 construction that is shared between the encryption and
                 decryption data paths of the AES. The currently most
                 compact implementation of the AES combined
                 S-box/inverse S-box is Canright's design, introduced
                 back in 2005. Since then, the research community has
                 introduced several optimizations over the S-box only,
                 however the combined S-boxlinverse S-box received
                 little attention. In this paper, we propose a new AES
                 combined S-boxlinverse S-box design that is both
                 smaller and faster than Canright's design. We achieve
                 this goal by proposing to use new tower field and
                 optimizing each and every block inside the combined
                 architecture for this field. Our complexity analysis
                 and ASIC implementation results in the CMOS STM 65nm
                 and NanGate 15nm technologies show that our design
                 outperforms the counterparts in terms of area and
                 speed.",
  acknowledgement = ack-nhfb,
  keywords =     "AES combined S-box-inverse S-box; application specific
                 integrated circuits; ARITH-25; Canright design; circuit
                 optimisation; CMOS STM; Complexity theory; Computer
                 architecture; cryptography; decryption data paths;
                 Encryption; encryption data paths; Generators; Logic
                 gates; Multiplexing; NanGate; Poles and towers; size
                 15.0 nm; size 65.0 nm",
}


bibtype: inproceedings
filename: fparith.bib
label: Riedy:2018:AAO
author: Jason Riedy and James Demmel
title: Augmented Arithmetic Operations Proposed for IEEE-754 2018
crossref: Tenca:2018:PIS
pages: 45--52
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464813
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Jason Riedy and James Demmel
rawtitle: Augmented Arithmetic Operations Proposed for {IEEE-754 2018}
abstract:
Algorithms for extending arithmetic precision through compensated summation or arithmetics like double-double rely on operations commonly called twoSum and twoProduct. The current draft of the IEEE 754 standard specifies these operations under the names augmentedAddition and augmentedMultiplication. These operations were included after three decades of experience because of a motivating new use: bitwise reproducible arithmetic. Standardizing the operations provides a hardware acceleration target that can provide at least a 33% speed improvements in reproducible dot product, placing reproducible dot product almost within a factor of two of common dot product. This paper provides history and motivation for standardizing these operations. We also define the operations, explain the rationale for all the specific choices, and provide parameterized test cases for new boundary behaviors.

keywords:
Acceleration; ARITH-25; arithmetic precision; augmented arithmetic operations; bitwise reproducible arithmetic; common dot product; floating point arithmetic; Hardware; hardware acceleration target; History; IEEE 754 standard; IEEE standards; IEEE-754 2018; Libraries; Magnetic heads; reproducible dot product; Software; Standards

rawabstract:
Algorithms for extending arithmetic precision through compensated summation or arithmetics like double-double rely on operations commonly called twoSum and twoProduct. The current draft of the IEEE 754 standard specifies these operations under the names augmentedAddition and augmentedMultiplication. These operations were included after three decades of experience because of a motivating new use: bitwise reproducible arithmetic. Standardizing the operations provides a hardware acceleration target that can provide at least a 33\% speed improvements in reproducible dot product, placing reproducible dot product almost within a factor of two of common dot product. This paper provides history and motivation for standardizing these operations. We also define the operations, explain the rationale for all the specific choices, and provide parameterized test cases for new boundary behaviors.

entry:
@InProceedings{Riedy:2018:AAO,
  author =       "Jason Riedy and James Demmel",
  title =        "Augmented Arithmetic Operations Proposed for {IEEE-754
                 2018}",
  crossref =     "Tenca:2018:PIS",
  pages =        "45--52",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464813",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Algorithms for extending arithmetic precision through
                 compensated summation or arithmetics like double-double
                 rely on operations commonly called twoSum and
                 twoProduct. The current draft of the IEEE 754 standard
                 specifies these operations under the names
                 augmentedAddition and augmentedMultiplication. These
                 operations were included after three decades of
                 experience because of a motivating new use: bitwise
                 reproducible arithmetic. Standardizing the operations
                 provides a hardware acceleration target that can
                 provide at least a 33\% speed improvements in
                 reproducible dot product, placing reproducible dot
                 product almost within a factor of two of common dot
                 product. This paper provides history and motivation for
                 standardizing these operations. We also define the
                 operations, explain the rationale for all the specific
                 choices, and provide parameterized test cases for new
                 boundary behaviors.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; ARITH-25; arithmetic precision;
                 augmented arithmetic operations; bitwise reproducible
                 arithmetic; common dot product; floating point
                 arithmetic; Hardware; hardware acceleration target;
                 History; IEEE 754 standard; IEEE standards; IEEE-754
                 2018; Libraries; Magnetic heads; reproducible dot
                 product; Software; Standards",
}


bibtype: article
filename: fparith.bib
label: Rodriguez-Henriquez:2018:SIH
author: Francisco Rodriguez-Henriquez and Erkay Savas
title: Special issue in honor of Peter Lawrence Montgomery
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 185--187
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0168-3
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Francisco Rodr{\'\i}guez-Henr{\'\i}quez and Erkay Savas
rawtitle: Special issue in honor of {Peter Lawrence Montgomery}
URL:
http://link.springer.com/article/10.1007/s13389-017-0168-3; https://link.springer.com/content/pdf/10.1007/s13389-017-0168-3.pdf

entry:
@Article{Rodriguez-Henriquez:2018:SIH,
  author =       "Francisco Rodr{\'\i}guez-Henr{\'\i}quez and Erkay
                 Savas",
  title =        "Special issue in honor of {Peter Lawrence
                 Montgomery}",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "185--187",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0168-3",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0168-3;
                 https://link.springer.com/content/pdf/10.1007/s13389-017-0168-3.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Saadat:2018:MBM
author: Hassaan Saadat and Haseeb Bokhari and Sri Parameswaran
title: Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
journal: j-IEEE-TRANS-CAD-ICS
volume: 37
number: 11
pages: 2623--2635
month: nov
monthnumber: 11
year: 2018
CODEN: ITCSDI
DOI: https://doi.org/10.1109/tcad.2018.2857262
ISSN: 0278-0070 (print), 1937-4151 (electronic) OR 02780070 (print), 19374151 (electronic)
ISSNL: 0278-0070 OR 02780070
bibdate: Wed Dec 20 07:46:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:46:25 ???
fjournal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43
rawauthor: Hassaan Saadat and Haseeb Bokhari and Sri Parameswaran
rawtitle: Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
entry:
@Article{Saadat:2018:MBM,
  author =       "Hassaan Saadat and Haseeb Bokhari and Sri
                 Parameswaran",
  title =        "Minimally Biased Multipliers for Approximate Integer
                 and Floating-Point Multiplication",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "37",
  number =       "11",
  pages =        "2623--2635",
  month =        nov,
  year =         "2018",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/tcad.2018.2857262",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Wed Dec 20 07:46:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}


bibtype: article
filename: fparith.bib
label: Sanchez-Stern:2018:FRC
author: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
title: Finding root causes of floating point error
journal: j-SIGPLAN
volume: 53
number: 4
pages: 256--269
month: apr
monthnumber: 4
year: 2018
CODEN: SINODQ
DOI: https://doi.org/10.1145/3296979.3192411
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Wed Oct 16 14:12:57 MDT 2019
bibtimestamp: 2019.10.16 14:12:57 MDT
fjournal: ACM SIGPLAN Notices
remark: PLDI '18 proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
rawtitle: Finding root causes of floating point error
abstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level languages like C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to simplified program fragments whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries and tracking error across function boundaries and through the heap.

rawabstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level languages like C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to simplified program fragments whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries and tracking error across function boundaries and through the heap.

entry:
@Article{Sanchez-Stern:2018:FRC,
  author =       "Alex Sanchez-Stern and Pavel Panchekha and Sorin
                 Lerner and Zachary Tatlock",
  title =        "Finding root causes of floating point error",
  journal =      j-SIGPLAN,
  volume =       "53",
  number =       "4",
  pages =        "256--269",
  month =        apr,
  year =         "2018",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3296979.3192411",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Wed Oct 16 14:12:57 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "Floating-point arithmetic plays a central role in
                 science, engineering, and finance by enabling
                 developers to approximate real arithmetic. To address
                 numerical issues in large floating-point applications,
                 developers must identify root causes, which is
                 difficult because floating-point errors are generally
                 non-local, non-compositional, and non-uniform. This
                 paper presents Herbgrind, a tool to help developers
                 identify and address root causes in numerical code
                 written in low-level languages like C/C++ and Fortran.
                 Herbgrind dynamically tracks dependencies between
                 operations and program outputs to avoid false positives
                 and abstracts erroneous computations to simplified
                 program fragments whose improvement can reduce output
                 error. We perform several case studies applying
                 Herbgrind to large, expert-crafted numerical programs
                 and show that it scales to applications spanning
                 hundreds of thousands of lines, correctly handling the
                 low-level details of modern floating point hardware and
                 mathematical libraries and tracking error across
                 function boundaries and through the heap.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "PLDI '18 proceedings.",
}


bibtype: article
filename: fparith.bib
label: Savas:2018:MI
author: Erkay Savas and Cetin Kaya Koc
title: Montgomery inversion
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 201--210
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0161-x
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0161-x
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Erkay Savas and {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: {Montgomery} inversion
entry:
@Article{Savas:2018:MI,
  author =       "Erkay Savas and {\c{C}}etin Kaya Ko{\c{c}}",
  title =        "{Montgomery} inversion",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "201--210",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0161-x",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0161-x",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Schneider:2018:USS
author: D. Schneider
title: U.S. supercomputing strikes back
journal: j-IEEE-SPECTRUM
volume: 55
number: 1
pages: 52--53
month: jan
monthnumber: 1
year: 2018
CODEN: IEESAM
DOI: https://doi.org/10.1109/MSPEC.2018.8241739
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Sat Jan 18 07:02:09 2020
bibtimestamp: 2020.01.18 07:02:09 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: D. Schneider
rawtitle: {U.S.} supercomputing strikes back
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib; https://www.math.utah.edu/pub/tex/bib/super.bib

keywords:
Companies; Computational modeling; floating-point operations; Games; Hardware; parallel machines; Payloads; petaflops; Rockets; Supercomputers; Titan machine; U.S. high-performance computing community; U.S. supercomputing

entry:
@Article{Schneider:2018:USS,
  author =       "D. Schneider",
  title =        "{U.S.} supercomputing strikes back",
  journal =      j-IEEE-SPECTRUM,
  volume =       "55",
  number =       "1",
  pages =        "52--53",
  month =        jan,
  year =         "2018",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2018.8241739",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Sat Jan 18 07:02:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/super.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "Companies; Computational modeling; floating-point
                 operations; Games; Hardware; parallel machines;
                 Payloads; petaflops; Rockets; Supercomputers; Titan
                 machine; U.S. high-performance computing community;
                 U.S. supercomputing",
}


bibtype: article
filename: fparith.bib
label: Seo:2018:FBM
author: Jungjoo Seo and Kunsoo Park
title: Fast batch modular exponentiation with common-multiplicand multiplication
journal: j-INFO-PROC-LETT
volume: 129
pages: 5--10
month: jan
monthnumber: 1
year: 2018
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Mon Oct 30 08:48:26 MDT 2017
bibtimestamp: 2017.10.30 08:48:26 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0020019017301527
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Jungjoo Seo and Kunsoo Park
rawtitle: Fast batch modular exponentiation with common-multiplicand multiplication
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib

entry:
@Article{Seo:2018:FBM,
  author =       "Jungjoo Seo and Kunsoo Park",
  title =        "Fast batch modular exponentiation with
                 common-multiplicand multiplication",
  journal =      j-INFO-PROC-LETT,
  volume =       "129",
  number =       "??",
  pages =        "5--10",
  month =        jan,
  year =         "2018",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Mon Oct 30 08:48:26 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0020019017301527",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: misc
filename: fparith.bib
label: Trader:2018:ICS
author: Tiffany Trader
title: Inventor Claims to Have Solved Floating Point Error Problem
pages: 5--10
day: 17
month: jan
monthnumber: 1
year: 2018
bibdate: Fri Mar 23 19:13:03 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.23 19:13:03 ???
URL: https://www.hpcwire.com/2018/01/17/inventor-claims-solved-floating-point-error-problem/
acknowledgement: ack-nhfb
howpublished: HPC Web site.
rawauthor: Tiffany Trader
rawtitle: Inventor Claims to Have Solved Floating Point Error Problem
note:
From the HPC editor: ``After this article was published, a number of readers raised concerns about the originality of Jorgensen's techniques, noting the existence of prior art going back years. Specifically, there is precedent in John Gustafson's work on unums and interval arithmetic both at Sun and in his 2015 book, booktitle The End of Error, which was published 19 months before Jorgensen's patent application was filed. ''

rawnote:
From the HPC editor: ``After this article was published, a number of readers raised concerns about the originality of Jorgensen's techniques, noting the existence of prior art going back years. Specifically, there is precedent in John Gustafson's work on unums and interval arithmetic both at Sun and in his 2015 book, \booktitle{The End of Error}, which was published 19 months before Jorgensen's patent application was filed. ''

entry:
@Misc{Trader:2018:ICS,
  author =       "Tiffany Trader",
  title =        "Inventor Claims to Have Solved Floating Point Error
                 Problem",
  howpublished = "HPC Web site.",
  day =          "17",
  month =        jan,
  year =         "2018",
  bibdate =      "Fri Mar 23 19:13:03 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "From the HPC editor: ``After this article was
                 published, a number of readers raised concerns about
                 the originality of Jorgensen's techniques, noting the
                 existence of prior art going back years. Specifically,
                 there is precedent in John Gustafson's work on unums
                 and interval arithmetic both at Sun and in his 2015
                 book, \booktitle{The End of Error}, which was published
                 19 months before Jorgensen's patent application was
                 filed. ''",
  URL =          "https://www.hpcwire.com/2018/01/17/inventor-claims-solved-floating-point-error-problem/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Villalba-Moreno:2018:FHF
author: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonzalez-Navarro
title: Fast HUB Floating-point Adder for FPGA
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 66
number: 6
pages: 1028--1032
month: jun
monthnumber: 6
year: 2018
DOI: https://doi.org/10.1109/TCSII.2018.2873194
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Mon Feb 10 08:25:14 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 08:25:14 ???
URL: https://ieeexplore.ieee.org/document/8477084
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
keywords: HUB (Half-Unit-Biased) floating-point format
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Circuits Syst., II Express Briefs
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonz{\'a}lez-Navarro
rawtitle: Fast {HUB} Floating-point Adder for {FPGA}
entry:
@Article{Villalba-Moreno:2018:FHF,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Sonia
                 Gonz{\'a}lez-Navarro",
  title =        "Fast {HUB} Floating-point Adder for {FPGA}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "66",
  number =       "6",
  pages =        "1028--1032",
  month =        jun,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/TCSII.2018.2873194",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Mon Feb 10 08:25:14 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/8477084",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Circuits Syst., II Express Briefs",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "HUB (Half-Unit-Biased) floating-point format",
}


bibtype: article
filename: fparith.bib
label: Villalba-Moreno:2018:URH
author: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonzalez-Navarro
title: Unbiased Rounding for HUB Floating-Point Addition
journal: j-IEEE-TRANS-COMPUT
volume: 67
number: 9
pages: 1359--1365
month: sep
monthnumber: 9
year: 2018
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2807429
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Mar 15 08:10:13 2019
bibtimestamp: 2019.03.15 08:10:13 ???
URL: https://ieeexplore.ieee.org/document/8300633/
fjournal: IEEE Transactions on Computers
keywords: HUB (Half-Unit-Biased) floating-point format
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonz{\'a}lez-Navarro
rawtitle: Unbiased Rounding for {HUB} Floating-Point Addition
entry:
@Article{Villalba-Moreno:2018:URH,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Sonia
                 Gonz{\'a}lez-Navarro",
  title =        "Unbiased Rounding for {HUB} Floating-Point Addition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "67",
  number =       "9",
  pages =        "1359--1365",
  month =        sep,
  year =         "2018",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2807429",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Mar 15 08:10:13 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://ieeexplore.ieee.org/document/8300633/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "HUB (Half-Unit-Biased) floating-point format",
}


bibtype: article
filename: fparith.bib
label: Walczyk:2018:IAF
author: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cieslinski
title: Improving the accuracy of the fast inverse square root algorithm
journal: arXiv.org
pages: 1--21
day: 17
month: feb
monthnumber: 2
year: 2018
DOI: https://doi.org/10.48550/arXiv.1802.06302
bibdate: Wed Dec 20 07:55:45 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:55:45 ???
URL: https://arxiv.org/abs/1802.06302
acknowledgement: ack-nhfb
rawauthor: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cie{\'s}li{\'n}ski
rawtitle: Improving the accuracy of the fast inverse square root algorithm
abstract:
We present improved algorithms for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithms are much more accurate than the famous fast inverse square root algorithm and have the same or similar computational cost. The main idea of our work consists in modifying the Newton-Raphson method and demanding that the maximal error is as small as possible. Such modification is possible when the distribution of Newton-Raphson corrections is not symmetric (e.g., if they are non-positive functions).

rawabstract:
We present improved algorithms for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithms are much more accurate than the famous fast inverse square root algorithm and have the same or similar computational cost. The main idea of our work consists in modifying the Newton-Raphson method and demanding that the maximal error is as small as possible. Such modification is possible when the distribution of Newton-Raphson corrections is not symmetric (e.g., if they are non-positive functions).

entry:
@Article{Walczyk:2018:IAF,
  author =       "Cezary J. Walczyk and Leonid V. Moroz and Jan L.
                 Cie{\'s}li{\'n}ski",
  title =        "Improving the accuracy of the fast inverse square root
                 algorithm",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--21",
  day =          "17",
  month =        feb,
  year =         "2018",
  DOI =          "https://doi.org/10.48550/arXiv.1802.06302",
  bibdate =      "Wed Dec 20 07:55:45 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1802.06302",
  abstract =     "We present improved algorithms for fast calculation of
                 the inverse square root for single-precision
                 floating-point numbers. The algorithms are much more
                 accurate than the famous fast inverse square root
                 algorithm and have the same or similar computational
                 cost. The main idea of our work consists in modifying
                 the Newton-Raphson method and demanding that the
                 maximal error is as small as possible. Such
                 modification is possible when the distribution of
                 Newton-Raphson corrections is not symmetric (e.g., if
                 they are non-positive functions).",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2018:TDN
author: Naigang Wang and Jungwook Choi and Daniel Brand and Chia-Yu Chen and Kailash Gopalakrishnan
editor: S. Bengio and others
title: Training Deep Neural Networks with 8-bit Floating Point Numbers
publisher: Curran Associates, Inc.
pages: 7675--7684
year: 2018
bibdate: Wed Dec 19 19:17:48 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.12.19 19:17:48 ???
acknowledgement: ack-nhfb
rawauthor: Naigang Wang and Jungwook Choi and Daniel Brand and Chia-Yu Chen and Kailash Gopalakrishnan
raweditor: S. Bengio and others
rawtitle: Training {Deep Neural Networks} with 8-bit Floating Point Numbers
booktitle:
Proceedings of the 32nd Conference on Neural Information Processing Systems (NeurIPS 2018), Montreal, Canada

URL:
https://arxiv.org/abs/1812.08011; https://papers.nips.cc/paper/7994-training-deep-neural-networks-with-8-bit-floating-point-numbers.pdf

abstract:
The state-of-the-art hardware platforms for training Deep Neural Networks (DNNs) are moving from traditional single precision (32-bit) computations towards 16 bits of precision in large part due to the high energy efficiency and smaller bit storage associated with using reduced-precision representations. However, unlike inference, training with numbers represented with less than 16 bits has been challenging due to the need to maintain fidelity of the gradient computations during back-propagation. Here we demonstrate, for the first time, the successful training of DNNs using 8-bit floating point numbers while fully maintaining the accuracy on a spectrum of Deep Learning models and datasets. In addition to reducing the data and computation precision to 8 bits, we also successfully reduce the arithmetic precision for additions (used in partial product accumulation and weight updates) from 32 bits to 16 bits through the introduction of a number of key ideas including chunk-based accumulation and floating point stochastic rounding. The use of these novel techniques lays the foundation for a new generation of hardware training platforms with the potential for 2--4 $ times $ improved throughput over today's systems.

remark:
The 8-bit floating-point format, FP8, has 1 sign bit, 5 exponent bits, and 2 significand bits (1,5,2); the 16-bit format, FP16, has 1 sign bit, 6 exponent bits, and 9 significand bits (1,6,9). There is no mention of Infinity, NaN, signed zeros, or FMA operations

rawabstract:
The state-of-the-art hardware platforms for training Deep Neural Networks (DNNs) are moving from traditional single precision (32-bit) computations towards 16 bits of precision in large part due to the high energy efficiency and smaller bit storage associated with using reduced-precision representations. However, unlike inference, training with numbers represented with less than 16 bits has been challenging due to the need to maintain fidelity of the gradient computations during back-propagation. Here we demonstrate, for the first time, the successful training of DNNs using 8-bit floating point numbers while fully maintaining the accuracy on a spectrum of Deep Learning models and datasets. In addition to reducing the data and computation precision to 8 bits, we also successfully reduce the arithmetic precision for additions (used in partial product accumulation and weight updates) from 32 bits to 16 bits through the introduction of a number of key ideas including chunk-based accumulation and floating point stochastic rounding. The use of these novel techniques lays the foundation for a new generation of hardware training platforms with the potential for 2--4 $ \times $ improved throughput over today's systems.

rawbooktitle:
{Proceedings of the 32nd Conference on Neural Information Processing Systems (NeurIPS 2018), Montr{\'e}al, Canada}

entry:
@InProceedings{Wang:2018:TDN,
  author =       "Naigang Wang and Jungwook Choi and Daniel Brand and
                 Chia-Yu Chen and Kailash Gopalakrishnan",
  editor =       "S. Bengio and others",
  booktitle =    "{Proceedings of the 32nd Conference on Neural
                 Information Processing Systems (NeurIPS 2018),
                 Montr{\'e}al, Canada}",
  title =        "Training {Deep Neural Networks} with 8-bit Floating
                 Point Numbers",
  publisher =    "Curran Associates, Inc.",
  address =      "????",
  pages =        "7675--7684",
  year =         "2018",
  bibdate =      "Wed Dec 19 19:17:48 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1812.08011;
                 https://papers.nips.cc/paper/7994-training-deep-neural-networks-with-8-bit-floating-point-numbers.pdf",
  abstract =     "The state-of-the-art hardware platforms for training
                 Deep Neural Networks (DNNs) are moving from traditional
                 single precision (32-bit) computations towards 16 bits
                 of precision in large part due to the high energy
                 efficiency and smaller bit storage associated with
                 using reduced-precision representations. However,
                 unlike inference, training with numbers represented
                 with less than 16 bits has been challenging due to the
                 need to maintain fidelity of the gradient computations
                 during back-propagation. Here we demonstrate, for the
                 first time, the successful training of DNNs using 8-bit
                 floating point numbers while fully maintaining the
                 accuracy on a spectrum of Deep Learning models and
                 datasets. In addition to reducing the data and
                 computation precision to 8 bits, we also successfully
                 reduce the arithmetic precision for additions (used in
                 partial product accumulation and weight updates) from
                 32 bits to 16 bits through the introduction of a number
                 of key ideas including chunk-based accumulation and
                 floating point stochastic rounding. The use of these
                 novel techniques lays the foundation for a new
                 generation of hardware training platforms with the
                 potential for 2--4 $ \times $ improved throughput over
                 today's systems.",
  acknowledgement = ack-nhfb,
  remark =       "The 8-bit floating-point format, FP8, has 1 sign bit,
                 5 exponent bits, and 2 significand bits (1,5,2); the
                 16-bit format, FP16, has 1 sign bit, 6 exponent bits,
                 and 9 significand bits (1,6,9). There is no mention of
                 Infinity, NaN, signed zeros, or FMA operations",
  xxpages =      "1--10",
}


bibtype: inproceedings
filename: fparith.bib
label: Yang:2018:OMP
editor: IEEE
booktitle: 2018 IEEE International Conference on Intelligence and Safety for Robotics (ISR)
title: An Omnidirectional and Movable Palletizing Robot based on Computer Vision Positing
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 423--428
year: 2018
DOI: https://doi.org/10.1109/IISR.2018.8535688
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2018 IEEE International Conference on Intelligence and Safety for Robotics (ISR)}
raweditor: {IEEE}
rawtitle: An Omnidirectional and Movable Palletizing Robot based on Computer Vision Positing
author:
Xiong Yang and Hongbin Zhang and Tianyou Cheng and Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian Lu and Zhiguo Lu and Yajing Shen

rawauthor:
Xiong Yang and Hongbin Zhang and Tianyou Cheng and Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian Lu and Zhiguo Lu and Yajing Shen

entry:
@InProceedings{Yang:2018:OMP,
  author =       "Xiong Yang and Hongbin Zhang and Tianyou Cheng and
                 Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian
                 Lu and Zhiguo Lu and Yajing Shen",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Conference on Intelligence
                 and Safety for Robotics (ISR)}",
  title =        "An Omnidirectional and Movable Palletizing Robot based
                 on Computer Vision Positing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "423--428",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/IISR.2018.8535688",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Adams:2019:RRP
author: Ulf Adams
title: Ryu revisited: tt printf floating point conversion
journal: j-PACMPL
volume: 3
number: OOPSLA
pages: 169:1--169:23
month: oct
monthnumber: 10
year: 2019
DOI: https://doi.org/10.1145/3360595
ISSN: 2475-1421 OR 24751421
bibdate: Fri Aug 7 19:22:30 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2020.08.07 19:22:30 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3360595
fjournal: Proceedings of the ACM on Programming Languages
keywords: base conversion
acknowledgement: ack-nhfb
articleno: 169
journalURL: https://pacmpl.acm.org/
rawauthor: Ulf Adams
rawtitle: {Ry{\=u}} revisited: {\tt printf} floating point conversion
abstract:
Ryu Printf is a new algorithm to convert floating-point numbers to decimal strings according to the tt printf tt %f, tt %e, and tt %g formats: tt %f generates `full' output (integer part of the input, dot, configurable number of digits), tt %e generates scientific output (one leading digit, dot, configurable number of digits, exponent), and tt %g generates the shorter of the two. Ryu's Printf is based on the Ryu algorithm, which converts binary floating-point numbers to the shortest equivalent decimal floating-point representation. We provide quantitative evidence that Ryu Printf is between 3.8 and 55 times faster than existing tt printf implementations.par Furthermore, we show that both Ryu and Ryu Printf generalize to arbitrary number bases. This finding implies the existence of a fast algorithm to convert from base-10 to base-2, as long as the maximum precision of the input is known a priori.

rawabstract:
Ry{\=u} Printf is a new algorithm to convert floating-point numbers to decimal strings according to the {\tt printf} {\tt \%f}, {\tt \%e}, and {\tt \%g} formats: {\tt \%f} generates `full' output (integer part of the input, dot, configurable number of digits), {\tt \%e} generates scientific output (one leading digit, dot, configurable number of digits, exponent), and {\tt \%g} generates the shorter of the two. Ry{\=u}'s Printf is based on the Ry{\=u} algorithm, which converts binary floating-point numbers to the shortest equivalent decimal floating-point representation. We provide quantitative evidence that Ry{\=u} Printf is between 3.8 and 55 times faster than existing {\tt printf} implementations.\par Furthermore, we show that both Ry{\=u} and Ry{\=u} Printf generalize to arbitrary number bases. This finding implies the existence of a fast algorithm to convert from base-10 to base-2, as long as the maximum precision of the input is known a priori.

entry:
@Article{Adams:2019:RRP,
  author =       "Ulf Adams",
  title =        "{Ry{\=u}} revisited: {\tt printf} floating point
                 conversion",
  journal =      j-PACMPL,
  volume =       "3",
  number =       "OOPSLA",
  pages =        "169:1--169:23",
  month =        oct,
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3360595",
  ISSN =         "2475-1421",
  bibdate =      "Fri Aug 7 19:22:30 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3360595",
  abstract =     "Ry{\=u} Printf is a new algorithm to convert
                 floating-point numbers to decimal strings according to
                 the {\tt printf} {\tt \%f}, {\tt \%e}, and {\tt \%g}
                 formats: {\tt \%f} generates `full' output (integer
                 part of the input, dot, configurable number of digits),
                 {\tt \%e} generates scientific output (one leading
                 digit, dot, configurable number of digits, exponent),
                 and {\tt \%g} generates the shorter of the two.
                 Ry{\=u}'s Printf is based on the Ry{\=u} algorithm,
                 which converts binary floating-point numbers to the
                 shortest equivalent decimal floating-point
                 representation. We provide quantitative evidence that
                 Ry{\=u} Printf is between 3.8 and 55 times faster than
                 existing {\tt printf} implementations.\par

                 Furthermore, we show that both Ry{\=u} and Ry{\=u}
                 Printf generalize to arbitrary number bases. This
                 finding implies the existence of a fast algorithm to
                 convert from base-10 to base-2, as long as the maximum
                 precision of the input is known a priori.",
  acknowledgement = ack-nhfb,
  articleno =    "169",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
  keywords =     "base conversion",
}


